JPH09266255A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the semiconductor device capable of avoiding the dispersion in the drain current (Ids) and the breakdown strength characteristics in the semiconductor device wherein a MOS in LDD(lightly doped drain) structured to be driven at low voltage and a high breakdown strength transistor consolidated with each other. SOLUTION: A sidewall oxide film 22 is formed on a gate electrode sidewall 17 by etching back CVD oxide film by RIE later to form a photoresist covering a MOS transistor 1 forming region further to form the second LDD diffused layer 21 of a high breakdown strength MOS transistor 2. Besides, a photoresist 23 to offset a gate electrode 17 with a source drain diffused layer 24 on a drain 2a of a high breakdown strength MOS transistor 2 later to form the source drain diffused layer 24 by ion implantation. Through these procedures, the title semiconductor device including the high breakdown strength MOS transistor can be manufactured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a normal LDD structure MOS transistor and a high voltage MOS transistor such as a booster circuit are mounted together.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits using highly integrated MOS transistors are known as LDD (Lightly D
In general, a MOS transistor having an open drain structure and driven at a low voltage is used. In recent years, there has also been a demand for a semiconductor device in which a booster circuit including a high breakdown voltage MOS transistor is mixedly mounted on a semiconductor integrated circuit having the MOS transistor as a basic configuration to form one chip. A conventional example of a method of manufacturing a semiconductor device having the LDD structure, in which an ordinary MOS transistor and a high voltage MOS transistor are mounted together, will be described with reference to FIG.

First, as shown in FIG. 3A, a field oxide film 12 is formed on the surface of a semiconductor substrate 11 by LOCOS (L
ocal Oxidation on Silico
n) Selectively formed by the method or the like. After that, normal MO
The well 12 of the S-transistor 1 and the well 13 of the high breakdown voltage MOS transistor 2 are ion-implanted using the patterned photoresist as a mask, and are sequentially formed.
After that, a channel stopper 15 is formed under the field oxide film 12 around the high breakdown voltage MOS transistor 2 by ion implantation using a photoresist as a mask. The end of the channel stopper 15 and the field oxide film 12
The distance A at the end of is the distance at which the high breakdown voltage MOS transistor 1 can secure a predetermined breakdown voltage. Next, the field oxide film 1
A gate oxide film 16 is formed in the element formation region surrounded by 2. After that, the normal MOS transistor 1 and high-voltage MO
A gate electrode 17 made of a doped polysilicon film or the like is formed on the S transistor 2. Next, a photoresist 18 is applied and patterned so that the photoresist 18 remains only in the high breakdown voltage MOS transistor 2. After that, ion implantation is performed using the photoresist 18, the field oxide film 12 and the gate electrode 17 as a mask. hand,
The first LDD diffusion layer 19 is formed of a low concentration impurity.

Next, as shown in FIG. 3B, a photoresist 20 is applied, the photoresist 20 is left in the normal MOS transistor 1, and the photoresist 20 is removed in the high breakdown voltage MOS transistor 2. Patterning is performed, and ion implantation is performed using the photoresist 20, the field oxide film 12 and the gate electrode 17 as a mask, and the second LDD diffusion layer 2 with a low concentration of impurities is formed.
Form one.

Next, as shown in FIG. 3C, after a CVD oxide film is deposited by the CVD method or the like, etch back is performed by anisotropic plasma etching by the RIE method to form side walls on the sidewalls of the gate electrode 17. The wall oxide film 22 is formed. After that, a photoresist 23 is applied and a high breakdown voltage MO is applied.
Part of the drain 2a of the S transistor 2 and the gate electrode 1
The photoresist is patterned so that the photoresist 23 is left on a part of 7. At this time, the distance B between the end of the photoresist 23 of the drain 2a and the side wall of the gate electrode 17 is set to a distance at which the drain 2a breakdown voltage of the high breakdown voltage MOS transistor 1 becomes a predetermined breakdown voltage. Next, photoresist 2
3, the gate electrode 17 having the field oxide film 12 and the sidewall oxide film 22 is used as a mask for ion implantation, and the source / drain diffusion layer 24 is formed by high-concentration impurities.
To form By doing so, the gate electrode 17 of the high breakdown voltage MOS transistor 2 and the source / drain diffusion layer 24 of the drain 2a are in a state where a large offset is taken, unlike an ordinary MOS transistor. After that, a manufacturing process according to a conventional method is performed to manufacture a semiconductor device.

However, with the above manufacturing method, a conventional MOS
When manufacturing a semiconductor device in which the transistor 1 and the high breakdown voltage MOS transistor 2 are mounted together, the RIE etchback for forming the sidewall oxide film 22 on the side wall of the gate electrode 17 is usually performed under overetching conditions, while the sidewall oxide film is formed. 22 CVD oxide film and semiconductor substrate 1
As shown in FIG. 4A, the first LDD diffusion layer 19 and the second LDD diffusion layer 2 of the semiconductor substrate 11 may not be sufficiently large because the etching selection ratio to the single crystal silicon 1 is not sufficiently large.
1 is etched. As a result, when the first LDD diffusion layer 19 and the second LDD diffusion layer 21 become shallower, the source / drain diffusion layer 24 formed by the next ion implantation becomes as shown in FIG. 4B. , The first LDD
It becomes deeper than the diffusion layer 19 and the second LDD diffusion layer 21.

When the high breakdown voltage MOS transistor 2 is manufactured in the above-mentioned state, the second breakdown voltage of the high breakdown voltage MOS transistor 2 is increased.
And the drain current Id increases.
s decreases. Further, since the source / drain diffusion layer 24 is deeper than the second LDD diffusion layer, the impurity profile of the PN junction becomes steep and the breakdown voltage of the PN junction is lowered. In addition, the second by the etch back by the above RIE
Since the etching amount of the LDD diffusion layer differs depending on slight fluctuations in manufacturing conditions, there arises a problem that variations in Ids and withstand voltage characteristics of the high withstand voltage MOS transistor 2 occur.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems in the method of manufacturing a semiconductor device. That is, an object of the present invention is to adopt an LDD structure, a MOS transistor driven at a low voltage, and a high breakdown voltage MO.
It is an object of the present invention to provide a method of manufacturing a semiconductor device in which S transistors are mixedly mounted without variations in Ids or withstand voltage characteristics of high breakdown voltage MOS transistors.

[0009]

A method of manufacturing a semiconductor device according to the present invention is proposed to solve the above-mentioned problems, and adopts an LDD structure, and a MOS transistor driven at a low voltage and a high breakdown voltage MOS transistor. In a method of manufacturing a semiconductor device in which a plurality of semiconductor devices are mounted together, a step of forming a gate electrode, a patterning step of forming a photoresist in a formation region of a high breakdown voltage MOS transistor, and a first LDD in a formation region of a MOS transistor driven at a low voltage. An ion implantation step of forming a diffusion layer, a step of forming a side wall oxide film on the side wall of the gate electrode, and a photoresist is formed in the formation region of the MOS transistor driven at a low voltage after the step of forming the side wall oxide film. A patterning step of forming and a high breakdown voltage M after the patterning step.
Ion implantation step of forming a second LDD diffusion layer in the formation region of the OS transistor, and patterning step of forming a photoresist for offsetting the source / drain diffusion layer formed in the drain region of the high breakdown voltage MOS transistor with respect to the gate electrode And an ion implantation step of forming a source / drain diffusion layer. Further, the projected range of ion implantation for forming the second LDD diffusion layer described above can be made larger than the projected range of ion implantation for forming the source / drain diffusion layer.

According to the present invention, the sidewall oxide film is formed on the sidewall of the gate electrode, and the photoresist is patterned to leave the photoresist in the normal MOS transistor.
In order to carry out the ion implantation step of forming the LDD diffusion layer, the depth of the second LDD diffusion layer and the impurity profile are kept constant even if the surface of the semiconductor substrate is etched at the time of etching back the sidewall oxide film formation. By making the projected range of the ion implantation for forming the second LDD diffusion layer larger than the projected range of the ion implantation for forming the source / drain diffusion layers, the steepness of the impurity profile of the PN junction is eliminated, and so on. It is possible to manufacture a semiconductor device without variation in withstand voltage characteristics.

[0011]

Embodiments of the present invention will be described below with reference to the accompanying drawings. Components similar to those in FIGS. 3 and 4 referred to in the description of the prior art are denoted by the same reference numerals.

In this embodiment, an ordinary MO having an LDD structure is used.
This is an example in which the present invention is applied to a method of manufacturing a semiconductor device in which an S transistor and a high voltage MOS transistor are mounted together, and this will be described with reference to FIGS. 1 and 2. First, FIG.
As shown in (a), the field oxide film 12 is selectively formed on the surface of the N-type semiconductor substrate 11 by the LOCOS method or the like. Then, the well 13 of the normal MOS transistor 1 and the well 14 of the high breakdown voltage MOS transistor 2 are used as a mask to perform ion implantation of P-type impurities, and are sequentially formed by diffusion by heat treatment thereafter. After that, the high voltage MOS transistor 2
A channel stopper 15 is formed by ion implantation of P-type impurities using a photoresist as a mask under the field oxide film 12 around the region. The distance A between the end of the channel stopper 15 and the end of the field oxide film 12 is high withstand voltage M.
The distance at which the OS transistor 2 can secure a predetermined breakdown voltage is, for example, about 1 μm. Next, the field oxide film 1
A gate oxide film 16 having a film thickness of about 30 nm is formed in the element formation region surrounded by 2. The gate oxide film 16 is
In order to secure the performance of the normal MOS transistor 1, the gate oxide film thickness and the high breakdown voltage MO of the normal MOS transistor 1 are secured.
The gate oxide film thickness of the S-transistor 2 may be changed to form the former by about 9 nm and the latter by about 30 nm by two thermal oxidation steps.

After that, the gate electrode 17 made of, for example, a doped polysilicon film is formed on the normal MOS transistor 1 and the high breakdown voltage MOS transistor 2. Next, a photoresist 18 is applied to the high breakdown voltage MOS transistor 2
Patterning is performed so that the photoresist 18 remains only in the first region, and then N-type impurity ions are implanted using the photoresist 18, the field oxide film 12 and the gate electrode 17 as a mask.
The LDD diffusion layer 19 is formed. In addition, this first LD
The ion implantation conditions for the D diffusion layer 19 are, for example, As ions, the implantation energy is about 25 KeV, and the dose amount is 2E13 / cm ² .

Next, as shown in FIG. 1B, the photoresist 18 is removed, a CVD oxide film is deposited by the CVD method or the like, and then an etch back is performed by anisotropic plasma etching by the RIE method. A sidewall oxide film 22 is formed on the sidewall of the gate electrode 17. After that, a photoresist 20 is applied, the photoresist 20 is left on the normal MOS transistor 1, and the high breakdown voltage MOS transistor 2 is applied.
Is patterned so that the photoresist 20 is removed, and the photoresist 20 and the field oxide film 1 are
2 and the gate electrode 17 are used as a mask to perform ion implantation of an N-type impurity to form a second LD with a low-concentration impurity.
The D diffusion layer 21 is formed. This second LDD diffusion layer 21
The ion implantation conditions for formation are, for example, P ions, implantation energy of about 60 KeV, and dose of 8E12 /.
cm ² . The ion implantation for forming the second LDD diffusion layer 21 may be performed by using the large-angle ion implantation method and performing the large-angle ion implantation at two degrees on the drain side and the source side. In the ion implantation at the time of forming the second LDD diffusion layer 21, the implantation energy is larger than that at the time of forming the first LDD diffusion layer 19, so that the projection range of the ion implantation becomes large, and the second LDD diffusion layer 21 is formed. The depth of is getting deeper.

Next, as shown in FIG. 1C, a photoresist 23 is applied and patterned so that the photoresist 23 remains on a part of the drain 2a of the high breakdown voltage MOS transistor 2 and a part of the gate electrode 17. do. At this time, the end of the photoresist 23 of the drain 2a and the gate electrode 17
The distance B to the side wall is, for example, about 1 μm, which is a distance at which the breakdown voltage of the drain 2a of the high breakdown voltage MOS transistor 1 becomes a predetermined breakdown voltage. After that, ion implantation is performed using the gate electrode 17 having the photoresist 23, the field oxide film 12 and the sidewall oxide film 22 as a mask to form a source / drain diffusion layer 24 of high concentration impurities. As the ion implantation conditions for forming the source / drain diffusion layer 24, for example, As ions are used, the implantation energy is about 35 KeV, and the dose amount is 5E15 / cm ² . By doing so, the gate electrode 17 of the high breakdown voltage MOS transistor 2 and the source / drain diffusion layer 24 of the drain 2a are formed.
Differs from a normal MOS transistor in that a large offset is taken. After that, a manufacturing process according to a conventional method is performed to manufacture a semiconductor device.

The CVD oxide film described in the conventional example is replaced with R.
The side wall oxide film 22 is etched back by IE.
When the surface of the semiconductor substrate 11 is etched in the step of forming the structure shown in FIG. 1B and FIG.
It becomes like (a) and FIG.2 (b). That is, by etching back by RIE, the first LDD diffusion layer 19 of the normal MOS transistor 1 is etched to be shallow as in the conventional example, and the second LDD diffusion layer 21 of the high breakdown voltage MOS transistor is formed on the semiconductor substrate. The surface of 11 is also shown in FIG.
However, since the ion implantation for forming the second LDD diffusion layer 21 is performed after the etching back step for forming the sidewall oxide film 22, the etching is performed as shown in FIG.
As shown in, the depth of the second LDD diffusion layer 21 is formed to a predetermined depth. Further, as shown in FIG. 2B, in the normal MOS transistor 1 after the ion implantation for forming the source / drain diffusion layer 24, the first MOS transistor 1 is formed similarly to the conventional example.
The depth of the source / drain diffusion layer 24 becomes deeper than the depth of the LDD diffusion layer 19 and the source / drain diffusion layer 24 is formed in the second LDD diffusion layer 21 having a predetermined depth in the high breakdown voltage MOS transistor 2. It will be in the formed state. Here, the second LDD diffusion layer 21 has a predetermined depth, and the projection range of ion implantation for forming the source / drain diffusion layer 24 is the projection range of ion implantation for forming the second LDD diffusion layer 21. Higher withstand voltage MO due to smaller size
In the drain 2a portion of the S transistor 2, the impurity profile of the PN junction portion does not become steep, and the PN junction breakdown voltage does not decrease.

According to the manufacturing method described above, since the second LDD diffusion layer 21 of the high breakdown voltage MOS transistor 2 is formed after the etching back by RIE for forming the sidewall oxide film 22, the source / source at the time of etching back is formed. Even if the amount of etching on the surface of the semiconductor substrate 11 on which the drain is formed varies, the depth of the second LDD diffusion layer 21 is kept constant. In addition, the projection range of the ion implantation for forming the source / drain diffusion layer 24 is set to the second LDD diffusion layer 2
The second LDD diffusion layer 21 is always formed to have a constant depth by making it smaller than the projected range of the ion implantation for forming 1.
The source / drain diffusion layer 24 can be formed therein. Therefore, the drain 2 of the high breakdown voltage MOS transistor 2
The resistance and the impurity profile of the second LDD diffusion layer 21 of the a portion are constant, and the variation of Ids is eliminated. In addition, since the source / drain diffusion layer 24 is always formed in the second LDD diffusion layer 21, the impurity profile of the PN junction does not become steep and the breakdown voltage does not decrease. Even if there is variation in the amount of etching on the surface of the semiconductor substrate 11 due to the etch back, the variation in withstand voltage does not occur.

The present invention has been described with reference to the embodiments.
The present invention is not limited to this embodiment. For example, although a doped polysilicon film is used as the gate electrode, a high melting point metal polycide film such as PolySi / WSi or a high melting point metal silicide film such as WSi ₂ or TiSi ₂ may be used. In the above-described embodiment,
Ordinary M that adopts LDD structure of N-type MOS transistor
The method of manufacturing the semiconductor device in which the OS transistor and the high voltage MOS transistor are mounted together has been described.
Obviously, it can be applied to a semiconductor device using a transistor. In addition, within the scope of the technical concept of the present invention, the process apparatus and process conditions can be appropriately changed.

[0019]

As is apparent from the above description, the method of manufacturing a semiconductor device, which adopts the LDD structure of the present invention and in which a MOS transistor driven at a low voltage and a high breakdown voltage MOS transistor are mounted together, is a method of manufacturing a high breakdown voltage MOS transistor. LD of 2
By performing the ion implantation for forming the D diffusion layer after forming the sidewall oxide film and making the projected range of this ion implantation larger than the projected range of the ion implantation for forming the source / drain diffusion layer, Ids and withstand voltage It is possible to manufacture a semiconductor device including a high breakdown voltage MOS transistor without variations.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor device, which illustrates the steps of an embodiment to which the present invention is applied, in the order of steps. FIG.
A state in which the first LDD diffusion layer is formed in the S transistor,
(B) is a state in which the second LDD diffusion layer is formed in the high breakdown voltage MOS transistor, and (c) is a state in which the source / drain diffusion layer is formed.

FIG. 2 is a schematic cross-sectional view of a semiconductor device illustrating subsequent steps when the surface of a semiconductor substrate is etched by overetching in an etch back step of an example to which the present invention is applied, in which (a) shows a high breakdown voltage. Second to MOS transistor
The LDD diffusion layer is formed, and (b) is the state where the source / drain diffusion layer is formed.

3A to 3C illustrate steps of a conventional semiconductor device in order of steps,
1A is a schematic cross-sectional view of a semiconductor device, in which FIG. 1A is a state in which a first LDD diffusion layer is formed in an ordinary MOS transistor, FIG.
Shows a state where the second LDD diffusion layer is formed in the high breakdown voltage MOS transistor, and (c) shows a state where the source / drain diffusion layer is formed.

FIG. 4 is a schematic cross-sectional view of a semiconductor device illustrating subsequent steps when a surface of a semiconductor substrate is etched by overetching in a conventional semiconductor device etch-back step. FIG. The state where the oxide film is formed, and the state (b) is the state where the source / drain diffusion layer is formed.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... MOS transistor, 2 ... High breakdown voltage MOS transistor, 2a ... Drain, 2b ... Source, 11 ... Semiconductor substrate, 12 ... Field oxide film, 13, 14 ... Well, 1
5 ... Channel stopper, 16 ... Gate oxide film, 17 ... Gate electrode, 18, 20, 23 ... Photoresist, 19 ...
First LDD diffusion layer, 21 ... Second LDD diffusion layer, 22
... Sidewall oxide film, 24 ... Source / drain diffusion layer

Claims (2)

[Claims] 1. An M having an LDD structure and driven at a low voltage.
In a method of manufacturing a semiconductor device in which an OS transistor and a high breakdown voltage MOS transistor are mounted together, a step of forming a gate electrode, a patterning step of forming a photoresist in a formation region of the high breakdown voltage MOS transistor, and a formation region of the MOS transistor After the ion implantation step of forming a first LDD diffusion layer, the step of forming a sidewall oxide film on the sidewall of the gate electrode, and the step of forming the sidewall oxide film, the MOS is formed.
A patterning step of forming a photoresist in a transistor formation region, an ion implantation step of forming a second LDD diffusion layer in the high breakdown voltage MOS transistor formation region after the patterning step, and a drain region of the high breakdown voltage MOS transistor A method for manufacturing a semiconductor device, comprising: a patterning step of forming a photoresist for offsetting the source / drain diffusion layer formed on the substrate with respect to the gate electrode; and an ion implantation step of forming the source / drain diffusion layer. . 2. The projected range of ion implantation for forming the second LDD diffusion layer is set larger than the projected range of ion implantation for forming the source / drain diffusion layer. A method for manufacturing a semiconductor device as described above.