JP2604021B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device having two or more gate electrodes.

(Prior Art) Conventionally, a semiconductor device having two or more layers of gate electrodes, for example, a floating gate type EPROM is manufactured through the steps shown in FIGS. 2 (a) to 2 (d). That is, first, a field oxide film 2 for isolating an element region in an island shape is formed on a semiconductor substrate 1 such as silicon, and then a gate oxide film 3 is formed on the surface of the element region of the substrate 1. Next, a first polycrystalline silicon film 4 is deposited on the entire surface (second polycrystalline silicon film 4).
FIG.

Next, the polycrystalline silicon film 4 is patterned to form a first gate electrode (floating gate electrode) 4 'having a desired shape, and then a silicon oxide film (Si
O ₂ film). As a result, the first gate electrode 4 '
An oxide film 5 is formed on the surface (FIG. 2B).

Next, a second polycrystalline silicon film 6 is deposited on the entire surface (shown in FIG. 2 (c)), and then the second polycrystalline silicon film 6 is etched using a resist pattern (not shown) to form an oxide film. 5 on the first gate electrode 4 '.
Gate electrode 6 '(control gate electrode) is formed. At this time, the wiring of the second gate electrode 6 'is also patterned at the same time. Next, a resist pattern (not shown) having a source / drain region formation planned opening formed on the entire surface is formed, and impurity ions are implanted using the resist pattern as a mask. Next, heat treatment is performed to activate the implanted ions to form source / drain regions 7 and 8, and then an interlayer insulating film 9 is deposited on the entire surface (shown in FIG. 2 (d)). Here the third
The figure is a sectional view taken along the line AA in FIG. 2 (d).

Next, a contact hole is opened at the position of the source / drain regions 7 and 8 of the interlayer insulating film 9 and then aluminum is deposited on the entire surface by a well-known technique. Then, the aluminum is patterned, and the source / drain is patterned through the contact hole. Drain region
The semiconductor device is completed by forming wirings connected to 7, 8.

(Problems to be Solved by the Invention) In such a conventional technique, when the first gate electrode 4 ′ is formed as described above, the first polycrystalline silicon film 4 deposited on the entire surface of the substrate 1 is formed. Is selectively etched away, and the patterning is performed, so that the end face of the first gate electrode 4 'is vertical as shown by reference numeral a in FIG. 4, and therefore, the corner is sharp.

When the oxide film 5 is formed on the surface of the first gate electrode 4 ', as shown in FIG. 5, the growth of the oxide film at this sharp corner becomes slow due to the nature of the oxide film growth. The thickness of the portion is reduced. In addition, since the portion of the gate electrode 4 'has a sharp edge b due to the shape of the formed oxide film, electric field concentration occurs here, and the withstand voltage is further deteriorated.

In the case where the vertical surface portion of the first gate electrode 4 'is remarkable, the upper side of the first gate electrode 4' protrudes like an eaves as compared with the lower side as shown by a dashed line c in FIG. It becomes a so-called overhang state.

Then, after the oxide film 5 is grown on the first gate electrode 4 ', a polycrystalline silicon film for the second gate electrode is deposited on the entire surface, and when this is patterned, the portion to be removed is The polycrystalline silicon film 6 below the overhang portion in the first gate electrode 4 'cannot be completely removed,
After the removal step, a phenomenon that unnecessary polycrystalline silicon remains in this portion occurred. When such a state occurs, an unnecessary portion is added to the second gate electrode 6, and furthermore, this residual polycrystalline silicon film is peeled off in the subsequent manufacturing process, and various problems occur. And adversely affect the reliability of the semiconductor device.

In the case of an EPROM or the like, a high melting point metal or a high melting point metal silicide is deposited on the upper surface of the second gate electrode 6 'and its wiring to improve the operation speed of the element.
Although the resistance may be reduced, in the conventional structure, a nearly vertical step on the side wall surface of the first gate electrode 4 'leads to a large decrease in the reliability of the device.

That is, even after the oxide film 5 is formed in such a step portion, the wall surface is still substantially vertical, and the refractory metal material film is locally formed in such a steep step structure portion during the deposition step. In some cases, a portion where the film thickness fluctuates occurs, and the mechanical strength is reduced. Further, these high melting point materials are generally said to be thermally stable, but in reality, disconnection was likely to occur at the step portion during heat treatment in a subsequent step. So, in this case,
The reduction in electrical resistance cannot be measured, and the reliability also deteriorates.

The present invention has been made in view of the above circumstances, and improves the withstand voltage of an insulating film of a first gate electrode.
In the case where a high-melting-point metal material is deposited on the second gate electrode and its wiring to reduce the electrical resistance, it is possible to prevent the pattern of the high-melting-point metal material from being cut due to a step on the side of the first gate electrode. It is an object of the present invention to provide a method for manufacturing a semiconductor device.

[Constitution of the Invention] (Means and Action for Solving the Problems) According to the present invention, a field insulating film for isolating an element region in an island shape is formed on a surface of a one-conductivity type semiconductor substrate, Forming a first gate insulating film, forming a first polycrystalline silicon film over the entire surface, forming a second gate insulating film thereon, and forming a second polycrystalline silicon film thereon And a step of patterning the three layers of the first polycrystalline silicon film, the second gate insulating film, and the second polycrystalline silicon film to form a second gate insulating from the first gate electrode.
Forming a laminated gate electrode layer with a part of the gate electrode in a self-aligning manner, forming a third insulating film on the entire surface, and removing a part of the third insulating film to form a second insulating film. Exposing the surface of the electrode and leaving the third insulating film between the stacked gate electrodes, forming a third electrode layer on the entire surface and forming the third electrode layer and the second polycrystalline silicon film. Connecting and selectively patterning the third electrode layer.

According to the present invention, the first gate electrode, the second gate insulating film, and a part of the second gate electrode in the same cell (the first gate electrode, the second gate insulating film, Is formed in a self-aligned manner, and then the second gate electrodes including other cells are formed on the remaining third insulating film by the third gate electrode.
Is connected to the first gate electrode so as not to be covered with the second gate electrode so as to cover the first gate electrode as in the related art, to prevent electric field concentration at the corner of the first gate electrode, When a high withstand voltage can be obtained and a high melting point metal material is deposited on the second gate electrode to reduce the resistance, the step of the first gate electrode is filled with the third insulating film. Since the steps are gradual, the pattern of the high melting point metal material is prevented from being cut.

(Example) Hereinafter, an example of the present invention will be described with reference to manufacturing process diagrams shown in FIGS. 1 (a) to 1 (g), taking a nonvolatile memory (EPROM) as an example. FIG. 1 is a cross-sectional view of the right half and the left half as viewed from directions different from each other by 90 °.

First, a field oxide film 102 for separating an element region in an island shape was formed on a p-type silicon substrate 101, and then a first gate oxide film 103 was formed on an exposed surface of the substrate 101. Next, the substrate 101
After the first polycrystalline silicon film 104 is deposited on the entire surface of the first polycrystalline silicon film 104, the first polycrystalline silicon film 104
Was doped with, for example, phosphorus as an impurity. Next, a second gate insulating film 105 composed of three layers of a Si oxide film / Si nitride film / Si oxide film is formed. Next, a second polycrystalline silicon film 106 is formed by lamination. (FIG. 1 (a)) Next, a resist was applied to the entire surface, and a resist pattern 107 was formed by photolithography at a portion where a first gate electrode is to be formed in the element region (FIG. 1 (b)). . Subsequently, using the resist pattern 107 as a mask, the polycrystalline silicon film 106 is used.
, The second gate insulating film 105, and the polycrystalline silicon film 104 are selectively etched and removed sequentially to form a first gate electrode 104 '(floating gate electrode) and a second gate electrode (control gate electrode).
106 'was formed (FIG. 1 (c)).

Next, after removing the resist pattern 107, arsenic ions are implanted at an acceleration voltage of 40 keV and a dose of 5 × 10 ¹⁵ cm ⁻² .
Continue thermal oxidation, for example, 90 for activation and oxide film formation.
Performed at 0 ° C. in an atmosphere of dry O ₂ ,
A drain layer 109, a diffusion wiring layer, and an oxide film 110 are formed.
(FIG. 1 (d)) This oxide film 110 is formed by BPSG to be formed later.
It also serves to prevent the diffusion of impurities downward and laterally from the film or the like. Here, the formation of the diffusion layer and the formation of the oxide film are performed simultaneously, but they may be performed separately. Subsequently, a BPSG film 111 is deposited on the entire surface to planarize the cell area, and the flow is performed by a heat treatment at 900 ° C. Thereby, the inside of the cell area is flattened. (FIG. 1 (e)) Next, the BPSG film 111 is etched back using anisotropic etching (RIE) so that the second polysilicon layer 106 'of the cell is exposed. At this time, the second gate insulating film 105 and the first polysilicon layer 10
The etching time is controlled so that the 4 'surface is not exposed. (FIG. 1 (f)) on the entire surface to form a third wiring electrode layers subsequent third polycrystalline silicon 112 _1, for example WSi
To form a film 112 _2. Further, a third wiring electrode layer 112 is formed using a well-known photoresist method, and the second polysilicon layer 106 'in the cell is selectively connected to form a memory array. (FIG. 1 (g)) Thereafter, according to the conventional technique, an interlayer insulating film was formed, a contact hole was formed in a necessary portion, and an aluminum wiring layer was formed to complete a semiconductor device.

In the semiconductor device manufactured as described above, the polysilicon layer 104 ′ serving as the first gate electrode is formed in a self-aligned manner with the polysilicon layer 106 ′ formed immediately above, and is farther away from the insulating film 111. Since the polysilicon layer 104 'is not separated and the polysilicon layer 104' is not surrounded by the polysilicon 106 'as in the related art, corners that cause electric field concentration anywhere,
Since there is no protrusion, the withstand voltage characteristic and the memory holding characteristic are improved. Further, as long as third wiring electrode layer 112 is connected to second polycrystalline silicon layer 106 ', it can run at any width and position, and the degree of freedom in design increases. Further, since the insulating film 111 is flattened, the step between the cell portion and the cell-to-cell is reduced. When the third wiring layer 112 has a silicide or polycide structure, disconnection due to the step is completely eliminated. Can be prevented.

The present invention is not limited to the above embodiment, but can be applied to various applications. For example, in the present invention, the third electrode layer 112 may be a polycrystalline silicon film or a laminated film of a polycrystalline silicon film and a refractory metal silicide film.
Further, the second gate insulating film 105 may be a Si oxide film or a composite film of a Si oxide film and a Si nitride film. Further, the third insulating film 111 may be a Si oxide film, a film in which the Si oxide film contains an impurity selected from phosphorus, arsenic, and boron. The method of flattening the third insulating film 111 is not limited to the flow, but may be a method of applying a resist and then performing etch back using RIE or the like. Before or after connecting the third electrode layer 112 and the second polycrystalline silicon layer 106 ', the stacked gate electrode layer, impurity diffusion source / drain layers, and diffusion wiring layers may be formed.

[Effects of the Invention] As described above in detail, according to the present invention, it is possible to prevent electric field concentration at the corner of the first gate electrode and obtain a sufficient withstand voltage. In the case where silicide or polycide is used for the third electrode layer serving as a control gate, since there is almost no step on the side surface of the cell, it is possible to provide a highly reliable method of manufacturing a semiconductor device such as no disconnection of a pattern. .

[Brief description of the drawings]

1 (a) to 1 (g) are manufacturing process diagrams for explaining a first embodiment of the present invention, FIGS. 2 (a) to 2 (d) are manufacturing process diagrams for explaining a conventional method, and FIG. The figure is A- of FIG.
FIG. 4 is a sectional view of A, FIG. 4 is a view for explaining the state of erosion near the first gate electrode on the surface of the field oxide film generated during the etching of the first polycrystalline silicon film in the related art, and FIG. FIG. 3 is a diagram showing a state of an oxide film formed on one gate electrode. 101 ... p-type silicon substrate, 102 ... field oxide film,
103 ... first gate oxide film, 104 ... first polycrystalline silicon film, 104 '... first gate electrode, 105 ... second gate insulating film, 106' ... second polycrystalline silicon Film (second gate electrode), 107 resist pattern, 108, 109 source / drain layer, 110 oxide film, 111 BPSG film, 11
2 ₁ ... Third polycrystalline silicon film, 112 ₂ ... Silicide film, 112... Third electrode layer.

Claims (5)

(57) [Claims] A step of forming a field insulating film for isolating an element region in an island shape on a surface of a semiconductor substrate of one conductivity type; forming a first gate insulating film on a surface of the element region; Forming a polycrystalline silicon film, forming a second gate insulating film thereon, and forming a second polycrystalline silicon film thereon; and forming the first polycrystalline silicon film and a second polycrystalline silicon film on the second polycrystalline silicon film. The three layers of the gate insulating film and the second polycrystalline silicon film are patterned to form a self-aligned laminated gate electrode layer of the first gate electrode and a part of the second gate electrode insulated therefrom. Forming a third insulating film on the entire surface; removing a part of the third insulating film to expose a second electrode surface; and forming the third insulating film between the stacked gate electrodes. And forming a third electrode layer on the entire surface and forming the third electrode layer The method of manufacturing a semiconductor device according to claim a linking two polycrystalline silicon film and the third electrode layer selectively be equipped and a step of patterning. 2. The method according to claim 1, wherein the third electrode layer is made of a polycrystalline silicon film or a laminated film of a polycrystalline silicon film and a refractory metal silicide film. . 3. The method according to claim 1, wherein the second gate insulating film is a Si oxide film or a composite film of a Si oxide film and a Si nitride film. 4. The method according to claim 1, wherein the third insulating film is a Si oxide film or
2. The method according to claim 1, wherein the Si oxide film includes a film containing an impurity selected from phosphorus, arsenic, and boron. 5. An impurity diffusion source / drain layer and a diffusion wiring layer are formed in a self-aligned manner with the stacked gate electrode layer before connecting the third electrode layer and the second polycrystalline silicon film. 2. The method for manufacturing a semiconductor device according to claim 1, wherein: