JPH0693442B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0693442B2 JPH0693442B2 JP62215603A JP21560387A JPH0693442B2 JP H0693442 B2 JPH0693442 B2 JP H0693442B2 JP 62215603 A JP62215603 A JP 62215603A JP 21560387 A JP21560387 A JP 21560387A JP H0693442 B2 JPH0693442 B2 JP H0693442B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- contact hole
- insulating film
- semiconductor substrate
- diffusion layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Weting (AREA)
- Formation Of Insulating Films (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特にコンタクト
部の形成方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a contact portion.
第３図は従来技術によって形成されたコンタクト部の断
面図を示すもので、Ｎ型拡散層２上の積層層間絶縁膜を
選択的に開口し、スパッタ法を用いてアルミ配線５を被
着させたものである。ここで、１はＰ型シリコン基板、
３および４は下層および上層の層間絶縁膜をそれぞれ示
す。FIG. 3 is a sectional view of a contact portion formed by a conventional technique, in which a laminated interlayer insulating film on the N-type diffusion layer 2 is selectively opened and an aluminum wiring 5 is deposited by using a sputtering method. It is a thing. Here, 1 is a P-type silicon substrate,
Reference numerals 3 and 4 denote lower and upper interlayer insulating films, respectively.
一般に層間絶縁膜に対するコンタクト孔の開口は、フォ
トレジスト膜をマスクとする選択的写真食刻法または異
方性ドライエッチング法で行なわれるが、開口がすすみ
コンタクト孔底部の基板面がむき出しとなると、その後
の工程でこのむき出しとなった基板面には自然酸化膜が
被着するようになる。従って、アルミ配線５をスパッタ
形成する前には必ずこの自然酸化膜を除去するエッチン
グ作業を行わねばならない。しかし、この自然酸化膜は
コンタクト孔の底部に存在するので、この除去作業の進
行と共に層間絶縁膜の側壁面も同時にエッチングされ
る。従って、下層絶縁膜３にエッチング・レートの高い
材質が、また、上層の層間絶縁膜14にエッチング・レー
トの低い材質が使用された場合には、開口されるコンタ
クト孔の側壁は第３図に示す如くオーバー・ハングとな
り、アルミ配線５の被覆性が著しく害される。Generally, the opening of the contact hole with respect to the interlayer insulating film is performed by the selective photo-etching method using the photoresist film as a mask or the anisotropic dry etching method, but when the opening is narrowed and the substrate surface at the bottom of the contact hole is exposed, In a subsequent step, a natural oxide film will be deposited on the exposed substrate surface. Therefore, an etching operation for removing the natural oxide film must be performed before the aluminum wiring 5 is formed by sputtering. However, since this natural oxide film exists at the bottom of the contact hole, the side wall surface of the interlayer insulating film is simultaneously etched as the removal work progresses. Therefore, when a material having a high etching rate is used for the lower insulating film 3 and a material having a low etching rate is used for the upper interlayer insulating film 14, the sidewall of the contact hole to be opened is shown in FIG. As shown, overhang occurs, and the covering property of the aluminum wiring 5 is significantly impaired.
本発明の目的は、上記の情況に鑑み、開口部側壁にオー
バー・ハングを生じることなきコンタクト部形成手段を
備えた半導体装置の製造方法を提供することである。In view of the above situation, an object of the present invention is to provide a method of manufacturing a semiconductor device including a contact portion forming means that does not cause overhang on the side wall of the opening.
本発明の特徴は、半導体基板の拡散層上もしくは半導体
基板上の配線膜上に被着形成された第１の絶縁膜と前記
第１の絶縁膜上に被着形成された第２の絶縁膜とを有す
る多層層間絶縁膜を選択的にエッチング除去して前記拡
散層もしくは前記配線膜の表面の所定部を露出させるコ
ンタクト孔を形成する工程と、多結晶シリコン、アルミ
ナ、シリコン窒化膜、高融点金属および高融点金属のシ
リサイドから選ばれた材質の保護膜を前記多層層間絶縁
膜上から前記コンタクト孔内に形成し、異方性エッチン
グを行って前記コンタクト孔の側壁のみに前記保護膜を
残余せしめこれにより前記コンタクト孔内に露出する前
記第１および第２の絶縁膜の側壁を前記保護膜で被覆す
る工程と、しかる後、前記コンタクト孔底部の前記半導
体基板の拡散層もしくは半導体基板上の配線膜の表面の
所定部上に発生した自然酸化膜をフッ化水素系のエッチ
ング液により除去する工程と有するを半導体装置の製造
方法にある。A feature of the present invention is that a first insulating film deposited on a diffusion layer of a semiconductor substrate or a wiring film on the semiconductor substrate and a second insulating film deposited on the first insulating film. Selectively removing the multilayer interlayer insulating film having a contact hole to expose a predetermined portion of the surface of the diffusion layer or the wiring film, and polycrystalline silicon, alumina, silicon nitride film, high melting point A protective film made of a material selected from metal and refractory metal silicide is formed in the contact hole from above the multilayer interlayer insulating film, and anisotropic etching is performed to leave the protective film only on the sidewall of the contact hole. The step of covering the sidewalls of the first and second insulating films exposed in the contact hole with the protective film, and then also the diffusion layer of the semiconductor substrate at the bottom of the contact hole Ku is a has a step of removing by the hydrofluoric etchant natural oxide film generated in a predetermined portion on the surface of the wiring layer on the semiconductor substrate to a method of manufacturing a semiconductor device.
以下図面を参照して本発明を詳細に説明する。 Hereinafter, the present invention will be described in detail with reference to the drawings.
第１図（ａ）〜（ｃ）は本発明の一実施例を示す工程図
である。本実施例によれば、一主面にＮ型拡散層２を選
択的に形成し、更にその上面に下層および上層の層間絶
縁膜３および４をそれぞれ4000Åおよび7000Åの膜厚に
積層した不純物濃度１×1015cm−３のＰ型シリコン基板
１がまず準備される。このＮ型拡散層２の形成には例え
ば砒素（As）のイオン注入法〔加速電圧（Ｅ）70KeV,ド
ーズ量（φ）５×1015cm−２〕が使用される。ここで、
下層および上層の層間絶縁膜３および４を通常の写真食
刻法によるパターニングとプラズマエッチング法とによ
って開口し、Ｎ型拡散層２上にコンタクト孔６を形成し
た後、この孔内を含む基板全面に多結晶シリコン膜８を
膜厚1000Å程度成長せしめる。〔（第１図（ａ）参
照〕。ここで、７は既に説明した理由によって形成され
た自然酸化膜である。ついで異方性プラズマエッチング
法を用いて多結晶シリコン膜８をエッチバックしコンタ
クト孔６の側壁面のみに多結晶シリコン膜８を残す。
〔第１図（ｂ）参照〕。つぎにアルミ配線材をスパッタ
する前に自然酸化膜７に対する除去工程を行う。この際
コンタクト孔側壁の多結晶シリコン膜８はエッチングさ
れないので、下層の層間絶縁膜３にエッチング・レート
の高い材質が用いられた場合でも従来の如きオーバー・
ハングは形成されない〔第１図（ｃ）参照〕。FIGS. 1A to 1C are process drawings showing an embodiment of the present invention. According to the present embodiment, the N-type diffusion layer 2 is selectively formed on one main surface, and the lower and upper interlayer insulating films 3 and 4 are further stacked on the upper surface thereof to have a film thickness of 4000 Å and 7000 Å, respectively. First, a 1 × 10 15 cm −3 P-type silicon substrate 1 is prepared. To form the N-type diffusion layer 2, for example, an arsenic (As) ion implantation method [acceleration voltage (E) 70 KeV, dose amount (φ) 5 × 10 15 cm −2 ] is used. here,
After opening the lower and upper interlayer insulating films 3 and 4 by patterning by a normal photo-etching method and a plasma etching method to form a contact hole 6 on the N-type diffusion layer 2, the whole surface of the substrate including the inside Then, the polycrystalline silicon film 8 is grown to a film thickness of about 1000Å. [Refer to FIG. 1 (a)] Here, 7 is a natural oxide film formed for the reasons already explained, and then the polycrystalline silicon film 8 is etched back by an anisotropic plasma etching method to make contact. The polycrystalline silicon film 8 is left only on the side wall surface of the hole 6.
[See FIG. 1 (b)]. Next, a step of removing the natural oxide film 7 is performed before the aluminum wiring material is sputtered. At this time, since the polycrystalline silicon film 8 on the side wall of the contact hole is not etched, even if a material having a high etching rate is used for the lower interlayer insulating film 3, it is possible to prevent over-etching as in the conventional case.
No hang is formed [see FIG. 1 (c)].
以上はコンタクト孔側壁面を被覆する材料として多結晶
シリコンを用いた場合を説明したが、自然酸化膜７の除
去工程で使用するフッ化水素系のエッチング液によって
エッチングされない材料であれば何れの半導体材料でも
用いることができる。これらの材料のなかには、アルミ
ナ，窒化シリコン膜，高融点金属および高融点金属シリ
サイド等が含まれる。The case where polycrystalline silicon is used as the material for covering the side wall surface of the contact hole has been described above. A material can also be used. Among these materials, alumina, silicon nitride film, refractory metal, refractory metal silicide and the like are included.
第２図は本発明の他の実施例によって製造されたコンタ
クト部の断面図を示す。本実施例によれば、コンタクト
孔６はフィールド絶縁膜９上に形成されたＮ形多結晶シ
リコン層10上に開口される。この多結晶シリコン層10は
一般に配線として用いられるものであるが、このように
コンタクト孔を多結晶シリコン配線上に設ける場合にお
いても前実施例と同様の効果を得ることができる。FIG. 2 is a sectional view of a contact portion manufactured according to another embodiment of the present invention. According to this embodiment, the contact hole 6 is opened on the N-type polycrystalline silicon layer 10 formed on the field insulating film 9. This polycrystalline silicon layer 10 is generally used as a wiring. However, even when the contact hole is provided on the polycrystalline silicon wiring in this way, the same effect as in the previous embodiment can be obtained.
以上詳細に説明したように、本発明によれば、コンタク
ト孔側壁にフッ化水素系のエッチング液ではエッチング
されない膜を被着してからコンタクト孔底部の自然酸化
膜を除去するので、自然酸化膜除去工程におけるコンタ
クト孔側壁の層間膜の同時エッチングは防止される。従
って、コンタクト孔の側壁にオーバーハングを発生せし
めることがないので、金属配線の被覆性がきわめて良好
なコンタクト部を容易に形成することができる。As described in detail above, according to the present invention, the native oxide film at the bottom of the contact hole is removed after depositing the film that is not etched by the hydrogen fluoride-based etching solution on the sidewall of the contact hole. Simultaneous etching of the interlayer film on the sidewall of the contact hole in the removing step is prevented. Therefore, an overhang is not generated on the side wall of the contact hole, so that the contact portion with excellent coverage of the metal wiring can be easily formed.
第１図（ａ）〜（ｃ）は本発明の一実施例を示す工程
図、第２図は本発明の他の実施例によって製造されたコ
ンタクト部の断面図、第３図は従来技術によって形成さ
れたコンタクト部の断面図である。 １……Ｐ型シリコ基板、２……Ｎ型拡散層、３および４
……下層および上層の層間絶縁膜、５……アルミ配線、
６……コンタクト孔、７……自然酸化膜、８……多結晶
シリコン膜、９……フィールド絶縁膜、10……Ｎ型多結
晶シリコン膜。1 (a) to 1 (c) are process diagrams showing an embodiment of the present invention, FIG. 2 is a sectional view of a contact portion manufactured by another embodiment of the present invention, and FIG. 3 is a conventional technique. It is sectional drawing of the formed contact part. 1 ... P-type silicon substrate, 2 ... N-type diffusion layer, 3 and 4
...... Lower and upper interlayer insulating films, 5 ...... Aluminum wiring,
6 ... Contact hole, 7 ... Natural oxide film, 8 ... Polycrystalline silicon film, 9 ... Field insulating film, 10 ... N-type polycrystalline silicon film.
Claims (1)
上の配線膜上に被着形成された第１の絶縁膜と前記第１
の絶縁膜上に被着形成された第２の絶縁膜とを有する多
層層間絶縁膜を選択的にエッチング除去して前記拡散層
もしくは前記配線膜の表面の所定部を露出させるコンタ
クト孔を形成する工程と、 多結晶シリコン、アルミナ、シリコン窒化膜、高融点金
属および高融点金属のシリサイドから選ばれた材質の保
護膜を前記多層層間絶縁膜上から前記コンタクト孔内に
形成し、異方性エッチングを行って前記コンタクト孔の
側壁のみに前記保護膜を残余せしめこれにより前記コン
タクト孔内に露出する前記第１および第２の絶縁膜の側
壁を前記保護膜で被覆する工程と、 しかる後、前記コンタクト孔底部の前記半導体基板の拡
散層もしくは半導体基板上の配線膜の表面の所定部上に
発生した自然酸化膜をフッ化水素系のエッチング液によ
り除去する工程と を有することを特徴とする半導体装置の製造方法。1. A first insulating film deposited on a diffusion layer of a semiconductor substrate or a wiring film on the semiconductor substrate and the first insulating film.
A multilayer insulating film having a second insulating film deposited on the insulating film is selectively removed by etching to form a contact hole exposing a predetermined portion of the surface of the diffusion layer or the wiring film. And a step of forming a protective film of a material selected from polycrystalline silicon, alumina, a silicon nitride film, a refractory metal, and a silicide of a refractory metal in the contact hole from above the multilayer interlayer insulating film and performing anisotropic etching. And leaving the protective film only on the side wall of the contact hole, thereby covering the side wall of the first and second insulating films exposed in the contact hole with the protective film. A natural oxide film formed on the diffusion layer of the semiconductor substrate at the bottom of the contact hole or on a predetermined portion of the surface of the wiring film on the semiconductor substrate is removed by a hydrogen fluoride-based etching solution. The method of manufacturing a semiconductor device characterized by a step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62215603A JPH0693442B2 (en) | 1987-08-28 | 1987-08-28 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62215603A JPH0693442B2 (en) | 1987-08-28 | 1987-08-28 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6457717A JPS6457717A (en) | 1989-03-06 |
| JPH0693442B2 true JPH0693442B2 (en) | 1994-11-16 |
Family
ID=16675164
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62215603A Expired - Lifetime JPH0693442B2 (en) | 1987-08-28 | 1987-08-28 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0693442B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7618549B2 (en) | 2005-10-26 | 2009-11-17 | Kabushiki Kaisha Toshiba | Method of forming patterns and method of manufacturing magnetic recording media |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03173126A (en) * | 1989-11-30 | 1991-07-26 | Mitsubishi Electric Corp | Semiconductor device of multilayer film structure and its manufacture |
| US5105857A (en) * | 1990-10-31 | 1992-04-21 | Microtek Industries, Inc. | System for forming leads for surface mounted components |
| US5487416A (en) * | 1991-12-11 | 1996-01-30 | Precision Technologies, Inc. | Lead conditioning system for semiconductor devices |
| JPH0677373A (en) * | 1992-08-25 | 1994-03-18 | Y K C:Kk | Forming die for outer lead bending device of semiconductor package |
| JP2771431B2 (en) * | 1993-09-07 | 1998-07-02 | 日本電気株式会社 | Lead forming equipment |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50103282A (en) * | 1974-01-11 | 1975-08-15 | ||
| JPS60175415A (en) * | 1984-02-21 | 1985-09-09 | Toshiba Mach Co Ltd | Vertical type vapor growth device |
| JPS61161720A (en) * | 1985-01-10 | 1986-07-22 | Nec Corp | Manufacture of semiconductor device |
| JPS62290127A (en) * | 1986-06-09 | 1987-12-17 | Toshiba Corp | Manufacture of semiconductor device |
-
1987
- 1987-08-28 JP JP62215603A patent/JPH0693442B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7618549B2 (en) | 2005-10-26 | 2009-11-17 | Kabushiki Kaisha Toshiba | Method of forming patterns and method of manufacturing magnetic recording media |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6457717A (en) | 1989-03-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term | ||
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