JPS6457717A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6457717A
JPS6457717A JP21560387A JP21560387A JPS6457717A JP S6457717 A JPS6457717 A JP S6457717A JP 21560387 A JP21560387 A JP 21560387A JP 21560387 A JP21560387 A JP 21560387A JP S6457717 A JPS6457717 A JP S6457717A
Authority
JP
Japan
Prior art keywords
layer
film
inter
type diffusion
polycrystalline silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21560387A
Other languages
Japanese (ja)
Other versions
JPH0693442B2 (en
Inventor
Hiroaki Akiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62215603A priority Critical patent/JPH0693442B2/en
Publication of JPS6457717A publication Critical patent/JPS6457717A/en
Publication of JPH0693442B2 publication Critical patent/JPH0693442B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To form a contact section, in which the coatability of a metallic wiring is improved, by selectively boring an inter-multilayer insulating film on a substrate, shaping an etching protective film, in which the sidewall of an opening section is coated with a semiconductor material nonreactive to a melting solution for an silicon oxide film, and removing a natural oxide film in the bottom of the opening section. CONSTITUTION:An N-type diffusion layer 2 is formed to a P-type silicon sub strate, and inter-layer insulating films 3 and 4 as a lower layer and an upper layer are laminated onto the top face of the layer 2. An ion implantation method such as arsenic (As) one is used for shaping the N-type diffusion layer 2. A contact hole 6 is bored onto the N-type diffusion layer 2 through patterning by a photoetching method and plasma etching in the inter-layer insulating films 3 and 4, and a polycrystalline silicon film 8 is grown on the whole surface of the substrate including the inside of the hole. The polycrystalline silicon film 8 is etched back by employing an anisotropic plasma etching method, and the polycrystalline silicon film 8 is left only on the sidewall surface of the contact hole 6. A removal process to a natural oxide film 7 is executed before an aluminum wiring 5 is sputtered.
JP62215603A 1987-08-28 1987-08-28 Method for manufacturing semiconductor device Expired - Lifetime JPH0693442B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62215603A JPH0693442B2 (en) 1987-08-28 1987-08-28 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62215603A JPH0693442B2 (en) 1987-08-28 1987-08-28 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS6457717A true JPS6457717A (en) 1989-03-06
JPH0693442B2 JPH0693442B2 (en) 1994-11-16

Family

ID=16675164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62215603A Expired - Lifetime JPH0693442B2 (en) 1987-08-28 1987-08-28 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0693442B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5105857A (en) * 1990-10-31 1992-04-21 Microtek Industries, Inc. System for forming leads for surface mounted components
US5319246A (en) * 1989-11-30 1994-06-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having multi-layer film structure
US5358017A (en) * 1992-08-25 1994-10-25 Y.K.C. Co., Ltd. Method, system and apparatus for forming leads for semiconductors packages
US5487416A (en) * 1991-12-11 1996-01-30 Precision Technologies, Inc. Lead conditioning system for semiconductor devices
US5535789A (en) * 1993-09-07 1996-07-16 Nec Corporation Lead wire forming apparatus capable of preventing the peeling of the solder from the lead wire

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4630795B2 (en) 2005-10-26 2011-02-09 株式会社東芝 Pattern forming method and method for manufacturing magnetic recording medium

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50103282A (en) * 1974-01-11 1975-08-15
JPS60175415A (en) * 1984-02-21 1985-09-09 Toshiba Mach Co Ltd Vertical type vapor growth device
JPS61161720A (en) * 1985-01-10 1986-07-22 Nec Corp Manufacture of semiconductor device
JPS62290127A (en) * 1986-06-09 1987-12-17 Toshiba Corp Manufacture of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50103282A (en) * 1974-01-11 1975-08-15
JPS60175415A (en) * 1984-02-21 1985-09-09 Toshiba Mach Co Ltd Vertical type vapor growth device
JPS61161720A (en) * 1985-01-10 1986-07-22 Nec Corp Manufacture of semiconductor device
JPS62290127A (en) * 1986-06-09 1987-12-17 Toshiba Corp Manufacture of semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5319246A (en) * 1989-11-30 1994-06-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having multi-layer film structure
US5105857A (en) * 1990-10-31 1992-04-21 Microtek Industries, Inc. System for forming leads for surface mounted components
US5487416A (en) * 1991-12-11 1996-01-30 Precision Technologies, Inc. Lead conditioning system for semiconductor devices
US5358017A (en) * 1992-08-25 1994-10-25 Y.K.C. Co., Ltd. Method, system and apparatus for forming leads for semiconductors packages
US5535789A (en) * 1993-09-07 1996-07-16 Nec Corporation Lead wire forming apparatus capable of preventing the peeling of the solder from the lead wire

Also Published As

Publication number Publication date
JPH0693442B2 (en) 1994-11-16

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