JPS6431453A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6431453A
JPS6431453A JP62188241A JP18824187A JPS6431453A JP S6431453 A JPS6431453 A JP S6431453A JP 62188241 A JP62188241 A JP 62188241A JP 18824187 A JP18824187 A JP 18824187A JP S6431453 A JPS6431453 A JP S6431453A
Authority
JP
Japan
Prior art keywords
film
whole surface
deposited
sidewall
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62188241A
Other languages
Japanese (ja)
Other versions
JPH06105772B2 (en
Inventor
Satoru Maeda
Shizuo Sawada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62188241A priority Critical patent/JPH06105772B2/en
Priority to KR1019880009514A priority patent/KR920000077B1/en
Priority to DE8888306979T priority patent/DE3877282T2/en
Priority to EP88306979A priority patent/EP0305055B1/en
Publication of JPS6431453A publication Critical patent/JPS6431453A/en
Priority to US07/549,632 priority patent/US5110766A/en
Publication of JPH06105772B2 publication Critical patent/JPH06105772B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To minimize a distance between an opening and a gate electrode, while reducing the size of an element and to prevent the wirings of an uppermost layer from stepwisely disconnecting by forming the gate electrode, depositing a fourth insulating film on a whole surface while leaving a third insulating film on a sidewall, and selectively removing it to form an opening communicating with the surface of a substrate. CONSTITUTION:After a silicon oxide film 30 remains only on the sidewall of word lines 24, a silicon oxide film 31 is formed on the whole surface, selectively etched with a mask of a predetermined shape to open a contact hole 32 between two word lines 24. Then, after a polycrystalline silicon film 33 is deposited on the whole surface, it is selectively removed with a predetermined mask, and the film 33 remains in a shape for burying in the hole 32. Then, after a low melting point glass film 34 is deposited on the whole surface, it is heat treated 60 flatten the surface of the film 34, and etched to expose part of the film 33. Thereafter, a polycrystalline silicon film and a high melting point metal film of Mo, W are sequentially deposited, and patterned to form a bit line 35 connected to the film 33.
JP62188241A 1987-07-28 1987-07-28 Method for manufacturing semiconductor device Expired - Fee Related JPH06105772B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP62188241A JPH06105772B2 (en) 1987-07-28 1987-07-28 Method for manufacturing semiconductor device
KR1019880009514A KR920000077B1 (en) 1987-07-28 1988-07-27 Method of manufacturing a semiconductor device
DE8888306979T DE3877282T2 (en) 1987-07-28 1988-07-28 METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE.
EP88306979A EP0305055B1 (en) 1987-07-28 1988-07-28 Method of manufacturing a semiconductor device
US07/549,632 US5110766A (en) 1987-07-28 1990-07-06 Method of manufacturing a semiconductor device including forming a flattening layer over hollows in a contact hole

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62188241A JPH06105772B2 (en) 1987-07-28 1987-07-28 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS6431453A true JPS6431453A (en) 1989-02-01
JPH06105772B2 JPH06105772B2 (en) 1994-12-21

Family

ID=16220259

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62188241A Expired - Fee Related JPH06105772B2 (en) 1987-07-28 1987-07-28 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH06105772B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0645329A (en) * 1992-03-04 1994-02-18 Samsung Electron Co Ltd High-integration semiconductor device and manufacture
KR100277932B1 (en) * 1993-03-12 2001-02-01 김영환 Contact hole flattening method of DRAM cell

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6159866A (en) * 1984-08-31 1986-03-27 Hitachi Ltd Mos type dynamic memory and manufacture thereof
JPS61144863A (en) * 1984-12-19 1986-07-02 Hitachi Ltd Semiconductor memory and manufacture thereof
JPS61183952A (en) * 1985-02-09 1986-08-16 Fujitsu Ltd Semiconductor memory device and manufacture thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6159866A (en) * 1984-08-31 1986-03-27 Hitachi Ltd Mos type dynamic memory and manufacture thereof
JPS61144863A (en) * 1984-12-19 1986-07-02 Hitachi Ltd Semiconductor memory and manufacture thereof
JPS61183952A (en) * 1985-02-09 1986-08-16 Fujitsu Ltd Semiconductor memory device and manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0645329A (en) * 1992-03-04 1994-02-18 Samsung Electron Co Ltd High-integration semiconductor device and manufacture
KR100277932B1 (en) * 1993-03-12 2001-02-01 김영환 Contact hole flattening method of DRAM cell

Also Published As

Publication number Publication date
JPH06105772B2 (en) 1994-12-21

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees