GB1521431A - Forming conductors for electrical devices - Google Patents

Forming conductors for electrical devices

Info

Publication number
GB1521431A
GB1521431A GB205677A GB205677A GB1521431A GB 1521431 A GB1521431 A GB 1521431A GB 205677 A GB205677 A GB 205677A GB 205677 A GB205677 A GB 205677A GB 1521431 A GB1521431 A GB 1521431A
Authority
GB
United Kingdom
Prior art keywords
layer
photoresist
deposited
metal
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB205677A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1521431A publication Critical patent/GB1521431A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off

Abstract

1521431 Semiconductor device metallization INTERNATIONAL BUSINESS MACHINES CORP 19 Jan 1977 [6 Feb 1976] 02056/77 Heading H1K The invention concerns the manufacture of multi-level metallization patterns, e.g. for LSI devices. In its preferred form there are successively deposited on a metal layer 40 on a substrate 36 an insulating layer (e.g. SiO 2 ) 42, a photoresist layer 44 and a metal marking layer 46. Preferably using a further photoresist mark, an opening 56 is successively etched down through the layers 46, 44 and 42, and a metal layer 58/60 of the same thickness as the layer 42 is deposited over the layer 46 and in the opening 56. The photoresist 44 is then dissolved, lifting off the overlying layers 46, 58. A further metal layer may then be deposited to contact the layer position 60, and appropriately patterned.
GB205677A 1976-02-06 1977-01-19 Forming conductors for electrical devices Expired GB1521431A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US65581476A 1976-02-06 1976-02-06

Publications (1)

Publication Number Publication Date
GB1521431A true GB1521431A (en) 1978-08-16

Family

ID=24630480

Family Applications (1)

Application Number Title Priority Date Filing Date
GB205677A Expired GB1521431A (en) 1976-02-06 1977-01-19 Forming conductors for electrical devices

Country Status (6)

Country Link
JP (1) JPS5827664B2 (en)
CA (1) CA1088382A (en)
DE (1) DE2703473A1 (en)
FR (1) FR2340620A1 (en)
GB (1) GB1521431A (en)
IT (1) IT1079545B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4184909A (en) * 1978-08-21 1980-01-22 International Business Machines Corporation Method of forming thin film interconnection systems
JPS59170692A (en) * 1983-03-16 1984-09-26 Ebara Corp Water-sealed heat exchanger
EP3368864B1 (en) 2015-10-27 2020-03-04 Schaeffler Technologies GmbH & Co. KG Bearing assembly with incorporated electric line for providing multiple operating voltages

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1267738B (en) * 1962-10-29 1968-05-09 Intellux Inc Process for making electrical connections between the circuits of multilayer printed electrical circuits
US3464855A (en) * 1966-09-06 1969-09-02 North American Rockwell Process for forming interconnections in a multilayer circuit board
DE1765013A1 (en) * 1968-03-21 1971-07-01 Telefunken Patent Process for the production of multilevel circuits
DE2059425A1 (en) * 1970-12-02 1972-06-22 Siemens Ag Partial structure of printed multilayer circuits
JPS4960870A (en) * 1972-10-16 1974-06-13
US3873361A (en) * 1973-11-29 1975-03-25 Ibm Method of depositing thin film utilizing a lift-off mask
JPS5120681A (en) * 1974-07-27 1976-02-19 Oki Electric Ind Co Ltd Handotaisochino seizohoho
NL7415841A (en) * 1974-12-05 1976-06-09 Philips Nv PROCESS FOR THE MANUFACTURE OF A SEMI-CONDUCTOR DEVICE AND SEMI-CONDUCTOR DEVICE, MANUFACTURED ACCORDING TO THE PROCESS.
JPS5272571A (en) * 1975-12-15 1977-06-17 Fujitsu Ltd Production of semiconductor device

Also Published As

Publication number Publication date
FR2340620B1 (en) 1979-09-28
DE2703473C2 (en) 1991-01-24
JPS5295987A (en) 1977-08-12
FR2340620A1 (en) 1977-09-02
JPS5827664B2 (en) 1983-06-10
CA1088382A (en) 1980-10-28
IT1079545B (en) 1985-05-13
DE2703473A1 (en) 1977-08-11

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee