CA1088382A

CA1088382A - Method of making a large scale integrated device having a planar surface

Info

Publication number: CA1088382A
Application number: CA271,002A
Authority: CA
Inventors: Ekkehard F. Miersch; Hwa N. Yu
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 1976-02-06
Filing date: 1977-02-03
Publication date: 1980-10-28
Also published as: JPS5295987A; DE2703473A1; IT1079545B; FR2340620B1; FR2340620A1; DE2703473C2; GB1521431A; JPS5827664B2

Abstract

Abstract of the Disclosure A method of surface planarizing large scale integrated devices, including a double metal lift-off step is described. A first resist layer is deposited on an insulating layer which is formed over a first metal layer with a pattern structure. The resist layer is then masked by another metal layer. Then, a second resist layer is deposited over the metal masking, and is exposed and developed to delineate via holes therein. The metal masking, first resist layer and insulating layer are successively etched to define the via holes. During this procedure the second esist layer is automatically removed. A second metal layer is then deposited on the metal masking layer and in the defined via holes. The first resist layer is then lifted off which in turn accomplishes the double metal lift-off of the metal masking and the second metal layer.
Subsequently, a third conductive metal pattern layer may, if desired, be deposited over the insulating layer and the metal filled via holes therein. A third resist layer is then deposited on the third metal layer and is exposed and develop-ed to delineate a conductive pattern on the resist layer. The third resist layer is then exposed and developed and then the conductive pattern is formed on the planar surface of the device by lift-off reactive ion etching or other convention-al techniques.

Description

1~83~32 Background of Th_ Invention

2 Known large scale integrated (LSI) devices have

3 an irregular service topography which makes it difficult

4 to stack and interconnect such devices. Also, the number of conductors which may be formed in a given area on the 6 device are limited by the irregular topography.
7 According to the present invention, a method is 8 disclosed for fabricating an LSI device having a planar 9 surface. Accordingly, a greater number of conductors can be formed in a given area on the device, and the devices 11 are easily stacked and interconnected.

12 Summary of The Invention 13 According to the present invention a method of 14 making a large scaled integrated circuit device having a planar surface adjacent via holes is disclosed. A substrate 16 has a first conductive layer deposited thereon, with an in-17 sulating layer being deposited over the conductive layer.
18 The insulating layer is metal masked and via holes are defined 19 in the metal masking. Etching defines the via holes in the insulating layer. A second conductive layer is deposited on 21 the metal masking and in the defined via holes. Lastly, the 22 metal masking and the portion of the second conductive layer 23 formed thereon are concurrently lifted off the device yield-24 ing a planar surface.

Brief Description of the Drawings 26 FIG. 1 is a side view, taken along the lines 1-1 27 of FIG. 2, of a large scale integrated circuit device known ~ -.

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1 in the prior art;
2 FIG. 2 is a top view of the large scale integrated 3 device illustrated in lIG. l;
4 FIG. 3 is a side view, taken along the lines 3-3

- 5 of FIG. 4, of a large scale integrated circuit device accord-

6 ing to the present invention;

7 FIGS. SA-SN represent sequential side views of a

8 substrate processed in accordance with the present invention

9 for forming a large scale integrated device having a more planar surface; and 11 FIG. 6 is a schematic diagram illustrating how 12 monolithic large scale integrated devices of the present in-13 vention may be interconnected with other monolithic devices.

14 Detailed Desc_iption of The Invention ~5 ReEer now to FIGS. 1 and 2 which illustrate a known 16 large scale integrated (LSI) device having an irregular 17 surface topography adjacent the via holes. An LSI device 2 18 is comprised of a substrate 4 having an insulating layer 6 19 such as silicon oxide (SiO2) formed thereon with a metal layer 8 being formed on the insulating layer 6. A second insulating 21 layer 10 of SiO2 is formed over the layer 8 and a via hole 9 22 is defined therein by chemically etching. The side dimension 23 of the hole 9 on the upper surface of the insulating layer is 24 Wl which tapers to a side dimension W2 on the lower surface of the insulating layer. The tapered hol~e results from the 26 chemical etching step. A metal layer 12 is deposited on the 27 insulating layer 10 and in the via hole 9 formed therein, _ . .. . _ ... .... . . _ .

!38382 1 with the layer 12 following the contour of the layer 10 2 The regions 14 and 16 oE the sloping walls of the via hole 3 exhibit contact problems due to the reduced conductor thick-4 ness in these regions. That is, due to the reduced conductor thickness there may be a greater than desired resistivity 6 in these regions or the conductors may even become broken.
7 Conductor patterns 18 are formed on the top surface of the 8 device 2 by etching away unwanted areas of the metal from the 9 layer 12. The conductors 18 have a dimension 1~2 correspond-ing to the lower side dimension W2 of the via hole formed ir 11 the bottom surface of the insulating layer 10. This is so, 12 due to the contact problems previously recited relative to 13 the r gions 14 and 16. Accordingl~, connections from the 14 conductors 18 are not made to these regions. The relative lS spacing between respective conductors 18 is limited by the ~ 16 dimension W3 between the upper sidcs of adjacent via holes, ¦ 17 since there is metal form-ed in these regions. Accordingly, 18 the number of conductors that may be formed in a given area 19 ln such a device is limited by the upper side dir.~ension Wl of the via hole and the spacing dimension W3 between the 21 respective via holes. Also, due to the irregular surface 22 topography of the device 2 it becomes difficult to stack 23 several groups of layers like 8, 10, 12 together, to a 24 n metal level (n=2,3,...) without increasing the dimensions ¦ 25 and thicknesses. Consequently this reduces the number of ~ 26 conductive patterns in the higher metal levels drastically.
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27 Additionally, stacking and bonding of such devices 2 to-~ 28 gether in a desired circuit configuration, beco~es difficult.
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1 Refer now to FIGS. 3 and 4 which illustrate an LSI
2 device 20 having a planar surface adjacent the via holes, ~ :
3 and which is processed in accordance with the present in-4 vention. Also, a device 20 having the same surface area as a device 2 (FIG. 1) can have on the order of twice as many 6 conductors formed thereon due to the planar surface.
7 The device 20 is comprised of a substrate 22 which 8 may comprise a conductive or non-conductive material. By way 9 of example only, the substrate 22 is chosen to be silicon. An insulating layer 24 such as SiO2 is formed over the substrate ll 22. In the event the substrate 22 is non-conductive the 12 insulating layer 24 may be omitted. A conductive layer such 13 as a metal 26 is formed over the insulating layer 24 and the 14 layer 26 as a second insulating layer 28 of SiO2 formed there-on. A via hole 30 is etched, for example, by reactive ion 16 etching techniques, in the layer 28, and a conductive metal 17 pattern layer 32 is deposited over the layer 28 and in the 18 via hole 30. A photolithographic pattern may be developed 19 on the layer 32 such that a plurality of conductors 34 are formed on the top surface of the device 20 bv conventional 21 subtractive etching or lift-off techniques. It is seen, that 22 the respective conductor widths are determined by the width 23 W2 of the via hole 30 which is identical to the lower side 24 dimension W2 of hole 9 in FIG. 2. The spacing between res-pective via holes and conductors is the dimension W3 which 26 is identical to the dimension W3 between via holes as 27 illustrated in FIG. 2. With reference to FIGS. 2 and 4, it 28 is seen that if devices 2 and 20 have the same surface area, I

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8~382 1 three conductors may be formed on the device 20 whereas only 2 two conductors may be formed on the device 2. This is so, 3 since the device 20 has a more planar surface and via holes 4 having identical upper and lower side dimensions which results in a greater conductor packing density for a given surface 6 area at improved interconnection conditions. It may also 7 be seen, that due to the planar surface of the device 20 8 several groups of layers like 26, 28, 30, 32 of equal -9 dimensions and thicknesses can be stacked toge~her to a

10 n metal level structure (n=2,3,). Such devices as 20

11 are more easily stacked and bonded together than are the

12 devices 2 which have an irregular surface topography adjacent

13 the via hole.

14 The metal layer 26 may or may not extend in its plane between adjacent via holes dependent upon the inter-16 connection pattern desired in this plane. In the instance 17 when the layer 26 does not extend between adjacent via holes, -18 the surface topography between the adjacent via holes is 19 irregular in the region W3. This has little, if any, effect when stacking and bonding devices 20, however, since inter-21 connections are made in the surface regions corresponding to 22 where the via holes are formed.
23 Refer now to FIGS. 5A-5N which sequentially illus-24 trate a method for fabricating the LSI device 20. ~IG. 5A
illustrates a substrate 36 which may be conduc~ive or non- -~
26 conductive depending upon whether the resultant LSI device is 27 to be used as a ground plane layer or as an .~-Y plane layer.
28 If the substrate 36 is to be conductive it may, for example, :~
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1 comprise silicon. If, on the other hand, the sub.strate 36 is to non-conductive it may be comprised of a material such as a ceramic or glass. If the substrate 36 is comprised of a conductive material, an insulating layer 38, as shown in FIG. 5B, is formed over the substrate 36 by sputtering, chemical vapor deposition or evaporation.
Silicon oxide (SiO2) is preferred as the insulating layer, however, other insulating layers such as silicon nitride (Si3N4) may be utilized. The insulating layer 38 may have a thickness in the range of 2,000A to 1 micron. If the substrate 36 is non-conductive, the insulating layer 24 may be omitted. Next, as illustrated in FIG. 5C, a conductive metal layer 40 is evaporated or sputtered over the layer 38. Aluminum (Al) is preferred, however, other metals such as copper (Cu) may be utilized. The thickness of layer 40 is on the order of 5,000A to 2 microns. Next, as illustrated in FIG. 5D, a second insulating layer 42 of SiO2 is sputtered over the layer 40 to a thickness on the order of 2,OOOA to 1 micron. As illustrated in FIG. 5E, a masking layer 44 of photoresist, is evaporated onto the layer 42 to a thickness on the order of 1-2 microns. Other suitable resist such as electron beam resist may be utilized. Next, as illustrated in FIG. 5F, a protective metal masking layer 46 is evaporated or sputtered over the masking layer 44, to a thickness on the order of 1,000-5,000A. The metal masking may be Al or Cu.
Then, as illustrated in FIG. 5G a masking layer 48 of photoresist is evaporated over the masking layer 46 to a thickness on the order of 5,000A-1.5 microns.

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1~88382 1 As shown in FIG. 5H, the masking layer 48 comprised of photo-resist is exposed and developed in a selected area by ultraviolet light or an electron beam to define an area 50 where a via hole is to appear. Next, as illustrated in FIG. 5I, the aluminum layer 46 is chemically etched in the defined area 50 to provide a via hole 52 which extends to the surface of photoresist layer 44. The chemi-cal etch may be an acid mixture such as a mixture of phosphoric and nitric acid. Then, as illustrated in FIG. 5J the defined area of masking layer 44 and the masking layer 48 are etched with an etchant that is non-reactive with aluminum for defining a via hole 54 which extends to the surface of the insulating layer 42. Typi-cally, a reactive ion etch such as oxygen is used. Next, as illustrated in FIG. 5K the defined area in insulating layer 42 is -etched with an etchant with is non-reactive with aluminum. A reac-tive ion etch such as carbon tetrafluoride (CF4) is suitable as the etchant. Then, as illustrated in FIG. 5L, a conductive metal layer 58 is evaporated or sputtered onto the metal layer 46 and in the via hole 56, with the metal layer 60 formed in the via hole and layer -58 being of substantially the same thickness as the insulating layer 42. Therefore, the layers 58 and 60 are in the 2,000A to 1 micron range as was insulating layer 42.
As illustrated in FIG. 5M, a double metal lift-off of the metal layers 46 and 58 is accomplished by lifting off or dissolving the photoresist layer 44 by the use of acetone or the like. Since layers 46 and 58 are formed over layer 44, the lifting off of layer 44 also removes layers 46 and 58.

~8i!3382 1 Finally, as illustrated in FIG. 5N, a conductive 2 metal layer 62 of aluminum or the like is evaporated over the 3 insulating layer 42 and the metal portion 60 thereof, result-4 ing in the LSI device 20 as illustrated in FIG. 3.
As prevlously stated with respect to FIG. 4, photo-6 resist may be applied to t.he layer 62 and then by photolitho-7 graphy or the like, a pattern is exposed and developed to 8 define a conductive pattern thereon, which may be similar to 9 the conductive pattern of conductors 34 as illustrated in FIG.. 4. I~ext, areas in which conductors are not defined are 11 etched away by a chemical etchant or by a simple lift-off 12 process or reactive ion etching techniques to yield the con-13 ductive pattern.
14 FIC. 6 illustrates how devices 20 may be utilized with integrated circuit chips or other auxiliary devices.
16 One device 20 is bonded to an integrated circuit chip 62, 17 while another device 20 is connected to a chip interconnection 18 carrier 64. The devices 62 and 64 are interconnected by way 19 of the devices 20 and through solder connections 66 and 68.
It is to be appreciated that other integrated circuit connect-21 ions may be acco~plished through the use of the planar LSI
22 devices 20 set forth in the present invention.

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Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A method of making a device having a planar sur-face, said method comprising the steps of:
(a) metal masking an insulating layer;
(b) defining via holes in said metal masking;
(c) etching to define said via holes in said insulating layer;
(d) depositing a conductive layer on said metal masking and in the defined via holes;
(e) concurrently lifting off said metal masking and the conductive layer formed thereon; and (f) depositing a second conductive layer over said insulat-ing layer; and (g) etching away selected regions of said second conductive layer to form a conductive pattern.

2. A method of making a device having a planar surface, said method comprising the steps of:
(a) depositing a first conductive layer on a substrate;
(b) depositing an insulating layer onto said first con-ductive layer;
(c) depositing a second conductive layer onto said first insulating layer;
(d) etching through a defined area of said second con-ductive layer to the surface of said insulating layer;
(e) etching, with a medium that does not react with said first and second conductive layers, through said insulating layer in the region under said defined area;

(f) depositing a third conductive layer over said second conductive layer and in the etched through defined region of said insulating layer, said third con-ductive layer being of substantially the same thick-ness as said insulating layer;
(g) concurrently lifting off said second and third con-ductive layers from the surface of said insulating layer; and (h) depositing a fourth conductive layer over said in-sulating layer; and (i) etching away selected regions of said fourth con-ductive layer to form a conductive pattern thereon.

3. A method of making an LSI device having a planar surface, said method comprising the steps of:
(a) depositing a first metal layer on a substrate;
(b) depositing an insulating layer over said conductive layer;
(c) metal masking said insulating layer;
(d) defining via holes in said metal masking;
(e) etching to define said via holes in said insulating layer;
(f) depositing a second conductive layer on said metal masking and in the defined via holes, said second conductive layer being of substantially the same thickness as said insulating layer;
(g) concurrently lifting said metal masking and the portion of said second conductive layer formed thereon;
(h) depositing a third conductive layer over said in-sulating layer;
(i) etching away selected regions of said third con-ductive layer to form a conductive pattern thereon.

4. A method of making an LSI device having a planar sur-face, said method comprising the steps of:
(a) depositing a first metal layer on a substrate;
(b) depositing an insulating layer over said first metal layer;
(c) depositing a first masking layer over said first metal layer;
(d) metal masking said first masking layer;
(e) depositing a second masking layer over said metal masking;
(f) defining via holes in said second masking layer;
(g) chemically etching said metal masking area in the region defined in step (f);
(h) etching said second masking layer and the portion of said insulating layer defined by steps (f) and (g), with an etchant that is non-reactive with said first metal layer and said metal masking, to define said via holes;
(i) depositing a second metal layer over said metal mask-ing and in the defined via holes, said second metal layer being of substantially the same thickness as said insulating layer;
(j) dissolving said first masking layer to concurrently lift off said metal masking and said second metal layer from said insulating layer;
(k) depositing a third metal layer on said insulating layer;
(l) exposing and developing a conductive pattern by photo lithography on said third metal layer; and (m) lifting off the portions of said third metal layer which are not defined by said conductive pattern.

5. The method of claim 4 wherein said substrate is an insulator.

6. The method of claim 4 wherein said substrate is conductive.

7. The method of claim 6 including the steps of deposit-ing an insulating layer on the conductive substrate prior to the deposition of said first metal layer.

8. The method of claim 4 wherein said substrate is cera-mic.

9. The method of claim 4 wherein said substrate is silicon.

10. The method of claim 4 wherein said first and second metal layers and said metal masking are each comprised of aluminum.

11. The method of claim 10 wherein said first and second masking layers comprise photoresist.

12. The method of claim 11 wherein said insulating layer comprises silicon oxide.