GB2059679A - Method of making composite bodies - Google Patents
Method of making composite bodies Download PDFInfo
- Publication number
- GB2059679A GB2059679A GB8026540A GB8026540A GB2059679A GB 2059679 A GB2059679 A GB 2059679A GB 8026540 A GB8026540 A GB 8026540A GB 8026540 A GB8026540 A GB 8026540A GB 2059679 A GB2059679 A GB 2059679A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- substrate
- silicon
- inorganic material
- silicon dioxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000002131 composite material Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 239000000463 material Substances 0.000 claims abstract description 33
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 30
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 26
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 25
- 239000010703 silicon Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 24
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 24
- 230000000717 retained effect Effects 0.000 claims description 20
- 238000000151 deposition Methods 0.000 claims description 19
- 230000008021 deposition Effects 0.000 claims description 17
- 229910010272 inorganic material Inorganic materials 0.000 claims description 16
- 239000011147 inorganic material Substances 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 22
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 abstract description 18
- 229910052697 platinum Inorganic materials 0.000 abstract description 9
- 230000000873 masking effect Effects 0.000 abstract description 6
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 22
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 18
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 9
- 229960004838 phosphoric acid Drugs 0.000 description 9
- 235000011007 phosphoric acid Nutrition 0.000 description 9
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 6
- 238000006073 displacement reaction Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001609 comparable effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Weting (AREA)
Abstract
A layer (13) of material is deposited on a substrate (11) through an opening (25) in a masking layer (21), the edges (24a, b) of the masking layer overhanging an aperture in a spacing layer (14), this aperture being formed by etching through opening (25) in masking layer (21). The spacing layer (14) may be silicon dioxide and the masking layer (21) may be a photoresist. Other combinations of materials are mentioned. A layer of platinum is deposited by sputtering to form a Schottky contact to silicon substrate (11), and the masking layer (21) is then removed to carry away the excess metal. The process may be used to form a Schottky diode or a Schottky gate for an FET. <IMAGE>
Description
SPECIFICATION
Method of making composite bodies
The present invention relates in general to a method of making composite bodies for integrated circuits. The present invention relates in particular to a method of forming members of a large variety of materials and of small dimensions on a large variety of substrates.
In carrying out the method of the present invention in accordance with one embodiment thereof a substrate including a surface and constituted of a first material is provided. A first layer of an inorganic etchable material is formed on the surface of the substrate. A second layer of an etch-resistant material having a removed portion and a pair of retained portions is formed on the first layer with adjacent edges of the pair of retained portions having a predetermined spacing. The first layer is etched through the removed portion of the second layer to form an opening therein exposing the surface of the substrate. The walls of the opening underlie the second layer and are spaced from the adjacent edges of the retained portions of the second layer.A second material is vapor-deposited through the removed portion of the second layer and the opening onto the substrate to form the member thereon. The retained portions of the second layer shade the deposition of the second material on the substrate. Thus, the spacing of the pair of edges of the deposited member is determined by the aforementioned predetermined spacing of the edges of the retained portions of the second layer.
the present invention will be further described, by way of example only, with reference to the accompanying drawings in which:
Figure 1 is a plan view of a composite body which includes a substrate of a first material on which is formed a member of a second material in accordance with one embodiment of the present invention,
Figure 2 is a cross-sectional view of the body of Fig. 1 taken along section lines 2-2 thereof.
Figures 3A-3E show cross-sections of structures representing successive steps in one method of fabricating the composite body in accordance with the present invention.
Referring now to Fig. 1 there is shown a composite body fabricated in accordance with the present invention. The composite body 10 includes a substrate 11 of silicon having a surface 12 on which has been formed a conductive member 13 of platinum. The body 10 also includes a layer 14 of silicon dioxide formed on the surface 12 of the substrate 1 1 in the process of formation of the body 10 and is retained thereon as a passivating element of the composite body. The layer 14 has an opening 15 in which is situated the conductive member 13 spaced from the walls 17 and 18 thereof. The conductive member 13 may represent one electrode of a Schottky diode in which the semiconductor substrate is the other electrode. Of course, in such case the substrate 11 would be of monocrystalline semiconductor silicon. The Schottky diode could provide the gate of a junction field effect transistor.Also, the conductive member 13 may constitute a conductive line interconnecting elements of an integrated circuit. The layer 14 of silicon dioxide provides passivation and protection of the surface 12 semiconductor substrate.
The method of fabricating the composite structure or body of Fig. 1 and 2 will now be described in connection with Figs. 3A-3E.
Elements of Figs. 3A-3E identical to the elements of Figs. 1 and 2 are identically designated. A substrate 11 of silicon semiconductor material about 10 mils thick is provided on a surface 12 thereof with a layer 14 of a first silicon dioxide about 5000 Angstroms thick.
A second layer 21 of a photoresist about 5000 Angstroms thick is provided overlying the first layer 14 of silicon dioxide, as shown in Fig. 3A. The second layer 21 is patterned using photoresist masking techniques wellknown in the art to provide a mask having a removed portion 22 and a pair of retained portions 23a and 23b as shown in Fig. 3B.
Edge 24a of retained portion 23a is spaced from edge 24b of retained portion 23b by a predetermined distance 25 which may be quite small, for example, less than 1 micron or 10000 Angstroms. The layer of silicon dioxide 14 is next etched through the removed portion 22 of the layer of photoresist 21 using an etchant to which layer 21 is resistant, for example, buffered hydrofluoric acid, to form an opening 15 in the layer of silicon dioxide 14 exposing the surface 12 of the substrate 11, as shown in Fig. 3C. The walls 17 and 18 of the opening 15 underlie respective unremoved portions 23a and 23b of second layer 21. Wall 17 is spaced from edge 24a of retained portion 23a and wall 18 is spaced from edge 24b of retained portion 23b.In the next step of the process substrate 11, with the patterned layers 14 and 21 thereon, is placed in suitable sputtering apparatus, for example, apparatus such as is disclosed in U.S. Patent No. 3,927,225, for sputtering platinum from a suitable source through the removed portion 22 of the second layer 21 and the opening 15 of the first layer 14 onto the silicon substrate 11. The retained portions 23a and 23b of the resist layer 21 shade the deposition of the platinum particles and thus determine the bounding edges 13a and 13b of the deposited member 13, as shown in Fig. 3D.The member 13 is the result of deposition of platinum from a source spaced a relatively large distance in relation to the dimensions of the opening 15 and essentially in a line orthogonal thereto so that
essentially a collimated beam is utilized to form a steep edge 13a in line with edge 24a
of retained portion 23a and the other steep
edge 13b in line with edge 24b of retained
portion 23b. Thus, the spacing 26 of the edges 13a and 13b is determined by the spacing of the edges 24a and 24b of the
patterned resist layer 21. The thickness of the
deposited member 13a depends upon the time of exposure to the depositing beam of
platinum particles and is shown as a little less than the thickness of the first layer 14.Location of the source of platinum closer to the opening, for example at a distance compara
ble to the spacing between the edges 24a and
24b would cause a displacement of edge 13a outward and also a change in thickness thereof adjacent the edge, and similarly would cause a displacement of the edge 13b outward and also a change in thickness thereof adjacent the edge. Of course, the spreading out of the edges of the member 13 could be extended to cover a portion of the first layer
14 overlying the walls 17 and 18 thereof, if desired, for reasons of passivation, for example. Next in the process, the photoresist layer 21 is removed along with the platinum deposited thereon by dissolution thereof in a suitable photoresist stripper or solvent well known to those skilled in the art to obtain the composite body shown in Fig. 3E.If desired, the silicon dioxide layer 14 may be removed in a suitable etchant such as, for example, buffered hydrofluoric acid. The resultant body of
Fig. 3E would undergo further processing depending on the function to be provided thereby. If desired, other metallic materials such as molybdenum and gold could have been deposited in sequence on the member 13 subsequent to the deposition of platinum to form a composite metal structure. Other conductive materials such as aluminum could be similarly deposited. Also, other non-conductive materials as well may be similarly deposited.
While the invention has been described and illustrated in connection with a composite body in which the substrate is constituted of silicon, the substrate may be constituted of other materials including other semiconductors, and conductors and insulators as well.
While the first layer 14 is shown as constituted of silicon dioxide, other inorganic materials such as silicon nitride may as well be utilized. When silicon nitride is utilized as the first layer material, the substrate may be constituted of silicon dioxide.
While the second layer 21 is shown constituted of an organic photoresist material, a suitable inorganic material may be utilized, for example, silicon nitride or silicon. When the second layer is an inorganic material, such as silicon or silicon nitride, it may be patterned by transfer mask techniques in which the retained portion is masked by a suitably constituted mask and the removable portion thereof is exposed and etched by a selective etch which leaves the underlying first layer relatively unaffected. A process in which silicon is used as a transfer mask is described in
U.S. Patent No. 3,772,102.
When the substrate 11 is silicon, the first layer 14 is silicon dioxide and the second layer 21 is silicon, a suitable etch for etching the first layer would be buffered hydrofluoric acid which selectively etches the first layer without affecting the patterned second layer.
After the deposition of the member 13 on the substrate 11 buffered hydrofluoric acid would be suitable for removal of the layer of silicon dioxide and the layer of silicon thereon. When the substrate 11 is silicon, the first layer 14 is silicon dioxide, and the second layer 21 is silicon nitride, a suitable etch for etching the first layer would be buffered hydrofluoric acid, which selectively etches the first layer without affecting the patterned second layer. After deposition of the member 13 on the substrate 11 hot phosphoric acid would remove the layer of silicon nitride and the material deposited on this layer. Also, in the alternative buffered hydrofluoric acid would remove the layer of silicon dioxide and the overlying layers of materials.
When the substrate 11 is silicon, the first layer 14 is silicon nitride and the second layer 21 is silicon, a suitable selective etch for etching the first layer would be hot phos- phoric acid. After the deposition of the member 13 on the substrate 11 hot phosphoric acid would be suitable for removal of the layer of silicon nitride and the layer of silicon thereon. When the substrate 11 is silicon, the first layer 14 is silicon nitride and the second layer 21 is silicon dioxide, a suitable selective etch for etching the first layer would be hot phosphoric acid. After deposition of the member 13 on the substrate 11 buffered hydrofluoric acid would remove the layer of silicon dioxide and the material deposited on this layer. Also, in the alternative hot phosphoric acid would remove the layer of silicon nitride and the overlying layers of materials.
When the substrate 11 is silicon dioxide, the first layer 14 is silicon nitride and the second layer 21 is silicon dioxide, a suitable etch for etching the first layer would be hot phosphoric acid. After deposition of member 13 on the substrate 11, hot phosphoric acid would remove the layer of silicon nitride and the layer of silicon dioxide thereon. When the substrate 11 is silicon dioxide, the first layer 14 is silicon nitride and the second layer 21 is silicon, a suitable selective etch for etching the first layer would be hot phosphoric acid.
After the deposition of the member 13 on the substrate 11 concentrated potassium hydroxide would remove the layer of silicon and the material deposited on this layer. Also, in the alternative hot phosphoric acid would remove the layer of silicon nitride and the overlying layers of materials.
When the substrate is silicon nitride, the first layer is silicon dioxide and the second layer is silicon nitride, a suitable etch for etching the first layer would be buffered hydrofluoric acid. After deposition of member 13 on the substrate 11, buffered hydrofluoric acid would remove the layer of silicon dioxide and the layer of silicon nitride thereon. When the substrate is silicon nitride, the first layer is silicon dioxide and the second layer is silicon, a suitable selective etch for etching the first layer would be buffered hydrofluoric acid.
After the deposition of member 13 on the substrate 11 concentrated potassium hydroxide would remove the layer of silicon and the material deposited this layer. Also, in the alternative buffered hydrofluoric acid would remove the layer of silicon dioxide and the overlying layers of materials.
Of course, in each of the above examples the etchants utilized to remove the first layer 14 and the second layer 21 after the member 13 has been deposited on the substrate 11 are ones to which the deposited member 13 is resistant.
The advantage of constituting the first layer of an inorganic material, such as silicon dioxide or silicon nitride, in addition to providing structure which may be incorporated in the resultant device fabricate, is that it may be more readily selectively etched without affecting the patterned second layer, particularly if the latter is constituted of an organic photoresist.
When the second layer as well as the first layer is constituted of an inorganic material such as silicon, silicon dioxide or silicon nitride, higher deposition temperatures may be tolerated and thus a variety of deposition processes may be utilized for deposition. This enables a wider variety of materials to be deposited under a wider variety of conditions, for example, with high temperature deposition sources being disposed closer to the first and second layers to effect a desired deposition pattern.
Claims (16)
1. A method of forming on a surface of a substrate of a first material a member of a second material with a pair of edges of a first predetermined spacing which method comprises the steps of:
providing said substrate having said surface,
forming on said surface a first layer of an inorganic etchable material,
forming on said first layer a second layer of an etch resistance material having a removed portion and a pair of retained portions the adjacent edges of said pair of retained portions having a second predetermined spacing,
etching said first layer through said removed portion of said second layer to form an opening in said first layer exposing said surface of said substrate the walls of said opening underlying said second layer and spaced from said adjacent edges of said retained portion thereof,
vapour depositing said second material through said removed portion of said second layer and said opening onto said substrate to form said member on said substrate, said retained portions of said second layer shading the deposition of said second material on said substrate whereby said first predetermined spacing of said pair of edges of said member is predetermined by said second predetermined spacing of the edges of said retained portions of said second layer.
2. A method as claimed in claim 1, wherein the second material is a conductor.
3. A method as claimed in claim 1 or claim 2, wherein the first material is a semiconductor.
4. A method as claimed in claim 3 the semiconductor being silicon.
5. A method as claimed in any one of the preceding claims, wherein the first inorganic material is silicon dioxide.
6. A method as claimed in any one of claims 1 to 4 wherein the first inorganic material is silicon nitride.
7. A method as claimed in claim 1 the second layer being constituted of a photoresist material.
8. A method as claimed in claim 1 wherein the second layer is constituted of a second inorganic material.
9. A method as claimed in claim 8 wherein the first inorganic material is silicon dioxide and said second inorganic material is silicon nitride.
10. A method as claimed in claim 8, wherein the first inorganic material is silicon nitride and second inorganic material is silicon dioxide.
11. A method as claimed in claim 8, wherein the first inorganic material is silicon dioxide and said second inorganic material is silicon.
12. A method as claimed in claim 8, wherein the first inorganic material is silicon nitride and said second inorganic material is silicon.
13. A method as claimed in any one of the preceding claims, in which second layer and the second material deposited thereon is removed.
14. A method as claimed in claim 13 in which said first layer is also removed.
15. A method as claimed in claim 1 substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.
16. A composite body when produced by a method as claimed in any one of the preceding claims.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US7701979A | 1979-09-19 | 1979-09-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2059679A true GB2059679A (en) | 1981-04-23 |
Family
ID=22135628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8026540A Withdrawn GB2059679A (en) | 1979-09-19 | 1980-08-14 | Method of making composite bodies |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5650517A (en) |
| DE (1) | DE3034980A1 (en) |
| FR (1) | FR2466102A1 (en) |
| GB (1) | GB2059679A (en) |
| NL (1) | NL8004573A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0145272A2 (en) * | 1983-11-22 | 1985-06-19 | BRITISH TELECOMMUNICATIONS public limited company | Metal/semiconductor deposition |
| GB2186424A (en) * | 1986-01-30 | 1987-08-12 | Plessey Co Plc | Method for producing integrated circuit interconnects |
| GB2194386A (en) * | 1986-08-20 | 1988-03-02 | Plessey Co Plc | Solder bonded integrated circuit devices |
| FR2643745A1 (en) * | 1989-02-27 | 1990-08-31 | Mitsubishi Electric Corp | METHOD FOR LEVELING A STEP ON A SEMICONDUCTOR SUBSTRATE |
| EP0392642A1 (en) * | 1984-05-15 | 1990-10-17 | Digital Equipment Corporation | Method of filling with a metal layer a recess formed in an integrated circuit chip |
| US5202286A (en) * | 1989-02-27 | 1993-04-13 | Mitsubishi Denki Kabushiki Kaisha | Method of forming three-dimensional features on substrates with adjacent insulating films |
| US5304459A (en) * | 1990-04-27 | 1994-04-19 | Seiko Epson Corporation | At-cut crystal oscillating reed and method of etching the same |
| GB2341276A (en) * | 1998-09-01 | 2000-03-08 | Int Rectifier Corp | Schottky diode with shortened barrier metal contact layer |
| GB2392009A (en) * | 2002-06-14 | 2004-02-18 | Filtronic Compound Semiconduct | Fabrication of solid-state device with improved lift-off |
| FR2914781A1 (en) * | 2007-04-03 | 2008-10-10 | Commissariat Energie Atomique | METHOD FOR MAKING LOCALIZED DEPOSITS |
| CN104425296A (en) * | 2013-09-03 | 2015-03-18 | 丰田自动车株式会社 | Semiconductor device and manufacturing method of semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2431768A1 (en) * | 1978-07-20 | 1980-02-15 | Labo Electronique Physique | Mfg. process for FETs and Schottky diodes - uses only two masks with shadow around lacquer layer ensuring self-alignment of contacts |
-
1980
- 1980-08-12 NL NL8004573A patent/NL8004573A/en not_active Application Discontinuation
- 1980-08-14 GB GB8026540A patent/GB2059679A/en not_active Withdrawn
- 1980-09-17 DE DE19803034980 patent/DE3034980A1/en not_active Withdrawn
- 1980-09-18 FR FR8020128A patent/FR2466102A1/en not_active Withdrawn
- 1980-09-19 JP JP12937180A patent/JPS5650517A/en active Pending
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0145272A3 (en) * | 1983-11-22 | 1985-07-31 | British Telecommunications Plc | Metal/semiconductor deposition |
| US4568411A (en) * | 1983-11-22 | 1986-02-04 | British Telecommunications Plc | Metal/semiconductor deposition |
| EP0145272A2 (en) * | 1983-11-22 | 1985-06-19 | BRITISH TELECOMMUNICATIONS public limited company | Metal/semiconductor deposition |
| EP0392642A1 (en) * | 1984-05-15 | 1990-10-17 | Digital Equipment Corporation | Method of filling with a metal layer a recess formed in an integrated circuit chip |
| GB2186424A (en) * | 1986-01-30 | 1987-08-12 | Plessey Co Plc | Method for producing integrated circuit interconnects |
| GB2194386A (en) * | 1986-08-20 | 1988-03-02 | Plessey Co Plc | Solder bonded integrated circuit devices |
| GB2194386B (en) * | 1986-08-20 | 1990-07-18 | Plessey Co Plc | Solder bonded integrated circuit devices |
| US5202286A (en) * | 1989-02-27 | 1993-04-13 | Mitsubishi Denki Kabushiki Kaisha | Method of forming three-dimensional features on substrates with adjacent insulating films |
| FR2643745A1 (en) * | 1989-02-27 | 1990-08-31 | Mitsubishi Electric Corp | METHOD FOR LEVELING A STEP ON A SEMICONDUCTOR SUBSTRATE |
| US5314577A (en) * | 1990-04-26 | 1994-05-24 | Seiko Epson Corporation | At-cut crystal oscillating reed and method of etching the same |
| US5304459A (en) * | 1990-04-27 | 1994-04-19 | Seiko Epson Corporation | At-cut crystal oscillating reed and method of etching the same |
| US5376861A (en) * | 1990-04-27 | 1994-12-27 | Seiko Epson Corporation | At-cut crystal oscillating reed and method of etching the same |
| GB2341276A (en) * | 1998-09-01 | 2000-03-08 | Int Rectifier Corp | Schottky diode with shortened barrier metal contact layer |
| GB2392009A (en) * | 2002-06-14 | 2004-02-18 | Filtronic Compound Semiconduct | Fabrication of solid-state device with improved lift-off |
| FR2914781A1 (en) * | 2007-04-03 | 2008-10-10 | Commissariat Energie Atomique | METHOD FOR MAKING LOCALIZED DEPOSITS |
| WO2008125511A1 (en) * | 2007-04-03 | 2008-10-23 | Commissariat A L'energie Atomique | Method of depositing localized coatings |
| US8815108B2 (en) | 2007-04-03 | 2014-08-26 | Commissariat A L'energie Atomique | Method of depositing localized coatings |
| CN104425296A (en) * | 2013-09-03 | 2015-03-18 | 丰田自动车株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| CN104425296B (en) * | 2013-09-03 | 2017-11-10 | 丰田自动车株式会社 | The manufacture method of semiconductor device and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5650517A (en) | 1981-05-07 |
| FR2466102A1 (en) | 1981-03-27 |
| NL8004573A (en) | 1981-03-23 |
| DE3034980A1 (en) | 1981-04-02 |
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