FR2431768A1 - Mfg. process for FETs and Schottky diodes - uses only two masks with shadow around lacquer layer ensuring self-alignment of contacts - Google Patents

Mfg. process for FETs and Schottky diodes - uses only two masks with shadow around lacquer layer ensuring self-alignment of contacts

Info

Publication number
FR2431768A1
FR2431768A1 FR7821515A FR7821515A FR2431768A1 FR 2431768 A1 FR2431768 A1 FR 2431768A1 FR 7821515 A FR7821515 A FR 7821515A FR 7821515 A FR7821515 A FR 7821515A FR 2431768 A1 FR2431768 A1 FR 2431768A1
Authority
FR
France
Prior art keywords
layer
lacquer
alignment
contacts
mfg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7821515A
Other languages
French (fr)
Other versions
FR2431768B1 (en
Inventor
Dominique Boccon-Gibod
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Laboratoires dElectronique Philips SAS
Original Assignee
Laboratoires dElectronique et de Physique Appliquee
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Laboratoires dElectronique et de Physique Appliquee filed Critical Laboratoires dElectronique et de Physique Appliquee
Priority to FR7821515A priority Critical patent/FR2431768A1/en
Publication of FR2431768A1 publication Critical patent/FR2431768A1/en
Application granted granted Critical
Publication of FR2431768B1 publication Critical patent/FR2431768B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors

Abstract

The semiconductor mfr. technique includes covering a layer of semi-insulating material of gallium arsenide (11) with a first layer of semiconductor material (12), a second layer of metal (13) and a third layer of photosensitive lacquer (14). Part of the lacquer is subject to UV light, and then the exposed part is dissolved, and the metal (aluminium) is attacked with hot orthophosphoric acid. The aluminium is totally removed and it is undercut to a depth of about one micron. The ohmic contacts are applied through the windows which have been produced, by evaporation of a gold-germanium metal layer (15). The shadow effect of the lacquer mask provides precise self-alignment of the ohmic contacts. A further layer of lacquer is then applied exposed through a mask and partially dissolved in the subsequent formation of a Schottky contact.
FR7821515A 1978-07-20 1978-07-20 Mfg. process for FETs and Schottky diodes - uses only two masks with shadow around lacquer layer ensuring self-alignment of contacts Granted FR2431768A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7821515A FR2431768A1 (en) 1978-07-20 1978-07-20 Mfg. process for FETs and Schottky diodes - uses only two masks with shadow around lacquer layer ensuring self-alignment of contacts

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7821515A FR2431768A1 (en) 1978-07-20 1978-07-20 Mfg. process for FETs and Schottky diodes - uses only two masks with shadow around lacquer layer ensuring self-alignment of contacts

Publications (2)

Publication Number Publication Date
FR2431768A1 true FR2431768A1 (en) 1980-02-15
FR2431768B1 FR2431768B1 (en) 1982-04-16

Family

ID=9210948

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7821515A Granted FR2431768A1 (en) 1978-07-20 1978-07-20 Mfg. process for FETs and Schottky diodes - uses only two masks with shadow around lacquer layer ensuring self-alignment of contacts

Country Status (1)

Country Link
FR (1) FR2431768A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2466102A1 (en) * 1979-09-19 1981-03-27 Gen Electric METHOD FOR MANUFACTURING COMPOSITE ELEMENTS FOR INTEGRATED CIRCUITS
FR2643745A1 (en) * 1989-02-27 1990-08-31 Mitsubishi Electric Corp METHOD FOR LEVELING A STEP ON A SEMICONDUCTOR SUBSTRATE
US5202286A (en) * 1989-02-27 1993-04-13 Mitsubishi Denki Kabushiki Kaisha Method of forming three-dimensional features on substrates with adjacent insulating films

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3866310A (en) * 1973-09-07 1975-02-18 Westinghouse Electric Corp Method for making the self-aligned gate contact of a semiconductor device
FR2302592A1 (en) * 1975-02-26 1976-09-24 Nippon Electric Co DOUBLE DOOR SCHOTTKY BARRIER FIELD EFFECT TRANSISTOR
FR2369689A1 (en) * 1976-10-29 1978-05-26 Western Electric Co FIELD-EFFECT MICROMINIATURE TRANSISTOR AND GALLIUM ARSENIDE AND ITS REALIZATION PROCESS

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3866310A (en) * 1973-09-07 1975-02-18 Westinghouse Electric Corp Method for making the self-aligned gate contact of a semiconductor device
FR2302592A1 (en) * 1975-02-26 1976-09-24 Nippon Electric Co DOUBLE DOOR SCHOTTKY BARRIER FIELD EFFECT TRANSISTOR
FR2369689A1 (en) * 1976-10-29 1978-05-26 Western Electric Co FIELD-EFFECT MICROMINIATURE TRANSISTOR AND GALLIUM ARSENIDE AND ITS REALIZATION PROCESS

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2466102A1 (en) * 1979-09-19 1981-03-27 Gen Electric METHOD FOR MANUFACTURING COMPOSITE ELEMENTS FOR INTEGRATED CIRCUITS
FR2643745A1 (en) * 1989-02-27 1990-08-31 Mitsubishi Electric Corp METHOD FOR LEVELING A STEP ON A SEMICONDUCTOR SUBSTRATE
US5202286A (en) * 1989-02-27 1993-04-13 Mitsubishi Denki Kabushiki Kaisha Method of forming three-dimensional features on substrates with adjacent insulating films

Also Published As

Publication number Publication date
FR2431768B1 (en) 1982-04-16

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Legal Events

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