JPS6424466A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6424466A
JPS6424466A JP18053287A JP18053287A JPS6424466A JP S6424466 A JPS6424466 A JP S6424466A JP 18053287 A JP18053287 A JP 18053287A JP 18053287 A JP18053287 A JP 18053287A JP S6424466 A JPS6424466 A JP S6424466A
Authority
JP
Japan
Prior art keywords
layer
sio2
protected
dry etching
damage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18053287A
Other languages
Japanese (ja)
Inventor
Haruo Kawada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18053287A priority Critical patent/JPS6424466A/en
Publication of JPS6424466A publication Critical patent/JPS6424466A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To improve GaAs MESFETs in reproducibility and uniformity of their electrical characteristics by a method wherein an FET-forming region on an S.I.GaAs substrate is protected from damage attributable to plasma-using dry etching in a GaAs MESFET manufacturing process. CONSTITUTION:On an AlN layer 5, an SiO2 layer 6 is formed as a spacer insulating film. Next, the SiO2 layer 6 is subjected to dry etching with a photoresist 21 serving as a mask, when a Schottky gate-forming region on the surface of an S.I.GaAs substrate 1 is protected from damage because it is covered by the AlN layer 5. A high-melting metal layer 7 is formed on a Schottky gate opening and SiO2 layer 6 and, for the elimination of abrupt steps, flattening photoresist is applied. A plasma-using dry etching process is accomplished for the removal of the high-melting metal layer 7 from above the SiO2 6, when the surface of the S.I.GaAs substrate 1 is protected from damage because it is covered by the AlN layer 5 and the high-melting metal layer 7. The remnant of the SiO2 layer 6 or of the AlN layer 5 is removed for the formation of a Schottky gate 8 in a prescribed region.
JP18053287A 1987-07-20 1987-07-20 Manufacture of semiconductor device Pending JPS6424466A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18053287A JPS6424466A (en) 1987-07-20 1987-07-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18053287A JPS6424466A (en) 1987-07-20 1987-07-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6424466A true JPS6424466A (en) 1989-01-26

Family

ID=16084911

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18053287A Pending JPS6424466A (en) 1987-07-20 1987-07-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6424466A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01244666A (en) * 1988-03-25 1989-09-29 Nec Corp Manufacture of semiconductor device
US5484740A (en) * 1994-06-06 1996-01-16 Motorola, Inc. Method of manufacturing a III-V semiconductor gate structure
US5688703A (en) * 1995-09-05 1997-11-18 Motorola, Inc. Method of manufacturing a gate structure for a metal semiconductor field effect transistor
US6008136A (en) * 1996-12-11 1999-12-28 Nec Corporation Method for manufacturing semiconductor device capable of improving etching rate ratio of insulator to refractory metal
JP2008221486A (en) * 2007-03-08 2008-09-25 Idemitsu Unitech Co Ltd Multilayered tape, its manufacturing method and packaging bag

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01244666A (en) * 1988-03-25 1989-09-29 Nec Corp Manufacture of semiconductor device
US5484740A (en) * 1994-06-06 1996-01-16 Motorola, Inc. Method of manufacturing a III-V semiconductor gate structure
US5688703A (en) * 1995-09-05 1997-11-18 Motorola, Inc. Method of manufacturing a gate structure for a metal semiconductor field effect transistor
US6008136A (en) * 1996-12-11 1999-12-28 Nec Corporation Method for manufacturing semiconductor device capable of improving etching rate ratio of insulator to refractory metal
US6214744B1 (en) * 1996-12-11 2001-04-10 Nec Corporation Method for manufacturing semiconductor device capable of improving etching rate ratio of insulator to refractory metal
JP2008221486A (en) * 2007-03-08 2008-09-25 Idemitsu Unitech Co Ltd Multilayered tape, its manufacturing method and packaging bag

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