JPS6077467A - Manufacture of field effect transistor - Google Patents
Manufacture of field effect transistorInfo
- Publication number
- JPS6077467A JPS6077467A JP18448883A JP18448883A JPS6077467A JP S6077467 A JPS6077467 A JP S6077467A JP 18448883 A JP18448883 A JP 18448883A JP 18448883 A JP18448883 A JP 18448883A JP S6077467 A JPS6077467 A JP S6077467A
- Authority
- JP
- Japan
- Prior art keywords
- film
- region
- type
- electrode
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 230000005669 field effect Effects 0.000 title claims description 9
- 150000002500 ions Chemical class 0.000 claims abstract description 18
- 238000002844 melting Methods 0.000 claims abstract description 12
- 230000008018 melting Effects 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 abstract description 16
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 13
- 239000007772 electrode material Substances 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 239000002344 surface layer Substances 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000000137 annealing Methods 0.000 description 5
- 230000004913 activation Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000005275 alloying Methods 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
- H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
- H01L29/66863—Lateral single gate transistors
- H01L29/66878—Processes wherein the final gate is made before the formation, e.g. activation anneal, of the source and drain regions in the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
本発明は、化合物半導体を用いた電界効果トランジスタ
の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a field effect transistor using a compound semiconductor.
（従来技術）
従来の化合物半導体電界効果トランジスタ例えは’ Ｇ
ａＡｓＭＥＳＦＥＴにおいては、ダート電極材として高
融点金属を用いたセルファライン構造が知られており、
そこではケ゛−ト電極を形成した後で、所１のｎ＋高濃
度注入層を形成し、その活性化アニールが行われ、その
アニール温度として８００℃〜９００℃程度までは保証
されている。(Prior art) An example of a conventional compound semiconductor field effect transistor is 'G
In aAs MESFET, a self-line structure using a high melting point metal as the dart electrode material is known.
In this method, after forming the gate electrode, a first n+ high concentration implantation layer is formed and activation annealing is performed, and the annealing temperature is guaranteed to be about 800 DEG C. to 900 DEG C.
他方、オーミック接触を得るための形成方法については
、ＡｕＧｅ／ＧａＡｓとの合金板あるいはＡｕＧｅ／Ｎ
ｉ／Ａｕ電極を利用した合金反応が広く行われていて、
その際の合金化温度としては４００℃〜４５０℃程度が
採用されている。On the other hand, regarding the formation method for obtaining ohmic contact, an alloy plate with AuGe/GaAs or an AuGe/N
Alloy reactions using i/Au electrodes are widely carried out,
The alloying temperature at this time is approximately 400°C to 450°C.
しかしながら、オーミック接触を形成する場合その合金
化処理工程において、例えばＧａＡｓとＡｕＧｅとの界
面に凸凹が生じ易く、又オーミック電極の表面モホロジ
ー（状態）の悪化などによるボールアップ現象が発生し
易い。よってＦＥＴを作製する場合、オーミック電極を
形成した後はオーミック処理温度以上の熱処理は適当で
はない。However, when forming an ohmic contact, in the alloying process, for example, unevenness tends to occur at the interface between GaAs and AuGe, and a ball-up phenomenon tends to occur due to deterioration of the surface morphology (condition) of the ohmic electrode. Therefore, when manufacturing an FET, heat treatment at a temperature higher than the ohmic processing temperature is not appropriate after forming the ohmic electrode.
従ってこのようなオーミック電極材を用いた従来の製造
方法においては、オーミック電極の形成工程の手順が特
定され、例えばＧａＡｓＭＥＳＦＥＴ を一つの構成要
素とする大規模回路を実現する場合、製造工程の自由度
が大幅に制約を受ける欠点があった。Therefore, in conventional manufacturing methods using such ohmic electrode materials, the procedure for forming the ohmic electrode is specified, and for example, when realizing a large-scale circuit with GaAs MESFET as one component, the degree of freedom in the manufacturing process is limited. However, it had the disadvantage of being severely restricted.
（発明の目的）
本発明はゲート電極及びオーミック電極の形成工程の前
後如伺を問わず、アニールを行なえるようにした電解効
果トランジスタの製造方法を提供することにある。(Object of the Invention) An object of the present invention is to provide a method for manufacturing a field effect transistor in which annealing can be performed before or after the step of forming the gate electrode and the ohmic electrode.
（発明の構成）
本発明はオーミック電極を形成する工程を含む電界効果
トランジスタの製造方法において、化合物半導体基板上
のオーミック電極形成予定領域にＧｅ膜を形成し、との
Ｇｅ膜に高濃度のＡｓイオンを注入し、しかも前記基板
の前記Ｇｅ膜直下の領域に高濃度のｎ形不純物イオンを
注入する工程と、その後ショットキ接合を形成しうる高
融点金属で前記基板上にショットキ電極とオーミック電
極を同時に形成する工程を含むことを特徴とした電界効
果トランジスタの製造方法である。(Structure of the Invention) The present invention provides a method for manufacturing a field effect transistor including a step of forming an ohmic electrode, in which a Ge film is formed in a region where the ohmic electrode is to be formed on a compound semiconductor substrate, and a high concentration of As is added to the Ge film. A step of implanting ions and implanting highly concentrated n-type impurity ions into a region directly under the Ge film of the substrate, and then forming a Schottky electrode and an ohmic electrode on the substrate using a high melting point metal capable of forming a Schottky junction. A method of manufacturing a field effect transistor characterized by including a step of forming simultaneously.
（実施例）
第１図ないし第１Ｏ図は本発明の一実施例の説明図であ
）、図面に沿って説明する。(Embodiment) FIGS. 1 to 1O are explanatory diagrams of an embodiment of the present invention), and will be explained along with the drawings.
まず半絶縁ＧａＡｓ基板の全面に耐熱オーミック材料で
あるＧｅ膜を被着し、レノストを用いてパターンニング
することによって、第１図に示すように、半絶縁ＧａＡ
ｓ基板１のオーミック接触予定表面にＧｅ膜２を被着形
成する。その際、レノストパターン３は次の工程のため
に残しておく。First, a Ge film, which is a heat-resistant ohmic material, is deposited on the entire surface of a semi-insulating GaAs substrate, and patterned using renost, as shown in Figure 1.
A Ge film 2 is deposited on the surface of the s-substrate 1 where ohmic contact is to be made. At that time, the Renost pattern 3 is left for the next process.
次にイオン阻止能の高いＮｉ膜を全面に被着し、リフト
オフ法によってそのＮｉ膜を・ぞターノニングすること
によって、第２図に示すように、Ｇｅ膜２が被着された
表面以外の表面にＮ１マスク４を被着形成する。Next, a Ni film with high ion-stopping ability is deposited on the entire surface, and by turning the Ni film by a lift-off method, the surfaces other than the surface on which the Ge film 2 is deposited are An N1 mask 4 is deposited on the surface.
次に第３図に示すように、Ｎ１マスク４をマスクとして
ｎ形イオン注入を行い、Ｇｅ膜２をｎ＋＋形イオン注入
Ｇｅ膜２′とし、その直下領域をｎ＋＋形イオン注入領
域５とする。Ｇｅ膜２へのイオン注入は、へ８イオンを
用い、イオン注入Ｇｅ膜２′の膜厚方向中央でのピーク
イオン濃度が１０２０／ｃｒｎ８になるようにするのが
よい。直下領域へのイオン注入は、Ｓｉイオンを用１／
ｓ Ｎ ｎ ” ”形イオン注入領域５のイオン濃度が
５ ｘ １０１８／副３程度となるように行うのがよい
Ｏ
次にＮｉマスク４を除去することによって、第４図に示
すように、オーミック接触予定表面にＡｓイオンが注入
されたＧｅ膜２′が被着形成され、その直下にｎ＋＋形
イオン注入領域５が形成されたものを作る。Next, as shown in FIG. 3, n-type ions are implanted using the N1 mask 4 as a mask, so that the Ge film 2 is made into an n++-type ion-implanted Ge film 2', and the region immediately below it is made into an n++-type ion-implanted region 5. For ion implantation into the Ge film 2, it is preferable to use He8 ions so that the peak ion concentration at the center in the film thickness direction of the ion-implanted Ge film 2' is 1020/crn8. Ion implantation into the region directly below uses Si ions.
It is preferable to perform the ion implantation so that the ion concentration in the s N n "" type ion implantation region 5 is about 5 x 1018/3. Next, by removing the Ni mask 4, as shown in FIG. A Ge film 2' implanted with As ions is deposited on the surface to be contacted, and an n++ type ion implantation region 5 is formed immediately below it.
次に第５図に示すように、レノストノやター７６を形成
したのち、これをマスクとして活性領域となる領域を含
む領域にイオン濃度が１０”／ｃｍ３程度となるように
ｎ形不純物であるＳｉイオンをイオン注入し、ｎ形イオ
ン注入領域７とする。Next, as shown in FIG. 5, after forming a layer 76, using this as a mask, Si, which is an n-type impurity, is added so that the ion concentration is about 10''/cm3 in the region including the region that will become the active region. Ions are implanted to form an n-type ion implantation region 7.
次に前記レノスト・母ターン６を除去したのち第６図に
示すように、ＧａＡｓｎ形活性層との間ショットキ接合
を形成できる高融点金属である、Ｗ−Ａｔ膜８を全面に
被着する。Next, after removing the Renost/mother turn 6, as shown in FIG. 6, a W-At film 8, which is a high melting point metal capable of forming a Schottky junction with the GaAsn type active layer, is deposited over the entire surface.
次にＮｉ膜を全面に被着し、その後ツクターフ二／グす
ることによって、第７図に示すように、ゲート電極を形
成すべき表面とｎ＋＋形イオン注入Ｇｅ膜２′の表面と
を被うＮｉマスク９を被着形成する。Next, by depositing a Ni film on the entire surface and then performing a double coating, the surface on which the gate electrode is to be formed and the surface of the n++ type ion-implanted Ge film 2' are covered, as shown in FIG. A Ni mask 9 is deposited and formed.
次に第８図に示すように、前記Ｎｉマスク９をマスクと
して、高融点金属でちるＷ−Ａｔ膜８をノＲターンニン
グし、ダート電極８ａ及びオーミック電極被覆８ｂを形
成する。Next, as shown in FIG. 8, using the Ni mask 9 as a mask, the W-At film 8 made of a high melting point metal is subjected to R-turning to form a dirt electrode 8a and an ohmic electrode coating 8b.
次に第９図に示すように、ＧａＡ６魔５ＦＥＴ 以外の
領域を被うレノスト・ぞターン１０を形成したのち、ｎ
＋＋形イオン注入領域５とケ゛−ト電極８ａとの間にイ
オン濃度１．０１８ｏｎ−６程度でＳｉイオンをイオン
注入し、ｎ＋形イオン注入領域１ノを形成する。Next, as shown in FIG.
Si ions are implanted between the + type ion implantation region 5 and the gate electrode 8a at an ion concentration of about 1.018 on -6 to form an n + type ion implantation region 1.
次にＮｉマスク９及びレジストノやターン１０を除去し
たのち、第１０図に示すように、ｎ＋＋形イオン注入Ｇ
ｅ膜２′、ｎ＋＋イオン注入領域５、活性領域用のイオ
ン注入領域７及びｎ＋イオン注入領域１１の不純物を活
性化するために５１０２膜１２を全面に被着したのち、
８００℃程度の温度で２０分間程度のアニールを行う。Next, after removing the Ni mask 9 and the resist holes and turns 10, as shown in FIG.
After depositing the 5102 film 12 on the entire surface in order to activate the impurities in the e film 2', the n++ ion implantation region 5, the ion implantation region 7 for active region, and the n+ ion implantation region 11,
Annealing is performed at a temperature of about 800° C. for about 20 minutes.
その後、ＳｉＯ□膜１２の所定個所に窓を開けることに
よってＧａＡｓＭＦＪＳＦＥＴは完成する。Thereafter, the GaAs MFJSFET is completed by opening windows at predetermined locations in the SiO□ film 12.
以上説明したように、この実施例では、高融点金属であ
るＷ−Ａ４膜でケ゛−ト電極を構成し、且つそのＷ−Ａ
ｔ膜とＡ８イオンによるｎ”Ｇｅ膜とでオーミック電極
を形成しているため、電極材の被着形成後に活性化アニ
ールを行っても、ＧａＡｓ／Ｇｅ界面、Ｇｅ／’Ｎ−Ａ
１界面および電極表面状態は良好であシ、従って全ての
領域の活性化を一度に行うことができる。As explained above, in this embodiment, the gate electrode is composed of the W-A4 film, which is a high melting point metal, and the W-A film is made of a high melting point metal.
Since the ohmic electrode is formed by the t film and the n'Ge film made of A8 ions, even if activation annealing is performed after the electrode material is deposited, the GaAs/Ge interface, Ge/'N-A
The interface and electrode surface conditions are good, so activation of all regions can be performed at once.
また、この実施例では、中間にｎ＋形領領域形成した構
造となっているので、ダート電極直下へのｎ形不純物の
横方向拡散を考慮することなく、オーミック電極直下の
ｎ＋＋形領域を十分高濃度にでき、従って寄生抵抗を低
減することができる。Furthermore, since this embodiment has a structure in which an n+ type region is formed in the middle, the n++ type region directly under the ohmic electrode can be raised sufficiently without considering the lateral diffusion of n type impurities directly under the dart electrode. concentration, thus reducing parasitic resistance.
なおまた、第１０図の工程の後、検査した結果、しきい
値が所定の値でなかった場合などにおいては、更に活性
領域７へのイオン注入とアニールを追加して行うことが
できるなどの利点がある。Furthermore, if the threshold value is not the predetermined value as a result of the inspection after the process shown in FIG. There are advantages.
なお、第４図の構造１では、半絶縁ＧａＡｓ基板１に、
まず第２図相当のＮ１マスクを形成し、次いでＧｅ膜２
を全面被着し、その後所定のイオン注入を行い、その後
Ｎ１マスク４及びその上のＧｅ膜を除去することによっ
ても作ることができる。Note that in the structure 1 in FIG. 4, the semi-insulating GaAs substrate 1 is
First, an N1 mask corresponding to FIG. 2 is formed, and then a Ge film 2
It can also be made by depositing on the entire surface, then performing predetermined ion implantation, and then removing the N1 mask 4 and the Ge film thereon.
また、活性領域７を形成するだめのイオン注入は、例え
ば第２図の工程前で行うなど、比較的随時の手順で行う
ことができる。Further, the ion implantation for forming the active region 7 can be performed relatively at any time, for example, before the process shown in FIG. 2.
また、ゲート電極及びオーミック電極のカバーとして用
いる高融点金属は、素子間配線を兼ねさせることもでき
る。Furthermore, the high melting point metal used as the cover for the gate electrode and the ohmic electrode can also serve as inter-element wiring.
（発明の効果）
本発明は高融点金属によりケ゛−ト電極を形成し、これ
ト同一の工程においてオーミック電極材を前記高融点金
属で覆いあるいは更に前記高融点金属を配線パターンに
利用できるため、オーミック電極の形成手順が特定され
ることなく電界効果トランゾスタを一つの構成要素とす
る大規模回路の製造に利用することができる。(Effects of the Invention) In the present invention, the gate electrode is formed from a high melting point metal, and in the same process, the ohmic electrode material can be covered with the high melting point metal, or the high melting point metal can be further used for the wiring pattern. The method can be used to manufacture large-scale circuits including field effect transistors as one component, without specifying the procedure for forming ohmic electrodes.
第１図ないし第１０図は、本発明の実施例におけるＧａ
ＡｓＭＥＳＦＥＴの構造断面図である。
１・・・半絶縁ＧａＡｓ基板、２・・・Ｇｅ膜、２′・
・・ｎ＋＋形イオン注入Ｇｅ膜、３・・・レジストパタ
ーン、４・・・Ｎｉマスク、５・・・ＧａＡｓ ｎ”形
イオン注入領域、６・・・レジストパターン、７・・・
ＧａＡｓ活性領域用イオン注入領域、８ ・Ｗ−Ａｔ膜
、８ ａ−Ｗ−Ａｔ）ｆ”−ト電極、８ｂ・・・Ｗ−Ａ
Ａオーミック雷接極被覆９・・・Ｎｉマスク、１０・・
・レジストパターン、１１・・・ＧａＡｓ ｎ＋形イオ
ン注入領域、１２・・・Ｓ ｉｏ ２膜特許出願人 沖
電気工業株式会社
第１図
第２図
第５図
第７図FIG. 1 to FIG. 10 show Ga in the embodiment of the present invention.
It is a structural sectional view of AsMESFET. 1... Semi-insulating GaAs substrate, 2... Ge film, 2'.
... n++ type ion-implanted Ge film, 3... resist pattern, 4... Ni mask, 5... GaAs n'' type ion implanted region, 6... resist pattern, 7...
Ion implantation region for GaAs active region, 8 ・W-At film, 8 a-W-At)f''-to electrode, 8b...W-A
A Ohmic lightning polarization coating 9...Ni mask, 10...
・Resist pattern, 11...GaAs n+ type ion implantation region, 12...S io 2 film patent applicant Oki Electric Industry Co., Ltd. Figure 1 Figure 2 Figure 5 Figure 7
Claims (1)
スタの製造方法において、化合物半導体基板上のオーミ
ック電極形成予定領域にＧｅ膜を形成し、とのＧｅ膜に
高濃度のＡｓイオンを注入し、しかも前記基板の前記Ｇ
ｅ膜膜下下領域に高濃度のｎ形不純物イオンを注入する
工程と、その後ショットキ接合を形成しうる高融点金属
で前記基板上にショットキ電極とオーミック電極とを同
時に形成する工程を含むことを特徴とした電界効果トラ
ンジスタの製造方法。In a method for manufacturing a field effect transistor including a step of forming an ohmic electrode, a Ge film is formed in a region where an ohmic electrode is to be formed on a compound semiconductor substrate, a high concentration of As ions is implanted into the Ge film, and The above G
A step of implanting n-type impurity ions at a high concentration into a region under the e-film, and a step of simultaneously forming a Schottky electrode and an ohmic electrode on the substrate using a high melting point metal capable of forming a Schottky junction. Characteristic method for manufacturing field effect transistors.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18448883A JPS6077467A (en) | 1983-10-04 | 1983-10-04 | Manufacture of field effect transistor |
| US06/602,578 US4540446A (en) | 1983-09-19 | 1984-04-20 | Method of forming ohmic contact on GaAs by Ge film and implanting impurity ions therethrough |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18448883A JPS6077467A (en) | 1983-10-04 | 1983-10-04 | Manufacture of field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6077467A true JPS6077467A (en) | 1985-05-02 |
| JPH028457B2 JPH028457B2 (en) | 1990-02-23 |
Family
ID=16154048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18448883A Granted JPS6077467A (en) | 1983-09-19 | 1983-10-04 | Manufacture of field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6077467A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01158778A (en) * | 1987-12-15 | 1989-06-21 | Fujitsu Ltd | Manufacture of semiconductor device |
| JP2005245968A (en) * | 2004-03-08 | 2005-09-15 | Tetsuo Tokuda | Bedding cover |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5425171A (en) * | 1977-07-27 | 1979-02-24 | Fujitsu Ltd | Manufacture of field effect semiconductor device |
| US4188710A (en) * | 1978-08-11 | 1980-02-19 | The United States Of America As Represented By The Secretary Of The Navy | Ohmic contacts for group III-V n-type semiconductors using epitaxial germanium films |
| JPS5698877A (en) * | 1980-01-08 | 1981-08-08 | Mitsubishi Electric Corp | Gaas field effect transistor |
-
1983
- 1983-10-04 JP JP18448883A patent/JPS6077467A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5425171A (en) * | 1977-07-27 | 1979-02-24 | Fujitsu Ltd | Manufacture of field effect semiconductor device |
| US4188710A (en) * | 1978-08-11 | 1980-02-19 | The United States Of America As Represented By The Secretary Of The Navy | Ohmic contacts for group III-V n-type semiconductors using epitaxial germanium films |
| JPS5698877A (en) * | 1980-01-08 | 1981-08-08 | Mitsubishi Electric Corp | Gaas field effect transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01158778A (en) * | 1987-12-15 | 1989-06-21 | Fujitsu Ltd | Manufacture of semiconductor device |
| JP2005245968A (en) * | 2004-03-08 | 2005-09-15 | Tetsuo Tokuda | Bedding cover |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH028457B2 (en) | 1990-02-23 |
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