JPS6323368A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor device with high performance and excellent reproducibility and low in gate electrode resistance and source parasitic resistance, by a method wherein a metallic film as a feeder electrode for metallic plating is formed on the surfaces of a gate electrode through the intermediary of a dielectric film. CONSTITUTION:A semiconductor substrate 21 comprising GaAs containing chrome is selectively implanted with Si<+> ion 29 to form an n type layer 22. Overall surface is coated with W5Si3(high melting point metal) and then selectively processed to form a gate electrode 24. The substrate 21 is implanted with Si<+> ion 29 again using the gate electrode 24 as a mask to provide n<+>type layers 23 on both sides of gate electrode 24. The overall surface of a wafer is coated with an SiO2 film 11 to be annealed in hydrogen atmosphere. After coating the overall surface with the first photoresist layer 12, the SiO2 film 11 on the surface and sides of the first photoresist layer 12 and the gate electrode 24 is removed to expose the surface and sides of the first photoresist layer 12 and the gate electrode 24 is removed to expose the surface 32 and the upper part 33 of sides of the gate electrode 24. Finally, after removing he first photoresist layer 12, Ti and Au are successively evaporated on the overall surface to form a TiAu film 31.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a single conductor device, and more particularly to a method for manufacturing a semiconductor device in which a Schottky barrier gate electrode is provided on a semiconductor conductive layer.

], Conventional technology゛] Semi-insulating 16 (semiconductor conductive layer formed on a board)
+ -:/l□Key barrier Semiconductor device provided with gate type electrode, for example, Schottkyd using gallium arsenide◇: Wall gate type field effect transistor (hereinafter referred to as GaAs)
(referred to as MIESFIΣ′F)
It is a semiconductor device that operates in the high frequency band of 1z), and is one of the important semiconductor devices that will support the advanced information society of the future.

In order to improve the frequency characteristics of such GaAs MESF, T, it is essential to reduce the gate electrode resistance R6 and the source parasitic resistance Rs.

For this reason, conventional G
aAs MESFET has been proposed.

In FIG. 2, 21 is a semi-insulating substrate made of GaAs, 22 is an n-type layer formed by, for example, ion implantation, and 2
3 is a low resistance n+ type layer selectively formed on both sides of the Schottky barrier gate electrode 24, 25 is an Au plating layer for reducing gate resistance, and 26 and 27 are source and drain electrodes, respectively. Such GaAs MESF
In ET, A, RG due to the presence of the plating layer 25
is small, and due to the presence of the n+ type layer 23, R3 is also reduced.

Next, GaAs MES with the structure shown in FIG.
Figure 3 (a) to (d) shows the conventional manufacturing method of FET.
).

First, as shown in FIG. 3(a), n impurities are implanted by first ion implantation into a semi-insulating substrate 21 made of GaAs to form an n layer 22, and this n-type layer 22-1 =, for example, tungsten silicide (WSi)
Next, using gate electrode 2/1 as a mask, second ion implantation is performed to form n+ type layers 23 on both sides of gate electrode 24. Here, the first ion implantation was carried out under the conditions of an acceleration voltage of 30 keV, a dose of 3 x 1, and 0' 2 cm "" (S i + ions), and the second ion implantation was carried out at 100 eV and 3 cm.
This is carried out under the condition of X 10 "cm-3 (si+ ions). The length of the upper layer of the gate electrode made of WSi is, for example, 1 μm.

Next, as shown in FIG. 3(b), after activating the implanted ions, a Ti^'1 film 31 is deposited on the entire surface, and the first
After applying a photoresist layer 13A, etching is performed.
The film surface 12 and the upper part 33 of the side surface of the Ti^11 film 31 are exposed.

Subsequently, as shown in FIG. 3C, a U plating layer 25 is formed on all 31 of the TiAu film 31 and on the side surfaces as electrodes of all 31 of the TiAu film 31.

Finally, as shown in FIG. 3(d), after removing the unnecessary photoresist layer 13A and the TiAu film 31, the source
By forming drain electrodes 26 and 27, a semiconductor device as shown in FIG. 2 is obtained.

[Problem that the invention seeks to solve]

However, in the conventional manufacturing method of semiconductor devices, Ti
In all 31 steps of the Au film 31, ^l can be removed by ion milling, and Ti can be etched with hydrochloric acid, etc., but in the ion milling stage of ^U, the underlying Ga
There is a problem of damage to the As conductive layer due to ion bombardment, and there is also a problem that Ti cannot be completely removed in Ti etching. This is because Ti and GaAs react slightly, and the reaction layer cannot be completely absorbed by the hydrochloric acid solution.

The present invention was made in view of the above-mentioned shortcomings in conventional semiconductor device manufacturing methods, and its "first objective is to realize high-performance semiconductor devices with low gate electrode resistance and low source parasitic resistance with good reproducibility. The purpose is to provide a manufacturing method for.

Means for Solving Problem C] The method for manufacturing a semiconductor device of the present invention includes the steps of selectively ion-implanting impurities into a semi-insulating substrate to form a first conductivity type impurity layer; forming a gate electrode made of a refractory metal in a predetermined region of the second conductivity type impurity layer, and ion-implanting impurities using the gate electrode as a mask to form a first conductivity type high concentration impurity layer in the semi-insulating substrate; A step of forming a dielectric film on the entire surface and then performing heat treatment to activate the implanted ions; and a step of forming a first photoresist layer on the entire surface and then forming a first photoresist layer on the gate electrode.
Etching the resist I-layer and the dielectric film
Game 1 - exposing the tops of the second and side surfaces of the electrode; forming a metal film on the entire surface including the top surface of the gate electrode after removing the first photoresist layer; a step of forming a second photoresist layer and then etching it to expose the metal film above the gate electrode; a step of plating metal on the exposed 1 m of the metal film; - removing the metal film of the photoresist layer and the second photoresist layer.

[One Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(i) are cross-sectional views of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1(a), Si + ions 29 are introduced into a semi-insulating substrate 21 made of GaAs doped with chromium (Cr) at an acceleration voltage of 30 keV for 3×1011012
Only C1 is selectively ion-implanted using the photoresist mask 10 to form an n-type layer 22.

Next, as shown in FIG. 1(b), a high melting point metal called Wdi3 is deposited on the entire surface to a thickness of about 5,000 mm, and then selectively processed using photolithography technology to form the gate electrode 24. shall be.

Next, as shown in FIG. 1(c), two Si+ ions are implanted again using the gate electrode 24 as a mask.
N-type layers 23 are provided on both sides of the gate electrode 24.

Next, as shown in FIG. 1(d), a 5i02 film 1 is applied to the entire surface.
1 to a thickness of about 2,000 layers, the entire wafer is annealed at 800° C. for 510 minutes in a hydrogen (+12) atmosphere to activate the implanted ions.

Next, as shown in FIG. 1(e), a first photoresist layer 12 is coated on the entire surface and etched, and the upper and side surfaces of the photoresist layer 12 and the gate electrode 24 are etched.
2 film 11 is removed and the upper surface 32 and 1j of the gate electrode 2/1 are removed.
The upper part 33 of the jl1 surface is exposed.

Next, as shown in FIG. 1(f), a first photoresist is sequentially deposited to a thickness of 500 and 1000 to form a TiAu film 31.

Next, as shown in Figure 1 (g), the second ho)
After applying KJ13 to the resist (resist), a portion of the head and side portions of the TiAu film 13 are exposed by etching.

Next, as shown in FIG. 1(h), the exposed TiA+
+ Human U plating 25 is performed on the + film 31, and the second photoresist layer 13 and T i A u film 3 that are no longer needed are further removed.
By removing 1, a T-shaped gate electrode with low resistance is obtained.

Next, as shown in FIG. 1(i), by forming source and drain electrodes 26 and 27 on the n+ type layer 23, the basic structure of a GaAs MESFET can be realized.

Needless to say, the source resistance and train resistance are sufficiently reduced due to the presence of the n+ type layer 23.

According to this embodiment, as shown in FIG. 1(g), since the Ti^11 film 31 serving as the power supply electrode for plating is formed on the SiO□ film 11, the TiAu film 3
1. Sufficient top-soching treatment can be performed without affecting the entire 31As conductive layer. Also, even if there is etching residue on all 31 of the TiAu films, S! It can be completely removed by removing 02WA.

In the above embodiment, the case where ^U was used as the metal plating was explained, but other metals such as Ni may be used.

〔Effect of the invention〕

As explained above, the present invention forms a metal film as a power supply electrode for applying metal plating on the upper surface of the gate electrode through a dielectric film, so that removal of the metal film damages the underlying conductive layer. Since this process can be carried out completely without imparting any lag, it is possible to obtain a method for manufacturing a semiconductor device with low gate electrode resistance and low parasitic source resistance, and high performance.

Figures 1 (a) to (i) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, and Figure 2 is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention. 3(a) to 3(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the conventional manufacturing method of a semiconductor device. .

DESCRIPTION OF SYMBOLS 10... Photoresist mask, 11... SiO□ film, 12... First e)~resist layer, 13... Second e) resist [~ layer, 1.3A... Photoresist layer ,
21... Semi-insulating substrate, 22... N-type layer, 23...
・n+ type layer, 24...gate electrode, 25...^U plating layer, 26...source electrode, 27...co-rain electrode, 31...T i Au film, 32... top surface , 33
...Top of the side.

,・　−゛

Claims (1)

[Claims] a step of selectively ion-implanting impurities into a semi-insulating substrate to form a first conductivity type impurity layer; and a step of forming a gate electrode made of a refractory metal in a predetermined region on the first conductivity type impurity layer. , implanting impurity ions using the gate electrode as a mask to form a first conductivity type high concentration impurity layer in the semi-insulating substrate; and after forming a dielectric film on the entire surface, heat treatment is performed to activate the implanted ions. forming a first photoresist layer over the entire surface, and then etching the first photoresist layer on the gate electrode and the dielectric film to expose the upper surface and side surfaces of the gate electrode; forming a metal film on the entire surface including the upper surface of the gate electrode after removing the first photoresist layer;
forming a second photoresist layer on the entire surface and then etching it to expose the metal film above the gate electrode; plating the exposed surface of the metal film with metal; and forming the second photoresist layer and the second photoresist layer. 2. A method for manufacturing a semiconductor device, comprising the step of removing the metal film under the photoresist layer.