JPS6037169A - Manufacture of mosfet - Google Patents
Manufacture of mosfetInfo
- Publication number
- JPS6037169A JPS6037169A JP14620783A JP14620783A JPS6037169A JP S6037169 A JPS6037169 A JP S6037169A JP 14620783 A JP14620783 A JP 14620783A JP 14620783 A JP14620783 A JP 14620783A JP S6037169 A JPS6037169 A JP S6037169A
- Authority
- JP
- Japan
- Prior art keywords
- source
- substrate
- ions
- drain regions
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 238000002844 melting Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 7
- 230000008018 melting Effects 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 5
- 238000010438 heat treatment Methods 0.000 claims abstract description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims 1
- 239000011229 interlayer Substances 0.000 abstract description 2
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 229910021645 metal ion Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 230000010354 integration Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
イ)産業上の利用分野
本発明は半導体基板上に設けるMOSFETの製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION A) Industrial Application Field The present invention relates to a method for manufacturing a MOSFET provided on a semiconductor substrate.
口)従来技術
近年、半導体基板に形成するMOSFETの微細化、工
程の簡略化のために、イオン打ち込みでゲート電極に対
し自己整合的にソース、ドレイ/領域を形成し、このソ
ース、ドレイン領域からA/を用いて直接ソース、ドレ
イン電極を取シ出す方法が採用されている。(2) Prior art In recent years, in order to miniaturize MOSFETs formed on semiconductor substrates and simplify the process, a source and drain/region are formed in a self-aligned manner with respect to the gate electrode by ion implantation, and from this source and drain region. A method is adopted in which the source and drain electrodes are directly extracted using A/.
ところで、上記方法ではAlのソース、ドレイン電極と
ソース、ドレイン領域とのコンタクトをオーミックにす
るため、ソース、ドレイン領域のシート抵抗の低下を図
らなければならず、現在ではこのソース、ドレイン領域
の不純物濃度を高くすることによルこれを図りでいた。By the way, in the above method, in order to make the contact between the Al source and drain electrodes and the source and drain regions ohmic, it is necessary to reduce the sheet resistance of the source and drain regions. This was achieved by increasing the concentration.
然し乍ら、上述のようにソース、ドレイン領域の不純物
濃度を高くすると、イオン注入後の活性化を行うための
熱処理時にソース、ドレイン領域が深く形成される。例
えば、N型半導体基板にボロンBを注入してP型のソー
ス、ドレイン領域を形成する場合、実用に供し得るオー
ミックコンタクトを採るにはソース、ドレイン領域の深
さは0.5戸以上になってしまう。このため、半導体基
板上に形成するMOSFETの微細化が図れず、ひいて
岐半導体装置の高集積化を阻害するものであった。However, when the impurity concentration of the source and drain regions is increased as described above, the source and drain regions are formed deeply during heat treatment for activation after ion implantation. For example, when boron B is implanted into an N-type semiconductor substrate to form P-type source and drain regions, the depth of the source and drain regions must be 0.5 mm or more in order to form a practical ohmic contact. I end up. For this reason, miniaturization of MOSFETs formed on a semiconductor substrate cannot be achieved, and this has hindered the high integration of branched semiconductor devices.
ハ)発明の目的
本発明はこのような点に鑑みて為されたものであって、
基板上に形成されるMOSFETの微細化、並びにMO
SFETを形成して成る半導体装置の小型集積化を図る
ことを目的とする。c) Purpose of the invention The present invention has been made in view of the above points, and
Miniaturization of MOSFETs formed on substrates and MOSFETs
The purpose of this invention is to achieve miniaturization and integration of a semiconductor device formed by forming an SFET.
二)発明の構凧
本発明はゲート電極をマスクとして基板表面部に不純物
及び高融点金属を連続的にイオン注入した後、熱処理を
して、ソース、ドレイン領域を形成すると同時に、この
ソース、ドレイン領域内に高融点金属シリナイドを形成
する構成を採っている。2) Structure of the kite of the invention In the present invention, impurities and refractory metals are continuously ion-implanted into the surface of the substrate using the gate electrode as a mask, and then heat-treated to form source and drain regions. A structure is adopted in which high melting point metal silinide is formed within the region.
ホ)実施例
第1図乃至第8図は本発明MO8FETの製造方法を工
程順に示す断面図であって、これ等の図を用いて本発明
を詳述する。まず、−導電型例えばN凰半導体基板(1
)上にゲート酸化膜(2)、多結晶シリコン層(3)、
5102膜(夷、を夫々400λ、5sooi、1oo
oAの膜厚で順次積層形成すゲート電極形状のレジスト
(5)を設け(第2図)、とのレジスト(5)をマスク
として弗酸と弗化アンモニウムの混合溶液を用いたウェ
ットエツチングによシ、上記5i02膜(4)及び多結
晶シリコン層(3)をエツチングし、ゲート電極(6)
を形成した後、レジスト(5ンを除去する(第6図)。E) Embodiment FIGS. 1 to 8 are cross-sectional views showing the manufacturing method of the MO8FET of the present invention in order of steps, and the present invention will be explained in detail using these figures. First, -conductivity type, for example, an N-type semiconductor substrate (1
) on which a gate oxide film (2), a polycrystalline silicon layer (3),
5102 membranes (400λ, 5sooi, 1oo respectively)
A resist (5) in the shape of a gate electrode is formed in sequence with a film thickness of 0A (Fig. 2), and wet etching is performed using a mixed solution of hydrofluoric acid and ammonium fluoride using the resist (5) as a mask. Next, the 5i02 film (4) and the polycrystalline silicon layer (3) are etched, and the gate electrode (6) is etched.
After forming the resist, the resist (5 mm) is removed (FIG. 6).
尚、ここで、ゲート電極(6)側面部には熱酸化等によ
・りて5i02膜(7)を設けてゲート電極(6)を保
護しておく。続いて、上記5i02膜(4)及びゲート
電極〔6)をマスクとして25Kavのエネルギーで1
x1o/。Here, a 5i02 film (7) is provided on the side surface of the gate electrode (6) by thermal oxidation or the like to protect the gate electrode (6). Next, using the 5i02 film (4) and gate electrode [6] as a mask, 1
x1o/.
程度ボロンBをイオン注入しく第4図)、さらに高融点
金属、例えばモリブデンMOを150KeVのエネルギ
ーで2X1015〜1x1o /aAイオン注入する(
第5図)。これにより、B及びMOが基板(1)内の略
同−領琥に注入される。次に、基板(1)全体を低温(
6oo〜7oo℃)で30分間熱処理を行い、接合の深
さが0.3〜0.4戸の浅いP型のソース、ドレイン領
域(8)(9)を形成する(第6図)。同時に、このソ
ース、ドレイン領域(8)(9J内では注入したMoと
基板(1)を構成するStが合金化してMOシリサイド
が形成され、このソース、ドレイン領域(8)(9Jの
シート抵抗は非常に低くなる。その後、基板全面にPS
G等から成る層間絶縁膜間を設け、ソース、ドレイン領
域(8)(9)上のゲート酸化膜(2J1層間絶縁膜叫
適所にソース、ドレイン領域(8)(9Jを露出するコ
ンタクトホールa凹aを開設する(第7図)。最後に、
これらのコンタクトホールαIJttaを介してソース
、ドレイン領域(8)(9)に接するソース、ドレイン
電極α3(I4をhpで形成してMOSFETを完成す
る(第8図)。このとき、上述したようにソース、ドレ
イン領域(8)(93はモリブデンシリサイドに依って
低抵抗化されているので、ソース、ドレイン電極13(
14)とソース、ドレイン領域(8)、(9)と祉良好
なオーミックコンタクトを呈する事となる。Boron B is ion-implanted (Fig. 4), and high-melting point metal such as molybdenum MO is ion-implanted at an energy of 150 KeV at 2×1015 to 1×1o/aA (Fig. 4).
Figure 5). As a result, B and MO are injected into approximately the same area within the substrate (1). Next, the entire substrate (1) is heated at a low temperature (
A heat treatment is performed for 30 minutes at a temperature of 60° to 70° C. to form shallow P-type source and drain regions (8) and (9) with a junction depth of 0.3 to 0.4° (FIG. 6). At the same time, in this source and drain region (8) (9J), the implanted Mo and St constituting the substrate (1) are alloyed to form MO silicide, and the sheet resistance of this source and drain region (8) (9J is It becomes very low.After that, PS is applied all over the board.
A contact hole a exposing the source and drain regions (8) (9J) is formed in an appropriate place with a gate oxide film (2J1 interlayer insulating film) on the source and drain regions (8) (9). Open a (Figure 7).Finally,
The source and drain electrodes α3 (I4) in contact with the source and drain regions (8) and (9) are formed in hp through these contact holes αIJtta to complete the MOSFET (Fig. 8).At this time, as described above, The source and drain regions (8) (93 have a low resistance due to molybdenum silicide, so the source and drain electrodes 13 (
14) and the source and drain regions (8) and (9), with good ohmic contact.
へ)発明の効果
以上述べた如く本発明MO8FETの製造方法は、ゲー
ト電極をマスクとして基板表面部に不純物及び高融点金
属を連続的にイオン注入した後、熱処理をしているので
、形成されたソース、ドレイン領域内にはシリサイドが
含有され良状態にな夛、接合を浅く形成してもソース、
ドレイン領域のシート抵抗を低く抑えて、ソース、ドレ
イン電極とオーミックなコンタクトが採れる。従って、
半導体基板上に形成するMOSFETの微細化が可能と
なル、ひいてはMOSFETを用いた半導体装置の高集
積化が図れる。f) Effects of the Invention As described above, the method for manufacturing the MO8FET of the present invention involves sequentially ion-implanting impurities and high-melting point metal into the surface of the substrate using the gate electrode as a mask, and then heat-treating it. The source and drain regions contain silicide and are in good condition, so even if the junction is formed shallowly, the source and drain regions
By keeping the sheet resistance of the drain region low, ohmic contact can be made with the source and drain electrodes. Therefore,
It is possible to miniaturize MOSFETs formed on a semiconductor substrate, and as a result, it is possible to achieve high integration of semiconductor devices using MOSFETs.
第1図乃至第8図は本発明MO8FETの製造方法を工
程順に示した断面図である。
(1)・・・半導体基板、(6ト・・ゲート電極、(8
1(9J・・・ソース、ドレイン領域、 113Q4)
・・・ソース、ドレイン電極。1 to 8 are cross-sectional views showing the method of manufacturing MO8FET of the present invention in order of steps. (1)...Semiconductor substrate, (6)...Gate electrode, (8)
1 (9J...source, drain region, 113Q4)
...Source and drain electrodes.
Claims (1)
板上にゲート酸化膜を設け、このゲート酸化膜上にゲー
ト電極を形成した後、このゲート電極をマスクとして基
板表面部に不純物及び高融点金属を連続的にイオン注入
し、続いて熱処理をすることによシ上記半導体基板内に
ソース、ドレイン領域を設けると同時にこのソース、ド
レイン領域中に高融点金属シリサイドを形成し、上記ソ
ース、ドレイン領域に接するソース、ドレイン電極を設
けて成るMOSFETの製造方法。1) When forming a MOSFET on a semiconductor substrate, a gate oxide film is provided on the substrate, a gate electrode is formed on this gate oxide film, and then impurities and high melting point metals are applied to the surface of the substrate using the gate electrode as a mask. By continuous ion implantation and subsequent heat treatment, source and drain regions are provided in the semiconductor substrate, and at the same time, high melting point metal silicide is formed in the source and drain regions. A method for manufacturing a MOSFET in which source and drain electrodes are provided in contact with each other.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14620783A JPS6037169A (en) | 1983-08-09 | 1983-08-09 | Manufacture of mosfet |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14620783A JPS6037169A (en) | 1983-08-09 | 1983-08-09 | Manufacture of mosfet |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6037169A true JPS6037169A (en) | 1985-02-26 |
Family
ID=15402536
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14620783A Pending JPS6037169A (en) | 1983-08-09 | 1983-08-09 | Manufacture of mosfet |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6037169A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6486560A (en) * | 1987-09-29 | 1989-03-31 | Nippon Telegraph & Telephone | Manufacture of semiconductor device |
-
1983
- 1983-08-09 JP JP14620783A patent/JPS6037169A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6486560A (en) * | 1987-09-29 | 1989-03-31 | Nippon Telegraph & Telephone | Manufacture of semiconductor device |
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