JPH10125623A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH10125623A JPH10125623A JP29751696A JP29751696A JPH10125623A JP H10125623 A JPH10125623 A JP H10125623A JP 29751696 A JP29751696 A JP 29751696A JP 29751696 A JP29751696 A JP 29751696A JP H10125623 A JPH10125623 A JP H10125623A
- Authority
- JP
- Japan
- Prior art keywords
- film
- titanium
- forming
- semiconductor device
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims description 49
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims abstract description 35
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 31
- 239000010936 titanium Substances 0.000 claims abstract description 31
- 238000010438 heat treatment Methods 0.000 claims abstract description 28
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 23
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- 150000004767 nitrides Chemical class 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 7
- 229910021332 silicide Inorganic materials 0.000 abstract description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 4
- 230000007704 transition Effects 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置の製造方
法に関わり、特に、ソース／ドレイン、ゲート電極上に
チタンシリサイド膜が形成されてなる半導体装置の製造
方法に関わる。The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a titanium silicide film formed on a source / drain and a gate electrode.
【０００２】[0002]
【従来の技術】ＭＯＳ型半導体集積回路装置では、ソー
ス／ドレイン領域およびゲート電極と配線間の高抵抗化
を防ぐため、ソース／ドレイン領域およびゲート電極上
に、選択的に低抵抗のシリサイド電極を形成する、いわ
ゆるサリサイド法が用いられるようとしている。シリサ
イド形成に用いられる金属として、従来よりチタンが一
般的である。2. Description of the Related Art In a MOS semiconductor integrated circuit device, a low-resistance silicide electrode is selectively formed on a source / drain region and a gate electrode in order to prevent an increase in resistance between a source / drain region and a gate electrode. The so-called salicide method for forming is to be used. As a metal used for silicide formation, titanium has been generally used.
【０００３】以下、図３を用いて、チタンを用いた従来
のチタンサリサイド法について説明する。図３（ａ）に
示すように、シリコン基板２１上に素子分離のためのシ
リコン酸化膜２２を形成し、素子形成領域２３上にゲー
ト酸化膜２４１を形成し、その上に多結晶シリコンのゲ
ート２４、ゲート酸化膜２４１およびシリコン酸化膜の
サイドウォール２５を形成する。然る後、前記シリコン
基板２１上の全面にスパッタ法によりチタン膜２６を形
成する。A conventional titanium salicide method using titanium will be described below with reference to FIG. As shown in FIG. 3A, a silicon oxide film 22 for element isolation is formed on a silicon substrate 21, a gate oxide film 241 is formed on an element formation region 23, and a polysilicon gate is formed thereon. 24, a gate oxide film 241 and a sidewall 25 of a silicon oxide film are formed. Thereafter, a titanium film 26 is formed on the entire surface of the silicon substrate 21 by a sputtering method.
【０００４】次いで、図３（ｂ）に示すように、例えば
８５０℃・１０秒の急速加熱を行い、ソース／ドレイン
領域２８およびゲート２４上のみチタンシリサイド２０
を形成する。[0004] Then, as shown in FIG. 3 (b), rapid heating is performed, for example, at 850 ° C. for 10 seconds to form titanium silicide 20 only on the source / drain region 28 and the gate 24.
To form
【０００５】次に、図３（ｃ）に示すように、例えばＮ
Ｈ4 ＯＨ＋Ｈ2 Ｏ2 薬液によるウェットエッチングを行
い、急速加熱後も未反応であったチタン膜２６を除去し
てソース／ドレイン領域２８上およびゲート２４上にチ
タンシリサイド電極２０を形成する。[0005] Next, as shown in FIG.
Wet etching with H 4 OH + H 2 O 2 chemical solution is performed to remove the titanium film 26 that has not been reacted even after rapid heating, thereby forming a titanium silicide electrode 20 on the source / drain region 28 and the gate 24.
【０００６】[0006]
【発明が解決しようとする課題】前述したチタンサリサ
イド法には、サリサイド幅が寸法が１．０μｍ以下の領
域では、急速加熱後に形成されるチタンシリサイドの抵
抗が高くなるという問題があった。The above-mentioned titanium salicide method has a problem that the resistance of titanium silicide formed after rapid heating becomes high in the region where the salicide width is 1.0 μm or less.
【０００７】これは、チタンシリサイドには低抵抗の構
造と高抵抗の構造の２種類の構造があり、熱処理時間に
比例して低抵抗構造への遷移が進むが、寸法の微細化に
伴い、低抵抗構造への遷移が発生しにくくなるためであ
る。この問題は、急速加熱時に、チタン膜に圧縮応力を
加えれば改善が可能であることが既に分かっている。This is because titanium silicide has two types of structures, a low resistance structure and a high resistance structure. The transition to the low resistance structure progresses in proportion to the heat treatment time. This is because the transition to the low-resistance structure hardly occurs. It has already been found that this problem can be improved by applying compressive stress to the titanium film during rapid heating.
【０００８】本発明は前述の問題点にかんがみ、チタン
シリサイド形成時にチタン膜に圧縮応力をかけること
で、チタンシリサイド電極を低抵抗化することを目的と
する。In view of the above problems, an object of the present invention is to reduce the resistance of a titanium silicide electrode by applying a compressive stress to a titanium film when forming titanium silicide.
【０００９】[0009]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体基板上に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成されたゲート電極と、前記ゲ
ート電極の側面に形成された側壁酸化膜とを備える半導
体装置の製造方法において、前記半導体基板上にチタン
膜を形成する第一の工程と、前記チタン膜上に窒化膜を
形成する第二の工程と、前記第二の工程後、前記半導体
基板に急速加熱処理を施し、前記ゲート電極上及び前記
ゲート電極の両脇近傍の前記半導体基板上にチタンシリ
サイド膜を形成する第三の工程と、前記ゲート電極の両
脇近傍に形成された前記チタンシリサイド膜の下の半導
体基板に拡散層を形成する第四の工程とを有することを
特徴としている。According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a gate insulating film formed on a semiconductor substrate;
In a method of manufacturing a semiconductor device including a gate electrode formed on the gate insulating film and a sidewall oxide film formed on a side surface of the gate electrode, a first step of forming a titanium film on the semiconductor substrate A second step of forming a nitride film on the titanium film, and after the second step, performing a rapid heating process on the semiconductor substrate to form a semiconductor substrate on the gate electrode and in the vicinity of both sides of the gate electrode. A third step of forming a titanium silicide film thereon; and a fourth step of forming a diffusion layer in a semiconductor substrate below the titanium silicide film formed near both sides of the gate electrode. And
【００１０】また、本発明の他の特徴とするところは、
半導体基板上に形成されたゲート絶縁膜と、前記ゲート
絶縁膜上に形成されたゲート電極と、前記ゲート電極側
面に形成された側壁酸化膜と、拡散層とを備える半導体
装置の製造方法において、前記半導体基板上にチタン膜
を形成する第一の工程と、前記チタン膜上に窒化膜を形
成する第二の工程と、前記第二の工程後、前記半導体基
板に急速加熱処理を施し、前記ゲート電極上及び前記拡
散層上にチタンシリサイド膜を形成する第三の工程とを
有することを特徴としている。Another feature of the present invention is that
A method of manufacturing a semiconductor device comprising: a gate insulating film formed on a semiconductor substrate; a gate electrode formed on the gate insulating film; a sidewall oxide film formed on a side surface of the gate electrode; and a diffusion layer. A first step of forming a titanium film on the semiconductor substrate, a second step of forming a nitride film on the titanium film, and after the second step, subjected to a rapid heating treatment on the semiconductor substrate, And forming a titanium silicide film on the gate electrode and the diffusion layer.
【００１１】また、本発明のその他の特徴とするところ
は、請求項１または２の何れか１項に記載の半導体装置
の製造方法において、前記第三の工程において、前記半
導体基板に、昇温速度１００〜６００℃の急速加熱処理
を施すことを特徴としている。According to another feature of the present invention, in the method of manufacturing a semiconductor device according to any one of claims 1 and 2, in the third step, the semiconductor substrate is heated. It is characterized by performing a rapid heating process at a rate of 100 to 600 ° C.
【００１２】また、本発明のその他の特徴とするところ
は、請求項１または２の何れか１項に記載の半導体装置
の製造方法において、前記第三の工程において、前記半
導体基板に、６５０〜９００℃の範囲のうちのいずれか
の温度で、急速加熱処理を施すことを特徴としている。According to another feature of the present invention, in the method of manufacturing a semiconductor device according to any one of claims 1 and 2, in the third step, the semiconductor substrate is provided with 650-500 nm. The rapid heating treatment is performed at any temperature within the range of 900 ° C.
【００１３】また、本発明のその他の特徴とするところ
は、請求項４に記載の半導体装置の製造方法において、
前記第三の工程において、前記半導体基板に、８５０
℃、１０秒の急速加熱処理を施すことを特徴としてい
る。Another feature of the present invention is that in the method of manufacturing a semiconductor device according to claim 4,
In the third step, 850 is added to the semiconductor substrate.
It is characterized by performing a rapid heating treatment at 10 ° C. for 10 seconds.
【００１４】また、本発明のその他の特徴とするところ
は、請求項５に記載の半導体装置の製造方法において、
前記第三の工程において、前記半導体基板に、８５０
℃、１０秒の急速加熱処理を施した後、６５０℃、３０
分の加熱を行うことを特徴としている。Another feature of the present invention is that in the method of manufacturing a semiconductor device according to claim 5,
In the third step, 850 is added to the semiconductor substrate.
650 ° C, 30 seconds
It is characterized by performing heating for minutes.
【００１５】[0015]
【発明の実施の形態】以下、本発明の実施の形態につい
て図１及び２を参照して説明する。図１及び図２は、本
発明の実施の形態を表す半導体装置の製造工程順断面図
である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 and 2 are cross-sectional views illustrating a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps.
【００１６】まず、図１（ａ）に示すように、シリコン
基板１１に素子分離用の熱酸化膜１２を形成し、素子形
成領域１３上にゲート酸化膜１４１を形成する。次に、
前記酸化膜１４１上に多結晶シリコンのゲート１４を形
成する。その後、図１（ｂ）に示すように、ゲート１４
の側面に公知の方法でサイドウォール酸化膜１５を形成
する。First, as shown in FIG. 1A, a thermal oxide film 12 for element isolation is formed on a silicon substrate 11, and a gate oxide film 141 is formed on an element formation region 13. next,
A polycrystalline silicon gate 14 is formed on the oxide film 141. Thereafter, as shown in FIG.
A side wall oxide film 15 is formed on the side surface by a known method.
【００１７】次に、図１（ｃ）に示すように、公知のス
パッタ法によりチタン膜１６をシリコン基板１１の全面
に、膜厚３０ｎｍで形成する。次いで、図１（ｄ）に示
すように、公知の化学的気相成長法でシリコン窒化膜１
７をシリコン基板１１の全面に膜厚４０ｎｍで形成す
る。Next, as shown in FIG. 1C, a titanium film 16 is formed with a thickness of 30 nm on the entire surface of the silicon substrate 11 by a known sputtering method. Next, as shown in FIG. 1D, the silicon nitride film 1 is formed by a known chemical vapor deposition method.
7 is formed on the entire surface of the silicon substrate 11 with a thickness of 40 nm.
【００１８】その後、図２（ａ）に示すように、昇温速
度１００〜６００℃で、８５０℃・１０秒の急速加熱を
行い、ゲート１４上およびソースドレイン領域１８上、
すなわち、チタンとシリコンとが直に接触する部分で選
択的にチタンシリサイド膜１０を形成する。Thereafter, as shown in FIG. 2A, rapid heating is performed at 850 ° C. for 10 seconds at a temperature increasing rate of 100 to 600 ° C., so that the gate 14 and the source / drain region 18 are heated.
That is, the titanium silicide film 10 is selectively formed at a portion where titanium and silicon are in direct contact.
【００１９】このとき、素子分離酸化膜１２およびサイ
ドウォール酸化膜１５上においてはチタンとシリコン酸
化膜とが接触しており、チタンは未反応である。この図
２（ａ）における急速加熱により、シリコン窒化膜１７
からチタン膜１６に圧縮応力がかかるので、チタンシリ
サイド膜１０の低抵抗構造への遷移が促進される。At this time, titanium and the silicon oxide film are in contact with each other on the element isolation oxide film 12 and the side wall oxide film 15, and titanium is not reacted. By the rapid heating in FIG.
Since a compressive stress is applied to the titanium film 16, the transition of the titanium silicide film 10 to a low resistance structure is promoted.
【００２０】次に、図２（ｂ）に示すように、シリコン
窒化膜１７を除去した後、図２（ｃ）に示すように、チ
タン膜１６のみをウェットエッチングにより除去するこ
とにより、チタンシリサイド膜（電極）１０を形成す
る。次に、図２（ｃ）に示すように、チタンサリサイド
膜（電極）１０の下に、拡散層１０１をイオン注入によ
り形成する。Next, as shown in FIG. 2B, after the silicon nitride film 17 is removed, only the titanium film 16 is removed by wet etching as shown in FIG. A film (electrode) 10 is formed. Next, as shown in FIG. 2C, a diffusion layer 101 is formed below the titanium salicide film (electrode) 10 by ion implantation.
【００２１】次に、図２（ｄ）に示すように、公知のイ
オン注入法により拡散領域１０１を形成する。なお、前
記の例では急速加熱を８５０℃・１０秒としたが、温度
条件は６５０℃〜９００℃の範囲で任意に選択すること
が可能である。また、熱処理時間も数秒から３０分程度
まで選択することが出来る。Next, as shown in FIG. 2D, a diffusion region 101 is formed by a known ion implantation method. In the above example, the rapid heating was performed at 850 ° C. for 10 seconds, but the temperature condition can be arbitrarily selected in the range of 650 ° C. to 900 ° C. Further, the heat treatment time can be selected from several seconds to about 30 minutes.
【００２２】また、急速加熱を１段階で行うのではな
く、６５０℃・３０分の加熱を行い、引き続き８５０℃
・１０秒の加熱を行う、といった２段階の熱処理に変更
することも可能である。Further, instead of performing rapid heating in one stage, heating is performed at 650 ° C. for 30 minutes, and then 850 ° C.
-It is also possible to change to a two-stage heat treatment in which heating is performed for 10 seconds.
【００２３】また、前記の例ではチタンシリサイドを形
成する以前にソース／ドレイン領域に拡散層を形成する
ための工程を入れていないが、あらかじめソース／ドレ
イン領域にイオン注入を行い拡散層を形成した後、チタ
ンシリサイドを形成することも可能である。また、ゲー
ト側面のサイドウォールを酸化膜により形成している
が、シリコン窒化膜などを用いることも可能である。In the above example, a step for forming a diffusion layer in the source / drain region was not performed before forming the titanium silicide. However, a diffusion layer was formed by implanting ions into the source / drain region in advance. Later, titanium silicide can be formed. Further, although the sidewall on the gate side surface is formed of an oxide film, a silicon nitride film or the like may be used.
【００２４】[0024]
【発明の効果】本発明は前述したように、本発明によれ
ば、シリサイド電極を形成する時に、チタン膜に圧縮応
力をかけるので、素子の微細化が進行して、サリサイド
電極寸法が狭い場合でも、低抵抗のソース／ドレイン、
ゲート電極を形成することが可能になる。As described above, according to the present invention, when a silicide electrode is formed, a compressive stress is applied to a titanium film. But low resistance source / drain,
A gate electrode can be formed.
【図１】本発明の実施の形態における半導体装置の工程
順断面図である。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention in the order of steps.
【図２】本発明の実施の形態における半導体装置の工程
順断面図である。FIG. 2 is a sectional view of the semiconductor device according to the embodiment of the present invention in the order of steps.
【図３】従来のチタンサリサイド法における半導体装置
の工程順断面図である。FIG. 3 is a sectional view of a semiconductor device in a conventional titanium salicide method in the order of steps.
１０ チタンシリサイド膜 １１ シリコン基板 １４１ ゲート酸化膜 １４ ゲート １５ ゲート側壁の絶縁性サイドウォール １６ チタン膜 １７ シリコン窒化膜 １８ ソース／ドレイン領域 DESCRIPTION OF SYMBOLS 10 Titanium silicide film 11 Silicon substrate 141 Gate oxide film 14 Gate 15 Insulating sidewall of gate side wall 16 Titanium film 17 Silicon nitride film 18 Source / drain region
Claims (6)
と、前記ゲート絶縁膜上に形成されたゲート電極と、前
記ゲート電極の側面に形成された側壁酸化膜とを備える
半導体装置の製造方法において、 前記半導体基板上にチタン膜を形成する第一の工程と、 前記チタン膜上に窒化膜を形成する第二の工程と、 前記第二の工程後、前記半導体基板に急速加熱処理を施
し、前記ゲート電極上及び前記ゲート電極の両脇近傍の
前記半導体基板上にチタンシリサイド膜を形成する第三
の工程と、 前記ゲート電極の両脇近傍に形成された前記チタンシリ
サイド膜の下の半導体基板に拡散層を形成する第四の工
程とを有することを特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device comprising: a gate insulating film formed on a semiconductor substrate; a gate electrode formed on the gate insulating film; and a sidewall oxide film formed on a side surface of the gate electrode. A first step of forming a titanium film on the semiconductor substrate; a second step of forming a nitride film on the titanium film; and after the second step, performing a rapid heating process on the semiconductor substrate. Forming a titanium silicide film on the gate electrode and on the semiconductor substrate near both sides of the gate electrode; and forming a semiconductor under the titanium silicide film formed on both sides of the gate electrode. And a fourth step of forming a diffusion layer on the substrate.
と、前記ゲート絶縁膜上に形成されたゲート電極と、前
記ゲート電極側面に形成された側壁酸化膜と、拡散層と
を備える半導体装置の製造方法において、 前記半導体基板上にチタン膜を形成する第一の工程と、 前記チタン膜上に窒化膜を形成する第二の工程と、 前記第二の工程後、前記半導体基板に急速加熱処理を施
し、前記ゲート電極上及び前記拡散層上にチタンシリサ
イド膜を形成する第三の工程とを有することを特徴とす
る半導体装置の製造方法。2. A semiconductor device comprising: a gate insulating film formed on a semiconductor substrate; a gate electrode formed on the gate insulating film; a sidewall oxide film formed on a side surface of the gate electrode; and a diffusion layer. In the manufacturing method, a first step of forming a titanium film on the semiconductor substrate, a second step of forming a nitride film on the titanium film, and after the second step, rapid heating of the semiconductor substrate Performing a treatment to form a titanium silicide film on the gate electrode and the diffusion layer.
半導体装置の製造方法において、 前記第三の工程において、前記半導体基板に、昇温速度
１００〜６００℃の急速加熱処理を施すことを特徴とす
る半導体装置の製造方法。3. The method for manufacturing a semiconductor device according to claim 1, wherein in the third step, the semiconductor substrate is subjected to a rapid heating process at a temperature increasing rate of 100 to 600 ° C. A method for manufacturing a semiconductor device, comprising:
半導体装置の製造方法において、 前記第三の工程において、前記半導体基板に、６５０〜
９００℃の範囲のうちのいずれかの温度で、急速加熱処
理を施すことを特徴とする半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein in the third step, 650 to 650 are provided on the semiconductor substrate.
A method for manufacturing a semiconductor device, wherein a rapid heating process is performed at any temperature within a range of 900 ° C.
において、 前記第三の工程において、前記半導体基板に、８５０
℃、１０秒の急速加熱処理を施すことを特徴とする半導
体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 4, wherein in the third step, 850 is added to the semiconductor substrate.
A method for manufacturing a semiconductor device, comprising performing a rapid heating process at 10 ° C. for 10 seconds.
において、 前記第三の工程において、前記半導体基板に、８５０
℃、１０秒の急速加熱処理を施した後、６５０℃、３０
分の加熱処理を行うことを特徴とする半導体装置の製造
方法。6. The method of manufacturing a semiconductor device according to claim 5, wherein in the third step, 850 is added to the semiconductor substrate.
650 ° C, 30 seconds
A method for manufacturing a semiconductor device, comprising performing a heat treatment for one minute.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29751696A JPH10125623A (en) | 1996-10-18 | 1996-10-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29751696A JPH10125623A (en) | 1996-10-18 | 1996-10-18 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10125623A true JPH10125623A (en) | 1998-05-15 |
Family
ID=17847538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29751696A Withdrawn JPH10125623A (en) | 1996-10-18 | 1996-10-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10125623A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000021121A1 (en) * | 1998-10-05 | 2000-04-13 | Seiko Epson Corporation | Semiconductor device and method for producing the same |
| US6284610B1 (en) * | 2000-09-21 | 2001-09-04 | Chartered Semiconductor Manufacturing Ltd. | Method to reduce compressive stress in the silicon substrate during silicidation |
| US6656847B1 (en) * | 1999-11-01 | 2003-12-02 | Taiwan Semiconductor Manufacturing Company | Method for etching silicon nitride selective to titanium silicide |
-
1996
- 1996-10-18 JP JP29751696A patent/JPH10125623A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000021121A1 (en) * | 1998-10-05 | 2000-04-13 | Seiko Epson Corporation | Semiconductor device and method for producing the same |
| US6500759B1 (en) | 1998-10-05 | 2002-12-31 | Seiko Epson Corporation | Protective layer having compression stress on titanium layer in method of making a semiconductor device |
| US6656847B1 (en) * | 1999-11-01 | 2003-12-02 | Taiwan Semiconductor Manufacturing Company | Method for etching silicon nitride selective to titanium silicide |
| US6284610B1 (en) * | 2000-09-21 | 2001-09-04 | Chartered Semiconductor Manufacturing Ltd. | Method to reduce compressive stress in the silicon substrate during silicidation |
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