JPH03288443A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To restrain short-circuiting between a gate electrode and a source/ drain caused by the lateral growth of silicide, by a method wherein, after an insulating film side wall is formed on the side surface of a gate electrode of two-layered structure composed of a polycrystalline silicon layer and an insulating film, the upper layer insulating film of the two-layered structure gate electrode is eliminated. CONSTITUTION:By patterning an SiN nitride film 22 and a polycrystalline silicon layer 15 deposited on a substrate 11, a gate electrode 14 of two-layered structure is formed on a gate oxide film 13. After a side wall 17 of an insulating film is formed on the sidewall of the gate electrode 14, the SiN nitride film 22 on a polycrystalline silicon layer 15 is eliminated by using hot phosphoric acid. Thus the insulating film side wall 17 protrudes above the gate electrode 14 composed of only the polycrystalline silicon layer 15. By depositing a Ti film on the whole surface and performing lamp annealing, the Ti film in the part in contact with the gate electrode 14 and Si on the surface of a diffusion layer 18 is turned into silicide, and TiSix layer 16a, 16b, 16c are obtained. At this time, the lateral growth of silicide is blocked by the side wall 17.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a salicide structure MOS (MOS) transistor.

(Prior art) In recent years, as silicon semiconductor devices have been miniaturized, MO
S) Gate electrode of transistor, impurity diffusion layer (source/
The drain region) is also becoming thinner and thinner. Accordingly, it becomes necessary to reduce the resistance values of the gate electrode and the diffusion layer.

Salicide technology is a technology that simultaneously reduces the resistance in these two areas.

FIG. 3 is an example of a conventional salicide structure MOS transistor described in the document ``Very LSI Technology N111O VLSI Circuit and Process, pp. 259-260''.

By pasting the TiSix layer 1 on the gate electrode 2 and the diffusion layer 3, the series resistance at this location is lowered.

FIG. 4 is a process sectional view showing a method of manufacturing the salicide structure MO3) transistor disclosed in the above-mentioned document. To explain this conventional manufacturing method, first, Fig. 4(a)
As shown in FIG.
After forming a diffusion layer 3 as a source/drain in a substrate 4 by high-concentration O ion implantation as shown in the figure, an insulating film of 5i0□ is formed on the entire surface of the substrate, and then it is etched by anisotropic etching. By etching, a sidewall 6 made of the remaining insulating film is formed on the side surface of the gate electrode 2. Next, as shown in FIG. 4(b), after forming a Ti film 7 on the entire surface by sputtering, a first lamp annealing is performed at a relatively low temperature of about 600"C or less. Then, the gate electrode 2 and T of the part in contact with 53 on the diffusion layer 3
The i film 7 is silicided, and as shown in FIG.
While forming the iSix layer 1, the Ti 117 on the SiF')all 6 (insulating film) remains in an unreacted state because the annealing temperature is low. After this, as shown in FIG. 4(d), unreacted T
I117 is selectively removed 1, and finally, a second lamp annealing is performed at a temperature of 650° C. or higher to complete silicidation and complete the 41st H(e) transistor.

In such a manufacturing method, there are certain reasons for performing two-stage annealing. This is described on page 259 of the above document. This is because silicide grows on the oxide film (sidewall 6) when the silicidation process is performed at a high temperature. In the titanium silicidation reaction in which titanium and silicon are alloyed, St acts as a moving atom because St is a reactive species. As silicon atoms diffuse through silicide formed on silicon, silicide grows laterally.

Therefore, the 17th anneal temperature is set low in order to suppress the growth of silicide in the lateral direction.

(Issue R to be solved by the invention) However, in the above two-step annealing method in which the first annealing temperature is suppressed, silicidation is difficult to occur on the diffusion layer 3 because A3 is doped at a high concentration. This is generally known. Therefore, in order to actually form silicide (TiSi2 layer) on the n4 diffusion layer 3, the 17th annealing temperature has to be raised to some extent. Therefore, even in the two-step annealing method described in the above document, Due to the growth of silicide on the sidewall 6, the gate electrode 2 and the source/drain (diffusion layer 3) are
The fear of -1 was unavoidable.

In addition, although it is not described in the above-mentioned document and was not mentioned in the explanation of the above-mentioned manufacturing method, in reality, before depositing the Ti film 7, it is necessary to wash the substrate with an aqueous solution of [(F).
The film of the sidewall 6 is reduced. Since the sidewall 6 is etched isotropically in the HP cleaning, the sidewall 6 retreats downward and laterally. As a result, the gate electrode polysilicon on the upper side wall of the gate electrode 2 is exposed, and the insulation distance between the gate electrode 2 and the source/drain (diffusion j13) is shortened. Therefore, the lateral growth of silicide becomes more severe.

The present invention has been made in view of the above points, and an object of the present invention is to provide a method of manufacturing a semiconductor device that can suppress the formation of a seat between a gate electrode and a source/drain due to the lateral growth of silicide.

(Means for Solving the Problems) The present invention provides a method for manufacturing a semiconductor device, particularly a method for manufacturing a salicide structure MO5) transistor, in which a gate electrode is formed on a silicon substrate with a two-layer structure of a polysilicon layer and an insulating film. After forming insulating film sidewalls on the sides of this two-layer gate electrode, the upper insulating film of the two-layer gate electrode is removed, and then a metal film is deposited on the entire surface and annealed to form a silicide layer. 6 (
Function) After forming an insulating film sidewall on the side surface of a gate electrode with a two-layer structure consisting of a polysilicon layer and an insulating film, when the upper insulating film of the 2N structure gate electrode is removed, the insulating film sidewall becomes, for example, As shown in FIG. 1(f), the structure is such that the gate electrode made of a polysilicon layer is warped in the E direction. According to this structure, even if lateral growth of silicide occurs when a silicide layer is selectively formed by depositing a metal film on the entire surface and then performing a uniform process, In order for the source/drain and gate electrodes to sigate due to the length, the lateral growth must overcome the upwardly protruding sidewalls, and this is difficult, so that segregation does not occur.

That is, the sidewall protruding upward serves as a protective wall against the lateral growth of silicide.

In addition, the sidewall is a gate electrode (polysilicon layer)
If the structure protrudes above the gate electrode, the gate electrode (
Exposure of the upper sidewall of the polysilicon layer (polysilicon layer) is prevented. In this case, the height of the sidewall can be adjusted by taking into account the thickness of the sidewall to be etched.The height of the sidewall protruding from the gate electrode (polysilicon layer) is determined by It can be easily controlled by making it approximately equal to the thickness of the insulating film.

(Example) An example of the present invention will be described below with reference to the drawings.
Before that, the structure of a MOS transistor manufactured according to an embodiment of the present invention will be explained with reference to FIG.

In FIG. 2, 11 is a p-type silicon substrate, on the surface of which a field oxide film 12 is selectively formed. A gate electrode 14 is formed on the surface of the substrate 11 in the element region surrounded by the field oxide film 12 with a gate oxide film 13 interposed therebetween.

This gate electrode 14 is made of polysilicon 1i15,
A TiSi layer (silicide) ij) 16a is formed on the surface. A side wall 17 of an insulating film is formed on the side wall of the gate electrode 14 by protruding above the gate electrode 14.
is formed. In addition, the substrates 11 on both sides of the gate electrode 14
A diffusion layer 18 serving as a source/drain is formed on the surface portion. The surface of this diffusion layer 18 has a TiSix layer (silicide layer) 16b16c. The entire surface of the substrate 11 having these structures is covered with an intermediate insulating film 19.

A contact hole 20 reaching the source/drain diffusion layer 18 is opened in this intermediate insulating layer 1119. Further, a wiring 21 is formed of M so as to be in contact with the source/drain diffusion layer 18 through the contact hole 20.

Such a MOS) transistor is manufactured by the manufacturing method shown in FIG. The manufacturing method (an embodiment of the present invention) will be described below.

First, as shown in FIG. 1(a), a p-type silicon substrate I
Field oxidation 1112 is selectively formed on the surface of J by a normal selective oxidation method. Next, a gate oxide film 13 is formed by thermal oxidation on the surface of the substrate 11 in the element region surrounded by this field oxidation W1112.

Thereafter, as shown in FIG. 1), a polysilicon layer 15 is first deposited on the entire surface of the substrate 11 by low-pressure CVD, and then phosphorus is diffused into the polysilicon layer 15. ! 22 is deposited by LPCVD (low pressure vapor deposition) or the like.

Then, as shown in FIG. 1(C), the SiN nitride film 22
By patterning the polysilicon layer 15 in a conventional manner, a gate Fa4 pole 14 having a 211 structure is formed on the gate oxide M1.3.

After forming the two-layer gate electrode 14 in this way,
Next, as shown in FIG. 1(d), the two-layer structure gate electrode 1
As'' is implanted into the surface of the substrate 11 on both sides of the source 4.
A diffusion layer 18 of n' is formed as a drain.

Next, PSG (phosphosilicate glass) or NSC (
Normal pressure CV of insulating films such as non-doped silicate glass
By depositing it on the entire surface of the substrate using the D method or the like and etching it using an anisotropic etching process, the pattern shown in Fig. 1 (
e) L As shown, a side mail 17 of an insulating film is formed on the side wall of the two-layer structure gate electrode 14.

Thereafter, the impurity diffusion layer 18 is activated through a heat treatment process at 900° C. for 30 minutes.

Next, as shown in FIG. 1(f), the SiN nitride film 22 on the polysilicon layer 15 is removed using hot phosphoric acid. As a result, the insulating film sidewall 17 has a structure in which the gate made of only the polysilicon layer 15 protrudes above the pole 14.

Next, after cleaning the substrate with an HF aqueous solution, the Ti film (metal film)
is deposited on the entire surface and lamp annealed in Ar at 600°C for 30 seconds. By this lamp annealing, S on the surface of the gate electrode 14 (polysilicon layer 15) and diffusion layer 18 is removed.
The Ti film in contact with I is silicided, as shown in Figure 1 (
6), Tilt, layers 16a, 16b, 16c
becomes. On the other hand, the Ti film on the insulating film of the sidewall 17 and field oxide film 12 remains unreacted. after that,
This unreacted Ti film is removed with a mixed solution of ammonia, hydrogen peroxide, and water. The state after this is shown in FIG. 1 (8).

From this point on, the process is exactly the same as the conventional general method, and as shown in FIG. After opening the contact hole 20,
The wiring 21 is formed by depositing an M film containing 1% Si and patterning the M film.

In the above embodiment, a SiN nitride film was used as the upper insulating film of the two-layer structure gate electrode, but TiN or Zr
High melting point nitrides such as N or Tic.

High melting point carbides such as ZrC can also be used. In those cases, for example, a mixed solution of sulfuric acid and hydrogen peroxide may be used to selectively remove the insulating film above the gate electrode.

Further, although a Ti film was used as the metal film for forming the silicide layer, other metal films such as ZrII, Ti film, and C.

A membrane etc. can also be used.

(Effects of the Invention) As described above in detail, according to the manufacturing method of the present invention, after forming a gate electrode with a two-layer structure and forming a sidewall on the side wall thereof, the upper layer of the two-layer structure gate electrode is By removing the insulating film, we created a structure in which the sidewalls protruded above the gate electrode consisting of only a polysilicon layer, making it difficult for the lateral growth of silicide to overcome the walls of the sidewalls during the subsequent formation of the silicide layer. The lateral growth of the silicide can prevent the gate electrode and the source/drain from coming into contact with each other.

In addition, the sidewall is a gate electrode (polysilicon layer)
If the structure protrudes above, even if the sidewall is etched in IIP cleaning before depositing the metal film for forming the silicide layer, the upper part of the sidewall of the gate electrode (polysilicon layer) can be prevented from being exposed. Therefore, it is possible to more reliably prevent the source/drain and the gate electrode from collapsing. Furthermore, the height of the sidewall protruding from the gate electrode (polysilicon layer) can be freely adjusted by adjusting the thickness of the insulating film on the polysilicon layer.

This is effective in the sense that it allows a degree of freedom to be given to the process.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view showing one embodiment of the method for manufacturing a semiconductor device of the present invention, FIG. 2 is a cross-sectional view of a MOS transistor manufactured by the above-mentioned embodiment, and FIG. FIG. 4 is a sectional view showing a conventional manufacturing method. 11... p-type silicon substrate, 14... gate electrode,
15...Polysilicon layer, 16a, 16b, 16c
...Ti5tx layer, 17... Side wall, 18
...diffusion layer. 14: Gate electrode 15: Polysilicon layer 16a, 16b, 16c: Ti5iX layer 17: Side wall 18: Diffusion layer 22: TiN nitride film An embodiment of the present invention Fig. 1 An embodiment of the present invention Fig. 1 Fig. 3

Claims (1)

[Claims] A step of forming a gate electrode with a two-layer structure of a polysilicon layer and an insulating film on a silicon substrate, and forming diffusion layers as a source and drain on the surface of the substrate on both sides; A step of forming insulating film sidewalls on the side surfaces of the layered gate electrode, and then removing the upper insulating film of the two-layered gate electrode to form the sidewalls on the gate electrode, which is left with only a polysilicon layer. After forming a protruding structure, a metal film is formed on the entire surface and annealed, thereby selectively forming a silicide layer on the gate electrode made of only the polysilicon layer and on the diffusion layer. Method of manufacturing the device.