JPH05190566A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent both a source and a drain region from increasing in resistance by a method wherein impurity ions are implanted into both a source forming region and a drain forming region before and after the sidewall of a gate electrode is formed so as to form an impurity ion-diffused layer which is deep extending under the sidewall of a gate. CONSTITUTION:A gate oxide film 7 and a gate electrode 8 are formed on the surface of a semiconductor substrate 1. Then, impurity ions are implanted into a source forming region and a drain forming region 10 after the gate electrode 8 is formed. In succession, an insulating film 9 is formed on the gate electrode and the semiconductor substrate 1, and a sidewall 12 formed of the insulating film 9 is formed only on the side of the gate electrode 8 by anisotropically etching the insulating film 9. Thereafter, impurity ions are implanted again into the source forming region and the drain forming region 10 so as to make the regions 10 as high in concentration as prescribed, and a source impurity diffusion layer 15 and a drain impurity diffusion layer 15 both deep are formed by a thermal treatment. By this setup, both a source and a drain region can be prevented from increasing in resistance as much as possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a MOS transistor.

[0002]

2. Description of the Related Art A conventional method of manufacturing a semiconductor device having a MOS transistor will be described with reference to FIGS. First, for example, B ions are applied to a P well forming region of the P type silicon substrate 1 at a dose of 100 keV.
After implanting at 2.0 × 10 ¹³ cm ^-2 , for example, P ions are implanted into the N well formation region at a dose of 160 keV and 6.4 × 1.
Then, the P well region 2 and the N well region 3 are formed by performing a heat treatment at 1190 ° C. for 150 minutes by implanting at 0 ¹² cm ⁻² (see FIG. 13A). After that, the element isolation region 4 is formed by the LOCOS method (see FIG. 13A).

Next, in order to obtain a desired threshold voltage in the P well region 2, for example, B ions of 15 keV, 1.
0 × 10 ¹³ cm by adjusting the concentration of the channel surface by injecting ^-2, followed by N-well region 3 a dose of for example P ions in order to obtain a desired threshold voltage during 120ke
V, 1.0 × 10 ¹³ cm ⁻² , and then As ions are implanted at a dose of 40 keV and 2.5 × 10 ¹² cm ⁻² to adjust the concentration on the channel surface (FIG. 13 (b )
reference).

In order to simplify the explanation, the N-channel MO will be described below.
Only the manufacture of the S-transistor is illustrated. 14
First, as shown in (a), for example, 10% HCl at 800 ° C.
By oxidizing the surface of the semiconductor substrate 1 in an atmosphere, for example, a gate insulating film 7 made of SiO _{2 having a} thickness of 7 nm is formed, and further, a thickness of ₂ nm is formed on the insulating film 7 by LPCVD.
A polysilicon film 8 of 00 nm is deposited, and an N channel MO
On the polysilicon film 8 on the S transistor region, for example, As
Ions are implanted at a dose of 40 keV and 3.0 × 10 ¹⁵ cm ⁻² , and BF ₂ ions, for example, are implanted at a dose of 35 keV in the polysilicon film on the P-channel MOS transistor region.
Implantation is performed at 1.0 × 10 ¹⁵ cm ^-2 , and patterning is performed using, for example, the RIE method to form the gate electrode 8. In addition,
Impurities are implanted into the N-channel and P-channel MOS transistor regions by using PEP (photoetching method).

Next, the surface of the semiconductor substrate 1 is 850, for example.
By oxidizing with O ₂ gas at ℃
A SiO ₂ film 9 of about m is formed (see FIG. 14B). Next, the source of the N-channel MOS transistor,
For example, a dose amount of As ions is 50 in the drain formation region.
Implantation with keV, 5.0 × 10 ¹⁵ cm ^-2 , and heat treatment are performed to form source / drain regions 10 ′ (FIG. 14B).
reference). In the source / drain formation region of the P-channel MOS transistor, for example, BF ₂ ions are implanted at a dose amount of 35 keV and 3.0 × 10 ¹⁵ cm ⁻² , and a similar heat process is performed to form the source / drain region. Form.

Next, a 100 nm-thick insulating film made of, for example, Si ₃ N ₄ is formed on the surface of the semiconductor substrate 1 by the CVD method, and the RIE method is performed so that the insulating film 12 remains only on the side surface of the gate electrode 8. Is used to etch the insulating film 12, and thereafter the SiO ₂ on the surface of the semiconductor substrate 1 and the gate electrode 8 is etched.
The oxide film 9 made of is removed by performing HF treatment (see FIG. 14C).

Next, a metal film 16 made of, for example, Ni and having a thickness of 20 nm is deposited on the surface of the semiconductor substrate 1 by a sputtering method (see FIG. 15A). Then, for example, by annealing in a nitrogen atmosphere at 600 ° C. for 30 seconds, a silicide film 17 is formed on the surfaces of the source / drain regions 10 ′ and the gate electrode (see FIG. 15B).
Then, the SC-2 solution (HCl: H ₂ O ₂ : H ₂ O =
By dipping the semiconductor substrate 1 in a 1: 1: 6 solution), the Ni film 16 remaining unreacted on the oxide film 4 and the nitride film 12 is removed (see FIG. 15C).

After that, an interlayer insulating film (not shown) made of SiO _{2 is} deposited to a thickness of, for example, 500 nm by the CVD method, contact holes are opened, and an Al film containing 1% of Si is sputtered. A wiring portion is formed by depositing and patterning. And for example 450
A passivation film of SiO _{2 having} a thickness of 1000 nm is formed on the surface portion through sintering in a forming gas atmosphere at ℃.

[0009]

When the MOS transistor is manufactured by the conventional manufacturing method described above, the sidewall 1 is formed.
2 is formed, the side wall 12 made of Si ₃ N ₄ and S
If the selection ratio of the plasma etching with respect to the oxide film 9 made of io ₂ and the Si substrate 1 is not sufficient, if the surface of the Si substrate 1 is transiently abraded, the source and drain regions 10 ′ into which impurities have already been implanted are removed. There is a problem in that the junction becomes shallow and the junction becomes shallow, which increases the resistance of the source and drain regions 10 '.

Similarly, if the selection ratio is not sufficient when forming the side wall 12, the surface of the substrate 1 is scraped by plasma etching to form a surface with poor flatness, and a salicide (self aligned silicide) after that is formed. ), The unevenness of the surface of the substrate 1 and the silicide interface increases due to
There is a problem that the junction breakdown voltage decreases and the junction leak current increases.

The present invention has been made in consideration of the above circumstances, and an object thereof is to prevent the resistance of the source and drain regions from increasing as much as possible even if the surface of the silicon substrate is shaved. It is to provide a method for manufacturing a semiconductor device.

Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing a decrease in junction breakdown voltage and an increase in junction leakage current as much as possible even if the surface of a silicon substrate is scraped. Especially.

[0013]

The method of manufacturing a semiconductor device according to the first aspect of the present invention having the above-described structure includes a first step of forming a gate oxide film and a gate electrode on a surface of a semiconductor substrate, and the gate electrode. Second step of implanting impurities into the source and drain formation regions after forming the insulating layer, and forming an insulating film on the surface of the gate electrode and the semiconductor substrate, and then etching the insulating film by anisotropic etching The method includes a third step of leaving the side wall made of the insulating film only on the side surface of the gate electrode, and a fourth step of injecting impurities again into the source and drain forming regions so as to have a predetermined concentration. It is characterized by

The method of manufacturing a semiconductor device according to the second aspect of the present invention having the above-described structure includes a first step of forming a gate oxide film and a gate electrode on the surface of a semiconductor substrate,
After forming the gate electrode, a second step of injecting impurities into the source / drain forming regions, and forming an insulating film on the surface of the gate electrode and the semiconductor substrate, and then etching the insulating film by anisotropic etching. And a third step of leaving a sidewall made of the insulating film only on the side portion of the gate electrode, and a source on the semiconductor substrate,
A fourth step of oxidizing the surface of the drain formation region and the surface of the gate electrode to form an oxide film, and then peeling off the oxide film.

[0015]

According to the method of manufacturing a semiconductor device of the first aspect of the invention configured as described above, impurity ions are implanted into the source / drain forming regions before and after forming the side wall of the gate electrode. As a result, a diffusion layer of impurity ions that is deep and extends below the side wall of the gate can be obtained, and the resistance of the source and drain regions can be prevented from increasing.

Further, according to the method of manufacturing a semiconductor device of the second aspect of the invention configured as described above, the surface of the source / drain formation region and the surface of the gate electrode of the semiconductor substrate are oxidized and oxidized after forming the side wall of the gate electrode. A film is formed and the oxide film is peeled off. As a result, it becomes possible to form a silicon surface with less unevenness, and the interface with the refractory metal silicide that is formed thereafter has high flatness, and it is possible to reduce the junction breakdown voltage and increase the junction leakage current as much as possible. Can be prevented.

[0017]

1 to 3 show the manufacturing process of an N-channel MOS transistor manufactured by the first embodiment of the manufacturing method of the first invention. The manufacturing method of this embodiment is as follows.
For example, B ions are dosed in the silicon substrate 1 at a dose of 100 k.
After injection with eV, 2.0 × 10 ¹³ cm ^-2 , for example, 119
The P well region 2 is formed by applying a heat process at 0 ° C. for 150 minutes. When manufacturing a P-channel MOS transistor, a P ion dose of 160 keV,
After implanting 6.4 × 10 ¹² cm ^-2 into the silicon substrate 1, the same heat process as described above is performed to form an N well region.

Subsequently, in order to obtain a desired threshold voltage in the P well region 2 by forming the element isolation region 4 by using, for example, the LOCOS method, for example, B ions are dosed at 15 k.
Injection is performed at eV and 1.0 × 10 ¹³ cm ^-2 (see FIG. 1A). When manufacturing a P-channel MOS transistor, for example, P ions are implanted into the N well region at a dose of 120.
Implantation is performed at a keV of 1.0 × 10 ¹³ cm ⁻² , and then As ions are implanted at a dose of 40 keV and 2.5 × 10 ¹² cm ⁻² .

Next, for example, the surface of the semiconductor substrate 1 is oxidized in a 10% HCl atmosphere at 800 ° C. to form SiO 2.
A gate insulating film 7 made of ₂ and having a thickness of 7 nm is formed, and a thickness of 2 is formed on the gate insulating film 7 by LPCVD.
A 00 nm polysilicon film 8 is deposited, and As ions are applied to this polysilicon film at a dose of 40 keV and 3.0 × 1.
0 ¹⁵ implanted in cm ^-2, to form a subsequent RIE, for example the gate electrode 8 is anisotropically etched into the polysilicon film 8 and the gate insulating film 7 by using (see Figure 1 (b)). When forming a P-channel MOS transistor,
BF ₂ ions instead of As ions, dose amount 35 ke
V, 1.0 × 10 ¹⁵ cm ^-2 .

Next, the surface of the semiconductor substrate 1 is heated to, for example, 850 ° C.
10 to 50 nm by oxidizing with O ₂ gas
An oxide film 9 made of SiO ₂ is formed to a certain extent, and As ions are applied to the source and drain forming regions 10 at a dose amount of 50 k.
Injection is performed at eV and 5.0 × 10 ¹⁵ cm ^-2 (see FIG. 1C). When forming a P-channel MOS transistor, 35 keF of BF ₂ ions are used instead of As ions.
V, 3.0 × 10 ¹⁵ cm ^-2 .

Subsequently, a thickness of 100 is formed on the surface of the semiconductor substrate 1.
nm of Si ₃ N ₄ is deposited by the CVD method, and the Si ₃ N ₄ film is subjected to anisotropic etching such as RIE method to form sidewalls 1 on both sides of the gate electrode.
Form 2. Here, the RIE of the Si ₃ N ₄ film is SiO ₂
When the selection ratio with respect to the film is small, the oxide film 9 on the silicon substrate is also etched (see FIG. 2A). After that, for example, As ions are dosed at 50 keV, 5.0 × 10 ¹⁵
The deep source / drain impurity diffusion layer 15 is formed by implanting at cm ⁻² and performing heat treatment for 20 seconds in a nitrogen atmosphere at 1000 ° C., for example. The impurity concentration at this time is 10
It is in the range of ¹⁹ to 10 ²² cm ^-3 . In addition, P channel MOS
When forming a transistor, B is used instead of As ions.
F ₂ ion dose of 35 keV, 3.0 × 10 ¹⁵ cm ^-2
Then, the same heat treatment is performed. After that, HF treatment is performed to remove S on the surface of the silicon substrate and on the gate polysilicon film 8.
The iO ₂ film is peeled off (see FIG. 2B).

Next, a 20 nm-thick metal film 16 made of Ni, for example, is formed on the surface of the semiconductor substrate 1 by sputtering (see FIG. 3A), and annealed in a nitrogen atmosphere at 600 ° C. for 30 seconds, for example. The metal film 16 on the source / drain regions 15 and the gate electrode 8 is silicided to form a silicide film 17 made of, for example, NiSi (see FIG. 3B). Then, the non-silicided Ni film 16 remaining on the sidewall 12 and the element isolation oxide film 4 is removed by immersing in the SC-2 solution (see FIG. 3C). After that, the semiconductor device is manufactured through the wiring process as in the conventional semiconductor device manufacturing method.

In the first embodiment of the first aspect of the present invention, impurity ions are implanted into the source and drain forming regions before and after forming the side wall of the gate electrode 8 to make it deeper and below the side wall 12. It is possible to obtain a diffusion layer of impurity ions extending up to this point. As a result, the high resistance resulting from the shallowness of the impurity ion diffusion layer 15 and the high resistance resulting from the fact that the impurity ion diffusion layer 15 does not extend below the gate electrode do not occur, and the source and drain regions 15 are It is possible to prevent the resistance from increasing.

Next, FIG. 4 is a sectional view showing the steps of manufacturing a semiconductor device manufactured by the manufacturing method according to the second embodiment of the first invention.
Shown in (a) and (b). The manufacturing method of this embodiment is the same as the manufacturing method of the first embodiment of the first invention until the Si ₃ N ₄ film 12 is deposited on the surface of the semiconductor substrate 1 to form the side wall 12 of the gate electrode 8. Do the same. Then Si
The side wall 12 of the gate electrode 8 is formed by anisotropically etching the ₃ N ₄ film and the oxide film 9. At this time, the surface of the semiconductor substrate 1 is etched from the original interface by, for example, about 2 to 50 nm (see FIG. 4A).

Subsequently, impurities are implanted into the source / drain formation region 10 in the same manner as in the first embodiment, and a thermal process is performed to form deep source / drain regions 15 (see FIG. 4B). .. Thereafter, FIG. 3 of the first embodiment.
The semiconductor device is completed using the same manufacturing process as the process shown in (a) and subsequent processes. The manufacturing method of the second embodiment of the first invention can also obtain the same effects as those of the manufacturing method of the first embodiment of the first invention.

Next, FIG. 5 is a sectional view showing the steps of manufacturing a semiconductor device manufactured by the manufacturing method of the first embodiment of the second invention.
Through FIG. The manufacturing method of this embodiment is the same as the manufacturing method of the first embodiment of the first invention until the side walls 12 made of Si ₃ N ₄ are formed on both side surfaces of the gate electrode 8 (FIG. 5). (See (a)). After that, the semiconductor substrate 1
The surface of the SiO ₂ film is oxidized, for example, by O ₂ gas at 850 ° C. to form a SiO ₂ film 14 having a thickness of about 10 to 50 nm on the surface of the source / drain region 10 ′ and the surface of the gate electrode 8 (FIG. )reference).

Then, the oxide film 14 on the surfaces of the semiconductor substrate 1 and the gate electrode 8 is removed by, for example, HF treatment (see FIG. 5C), and then the surface of the semiconductor substrate 1 is exposed to N, for example.
A metal film 16 made of i and having a thickness of 20 nm is deposited by sputtering (see FIG. 6A). Next, for example, by annealing for 30 seconds in a nitrogen atmosphere at 600 ° C., N on the surface of the source / drain region 10 ′ and the gate electrode 8 is
The i film 16 is silicidized to form a silicide film 17 (see FIG. 6B). Then, the Ni film 16 which is not silicified on the Si ₃ N ₄ film and the element isolation oxide film 4 is removed by immersing in the SC-2 solution (see FIG. 6C), and thereafter, the conventional semiconductor is used. A semiconductor device is manufactured by performing a wiring process and the like in the same manner as the device.

According to the manufacturing method of the first embodiment of the second invention, after forming the side wall 12 of the gate electrode 8, the semiconductor surface is oxidized to form an oxide film on the source and drain regions. This makes it possible to remove the damaged layer due to plasma etching when forming the side wall,
The interface between silicon and silicide can be made flat, and the decrease in junction breakdown voltage and the increase in junction leakage current can be prevented as much as possible.

Next, FIG. 7 is a sectional view showing the steps of manufacturing a semiconductor device manufactured by the manufacturing method of the second embodiment of the second invention.
Shown in. The manufacturing method of this embodiment is the same as the manufacturing method of the first embodiment of the second invention, but when the anisotropic etching for forming the side wall 12 is performed, the semiconductor substrate 1 is, for example, about 2 to 50 nm from the original interface. Deeply etch (Fig. 7
(See (a)). After that, the surface of the semiconductor substrate is heated to, for example, 850 ° C.
O ₂ gas to form an oxide film 14 on the source / drain regions 10 ′ and the gate electrode 8 (see FIG. 7B), and then the oxide film 14 is removed by, for example, HF treatment (see FIG. 7B). See FIG. 7C). Thereafter, the same steps as the steps shown in FIG. 6A and subsequent figures of the first embodiment of the second invention are performed to manufacture a semiconductor device. The manufacturing method of the second embodiment of the second invention can also obtain the same effects as those of the manufacturing method of the first embodiment of the second invention.

Next, FIG. 8 is a sectional view showing the steps of manufacturing a semiconductor device manufactured by the manufacturing method of the third embodiment of the second invention.
Shown in. The manufacturing method of this embodiment, in the manufacturing method of the first embodiment of the second invention, SiO ₂ film by O ₂ gas oxidation of the surface of the semiconductor substrate 1, for example 850 ° C. 9
The same steps as those in the first embodiment of the second invention are carried out until the formation of. After that, if it is an N-channel transistor in the source / drain formation region 11, for example, As or P ions are introduced at 30 to 50 KeV, 1 × 10 ¹⁴ cm ⁻² , and if it is a P-channel transistor, for example, BF ₂ or B.
Ions are introduced at 35 KeV and 1 × 10 ¹⁴ cm ⁻² . (Fig. 8
reference). After that, like the first embodiment of the first invention,
A semiconductor device is formed by performing the steps after the sidewall formation shown in FIG. The manufacturing method of the third embodiment can also obtain the same effect as that of the first embodiment of the second invention.

Next, FIG. 9 is a sectional view showing the steps of manufacturing a semiconductor device manufactured by the manufacturing method of the fourth embodiment of the second invention.
Shown in. The manufacturing method of this embodiment is performed in the same manner as the first embodiment of the second invention until the oxide film 9 is formed on the surface of the semiconductor substrate 1. Then, the source / drain formation region 11
P ions are implanted at a dose of 40 KeV and 7.0 × 10 ¹³ cm ^-2 , and then As ions are implanted at a dose of 50 KeV and 5.0.
Inject at × 10 ¹⁵ cm ^-2 (see Figure 9). Thereafter, similar to the first embodiment of the second invention, the subsequent steps shown in FIG. 5A are performed to form a semiconductor device. In this embodiment, the source / drain regions 11 which are deep and diffused to the lower part of the gate electrode 8 can be formed by performing the above-mentioned impurity introduction heat treatment. The manufacturing method of the fourth embodiment is also the third one.
It is possible to obtain the same effect as the manufacturing method of the embodiment.

Next, FIG. 1 is a sectional view showing the steps of manufacturing a semiconductor device manufactured by the manufacturing method of the fifth embodiment of the second invention.
It shows in 0. The manufacturing method of this embodiment is performed in the same manner as the first embodiment of the second invention until the oxide film 9 is formed on the surface of the semiconductor substrate 1. After that, P ions are added to the source / drain 11 forming region at an angle with respect to the normal line of the surface of the substrate 1,
For example, tilted at 45 degrees, dose amount 40 KeV, 7.0 × 1
Implantation at 0 ¹³ cm ^-2 followed by As ion dose 50 Ke
V, 5.0 × 10 ¹⁵ cm ^-2 (see FIG. 10). Thereafter, similar to the first embodiment of the second invention, the subsequent steps shown in FIG. 5A are performed to form a semiconductor device. In this embodiment, the source / drain regions 11 which are deep and diffused to below the gate electrode 8 can be formed by the subsequent heat treatment by introducing the above impurities. The manufacturing method of the fifth embodiment can also obtain the same effect as that of the fourth embodiment.

Next, FIG. 1 is a sectional view showing the steps of manufacturing a semiconductor device manufactured by the manufacturing method according to the sixth embodiment of the second invention.
Shown in 1. The manufacturing method of this embodiment is a combination of the first embodiment of the first invention and the first embodiment of the second invention. Until the side wall 12 of the gate electrode 8 is formed, it is performed in the same manner as in the first embodiment of the second invention (see FIG. 11A). After that, the surface of the substrate 1 is oxidized with O ₂ gas at 850 ° C. to form an oxide film 14, and then As
Ions are implanted with a dose amount of 50 KeV and 5.0 × 10 ¹⁵ cm ^-2 , and a deep source / drain region 15 is formed by performing heat treatment for about 20 seconds in a nitrogen atmosphere at 1000 ° C., for example (FIG. 11B. )reference). In addition, P channel MO
When manufacturing an S transistor, for example, BF ₂ ions are used instead of As ions at a dose of 35 KeV, 3.0 × 10 5.
^Implant at ¹⁵ cm ^-2 and apply similar heat treatment.

Next, the oxide film 14 is peeled off by, for example, HF treatment, and the surface of the semiconductor substrate 1 is made of, for example, Ni to a thickness of 2
A 0 nm metal film 16 is deposited (see FIG. 11C).
After that, the semiconductor device is formed by performing the subsequent steps shown in FIG. 3B of the first embodiment of the first invention. This second
The manufacturing method according to the sixth embodiment of the invention is
It is possible to obtain the same effect as the embodiment of
The same effect as that of the first embodiment of the invention can be obtained.

Next, FIG. 1 is a sectional view showing the steps of manufacturing a semiconductor device manufactured by the manufacturing method according to the seventh embodiment of the second invention.
2 shows. The manufacturing method of this embodiment is a combination of the second embodiment of the first invention and the second embodiment of the second invention. Until the side wall 12 of the gate electrode 8 is formed, the same process as in the second embodiment of the second invention is performed (see FIG. 12A)). After that, the surface of the substrate 1 is oxidized with O ₂ gas at 850 ° C., for example, to form an oxide film 14, and then the oxide film 14 is formed.
Deep source / drain regions 1 are formed by implanting s ions with a dose amount of 50 KeV and 5.0 × 10 ¹⁵ cm ^-2 , and performing heat treatment in a nitrogen atmosphere at 1000 ° C. for about 20 seconds.
5 is formed (see FIG. 12B). When manufacturing a P-channel MOS transistor, for example, BF ₂ ions are used instead of As ions at a dose of 35 KeV, 3.0 ×.
Implantation is performed at 10 ¹⁵ cm ^-2 , and the same heat treatment is performed.

Next, the oxide film 14 is peeled off by, for example, HF treatment, and a metal film 16 made of, for example, Ni and having a thickness of 20 nm is deposited on the surface of the substrate 1 (see FIG. 12C). After that, the semiconductor device is formed by performing the subsequent steps shown in FIG. 3B of the second embodiment of the first invention. The manufacturing method of the seventh embodiment of the second invention can obtain the same effect as that of the second embodiment of the first invention and the same effect as that of the second embodiment of the second invention. Obtainable. In addition,
Although Ni is used to form the metal film 16 in the above-described embodiment, a refractory metal such as Ti, Co, W, Mo, or V may be used instead of Ni.

[0037]

According to the first aspect of the present invention, since it is possible to obtain a source / drain diffusion layer which is deep and has a predetermined concentration, it is possible to prevent the resistance of the source / drain region from increasing. can do. According to the second aspect, since the surfaces of the source and drain regions are smoothed, it is possible to suppress the junction leak current after silicidation and prevent the junction breakdown voltage from decreasing as much as possible.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process of a first embodiment of the first invention.

FIG. 2 is a sectional view of the manufacturing process of the first embodiment of the first invention.

FIG. 3 is a sectional view of a manufacturing process of the first embodiment of the first invention.

FIG. 4 is a sectional view of a manufacturing process of a second embodiment of the first invention.

FIG. 5 is a sectional view of a manufacturing process of the first embodiment of the second invention.

FIG. 6 is a sectional view of a manufacturing process of the first embodiment of the second invention.

FIG. 7 is a sectional view of a manufacturing process of a second embodiment of the second invention.

FIG. 8 is a sectional view of a manufacturing process of the third embodiment of the second invention.

FIG. 9 is a manufacturing step sectional view of a fourth embodiment of the second invention.

FIG. 10 is a manufacturing step sectional view of a fifth embodiment of the second invention.

FIG. 11 is a sectional view of a manufacturing process of the sixth embodiment of the second invention.

FIG. 12 is a manufacturing step sectional view of a seventh embodiment of the second invention.

FIG. 13 is a process sectional view according to a conventional manufacturing method.

FIG. 14 is a process sectional view according to a conventional manufacturing method.

FIG. 15 is a process sectional view according to a conventional manufacturing method.

[Explanation of symbols]

1 semiconductor substrate 2 P well 4 element isolation oxide film 7 gate oxide film 8 gate electrode 9 SiO ₂ film 10 source / drain forming ion implantation region 10 ′ source, drain region 15 source / drain region 12 sidewall (Si ₃ N ₄ ) 16 Ni film 17 Silicide (NiSi) film

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toyota Morimoto 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Toshiba Research Institute Ltd. Muko Toshiba Town 1 Stock Company Toshiba Research Institute

Claims (2)

[Claims] 1. A first step of forming a gate oxide film and a gate electrode on a surface of a semiconductor substrate, a second step of forming an impurity into a source / drain formation region after forming the gate electrode, and the gate. A third step of forming an insulating film on the surface of the electrode and the semiconductor substrate, and then etching the insulating film by anisotropic etching to leave a sidewall made of the five-edge film only on a side surface of the gate electrode; A fourth step of implanting an impurity again into the source and drain forming regions so as to have a predetermined concentration, and a method of manufacturing a semiconductor device. 2. A first step of forming a gate oxide film and a gate electrode on the surface of a semiconductor substrate made of silicon, and a second step of implanting an impurity into a source / drain formation region after forming the gate electrode. A third step of forming an insulating film on the surface of the gate electrode and the semiconductor substrate, and then etching the insulating film by anisotropic etching to leave a sidewall made of the insulating film only on the side surface of the gate electrode. A fourth step of oxidizing the surface of the source / drain formation region and the surface of the gate electrode on the semiconductor substrate to form an oxide film, and then peeling off the oxide film. Device manufacturing method.