JPH08264482A - Method of forming semiconductor device - Google Patents

Abstract

PURPOSE: To form a low resistance high melting point metal silicide in a self alignment manner without increasing any junction leakage even when an im purity diffusion layer is very shallow. CONSTITUTION: A poly Si film 16 is formed on a gate oxide film 14 on an Si substrate into which an impurity is ion implanted, and thereafter it is patterned to form a gate electrode 18 on which a SiO2 film is deposited and thereafter a side wall 20 of the gate electrode is formed. Using them as a mask, As is ion-implanted to form an impurity diffusion layer 22 of an S/D region. After a surface oxide film is removed with hydrofluoric acid, a Co film 24 and a TiN film 26 are continuously sputtered. Then, a non-reacted Co film after formation of the CoSi film is removed in a first heat treatment at 550 deg.C for 30 seconds, and a second heat treatment is performed at 750 deg.C for 30 seconds like the prior art to make the CoSi film low resistance. Hereby, when the impurity diffusion layer becomes very shallow, reverse I-V characteristic of a pn junction just under the CoSi film 28 is severely varied, but provided a third heat treatment is performed after the second heat treatment is performed at 80 deg.C for 30 seconds, the variations are sharply reduced to improve the characteristic.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming electrodes in a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which refractory metal silicide is formed by self-alignment.

[0002]

2. Description of the Related Art With the high integration of LSIs, a short channel effect due to miniaturization of elements has become a problem. In order to suppress the short channel effect, it is effective to make the diffusion layer shallow, but on the other hand, there arises a problem that the diffusion layer resistance increases. Therefore, as a technique for reducing the resistance of the diffusion layer without sacrificing the depth of the diffusion layer, a method of silicidizing the gate electrode and the source / drain diffusion layer in a self-aligned manner has been studied.

A typical method of manufacturing a semiconductor device in which a silicide film is formed by self-alignment will be described with reference to FIGS. First, the element isolation film 12 is formed on the silicon substrate 10 by the LOCOS method or the like. Next, a gate oxide film 14 having a film thickness of about 10 nm is formed on the element region defined by the element isolation film 12 by thermal oxidation.

Then, a film thickness of 15 is formed on the gate oxide film 14.
A polycrystalline silicon film 16 of about 0 nm is formed by chemical vapor deposition (C
VD: Chemical Vapor Deposition) method is used for deposition, and boron (B), phosphorus (P), or arsenic (As) is ion-implanted. As a result, p-type or n-type impurities are introduced into the polycrystalline silicon film 16 (FIG. 8A). After that, the polycrystalline silicon film 16 is patterned by the usual lithography technique and etching technique to form the gate electrode 18 (FIG. 8B).

Then, after depositing a silicon oxide film having a film thickness of about 150 nm by the CVD method, anisotropic etching is performed until the gate electrode 18 is exposed to form a sidewall 20 on the side wall of the gate electrode 18. Then, using the gate electrode 18 and the sidewall 20 as a mask, B, P, or As is ion-implanted to form an impurity diffusion layer 22 to be a source / drain region.

Thereafter, a mixed solution of hydrofluoric acid and water (HF: H ₂ O
= 2: 100) for about 60 seconds to form the gate electrode 18,
The silicon oxide film on the surface of the impurity diffusion layer 22 is removed (FIG. 8C). Then, cobalt (C
o) the film 24 and titanium nitride (Ti) having a film thickness of about 30 nm.
N) Short-time annealing (RTA: Rapid Thermal Annealing) at 550 ° C. for about 30 seconds after continuously forming the film 26
Is performed to selectively form the cobalt silicide film 28 in the region where the silicon is exposed (FIGS. 8D and 9).
(A)).

Subsequently, the TiN film 26 and the unreacted Co film 24 are removed by a mixed solution of ammonia water and hydrogen peroxide solution and a mixed solution of sulfuric acid and hydrogen peroxide solution. afterwards,
Heat treatment is performed at 750 ° C. for about 30 seconds to reduce the resistance of the formed cobalt silicide film 28 (FIG. 9B). In this way, on the gate electrode 18 and the impurity diffusion layer 22,
The cobalt silicide film 28 was selectively formed.

[0008]

However, in the above-described conventional method for manufacturing a semiconductor device, the cobalt silicide film 28 is formed by the reaction with the underlying silicon, so that the impurity diffusion layer 22 may enter the inside of the silicon substrate. Is formed. Therefore, there is a problem that the cobalt silicide film 28 penetrates the impurity diffusion layer 22 when the depth of the impurity diffusion layer 28 becomes 0.1 μm or less.

Further, even if the cobalt silicide film 28 does not penetrate the impurity diffusion layer 22, as shown in FIG. 10, the problem that the junction leak current increases when a reverse bias is applied to the impurity diffusion layer 22. was there. Further, if the thickness of the deposited Co film 24 is reduced and the thickness of the formed cobalt silicide film 28 is reduced in order to prevent the penetration of the cobalt silicide film 28 and the like, the resistance of the cobalt silicide film 28 increases. There was a problem that it would end up.

It is an object of the present invention that the impurity diffusion layer 22 has a thickness of 0.
It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of forming a low-resistance refractory metal silicide in a self-aligned manner without increasing junction leakage even when the depth is 1 μm or less.

[0011]

The above object is to provide a refractory metal film deposition step of depositing a refractory metal film on an impurity diffusion layer, and a heat treatment at a first temperature to form a high melting point metal film on the impurity diffusion layer. A first heat treatment step of forming a melting point metal silicide film; a refractory metal film removal step of removing the refractory metal film that has not reacted in the first heat treatment step; and a second heat treatment step higher than the first temperature. Second heat treatment at temperature
And a third heat treatment step of performing heat treatment at a third temperature higher than the second temperature.

In the method of manufacturing a semiconductor device described above, after the second heat treatment step is completed, the temperature is raised from the second temperature to the third temperature and the third heat treatment step is performed. desirable. Further, in the above-described method for manufacturing a semiconductor device, it is desirable that the refractory metal film is a cobalt film.

Further, in the above-mentioned method for manufacturing a semiconductor device, in the first heat treatment step, short-time annealing is performed at a temperature of 525 to 625 ° C., and in the second heat treatment step, a short annealing is performed at a temperature of 735 ° C. or higher. It is desirable to perform time annealing. Further, in the above-described method for manufacturing a semiconductor device, it is desirable that short-time annealing is performed at a temperature of 800 ° C. or higher in the third heat treatment step.

Further, in the above-described method for manufacturing a semiconductor device, it is desirable that furnace annealing is performed at a temperature of 400 to 500 ° C. in the first heat treatment step.

[0015]

According to the present invention, the refractory metal silicide film is selectively formed by the first heat treatment to remove unreacted refractory metal, and then the second heat treatment is performed at a temperature higher than the first heat treatment temperature. By performing the third heat treatment at a temperature higher than the second heat treatment temperature, the reverse leakage characteristic of the pn junction formed immediately below the refractory metal silicide film is improved, so that the impurity diffusion layer becomes 0.1 μm or less. The diffusion layer resistance can be reduced even when the depth becomes shallow.

After the second heat treatment step is completed, the temperature is raised from the second temperature to the third temperature and the heat treatment step at the third temperature is performed. Therefore, the pn formed directly under the refractory metal silicide film is used. The reverse leakage characteristic of the junction is improved, and the resistance of the diffusion layer can be reduced even when the impurity diffusion layer is as shallow as 0.1 μm or less. Further, in the above-described method for manufacturing a semiconductor device, a cobalt film can be applied as the refractory metal film.

Also, in the first heat treatment step,
Improving the reverse leakage characteristic of the pn junction formed directly under the refractory metal silicide film by performing short-time annealing at a temperature of 625 ° C. and performing short-time annealing at a temperature of 735 ° C. or higher in the second heat treatment step. You can
In addition, by performing short-time annealing at a temperature of 800 ° C. or higher in the third heat treatment step, it is possible to improve the reverse leakage characteristic of the pn junction formed immediately below the refractory metal silicide film.

In the first heat treatment step,
By performing furnace annealing at a temperature of 500 ° C., it is possible to improve the reverse leakage characteristic of the pn junction formed immediately below the refractory metal silicide film.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. Figure 1 is p
FIGS. 2 and 3 are graphs showing a reverse leakage characteristic in an n-junction, FIGS. 2 and 3 are graphs showing a reverse leakage characteristic in a pn junction and a graph showing a heat treatment temperature profile, and FIGS. 6 is a graph showing the temperature dependence of the heat treatment of No. 1, FIG. 6 is a graph showing the temperature dependence of the second heat treatment in this embodiment, and FIG. 7 is a graph showing the temperature dependence of the third heat treatment in this embodiment. 8 and 9 are process cross-sectional views showing a method for manufacturing a semiconductor device in which a refractory metal silicide film is formed in a self-aligned manner.

As described above, in the conventional method of manufacturing a semiconductor device, the cobalt silicide film 28 is formed by the first heat treatment at 550 ° C. for 30 seconds, the unreacted Co film is removed, and the 750 ° C. for 30 seconds is used. The heat treatment of 2 reduced the resistance of the cobalt silicide film 28. But,
When the impurity diffusion layer has a depth of about 0.1 μm or less, the reverse IV characteristic of the pn junction directly below the cobalt silicide film 28 thus formed has a very large variation as shown in FIG. 10A. Was great.

The inventor of the present application has found that it is effective to carry out the second heat treatment at two stages of temperature as a method for preventing such variations in IV characteristics. First, a method of measuring the reverse leak characteristic performed by the inventor of the present application will be described with reference to FIG. A Co film 24 is deposited on the P-type silicon substrate 10 in which the impurity diffusion layer 22 is formed in the element region defined by the element isolation film 12 (FIG. 1A), and cobalt silicide is formed in the element region by the first heat treatment. Membrane 28
Was formed (FIG. 1 (b)). Then, the unreacted Co film is removed, and the second heat treatment and the third heat treatment are performed to form a cobalt silicide film 28 having a pn junction formed directly thereunder in a self-aligned manner (FIG. 1).
(C)).

A reverse bias was applied to the pn junction thus formed to measure the reverse leakage current, and the variation of the leakage current was investigated (FIG. 1 (d)). A pn junction having a junction area of about 180 × 880 μm ² was used, and 60 to 70 chips were measured for each condition. In FIG. 2A, short-time annealing at 550 ° C. for 30 seconds is performed as the first heat treatment, and short-time annealing at 750 ° C. for 30 seconds and short-time annealing at 800 ° C. for 30 seconds are successively performed as the second heat treatment. It is the reverse IV characteristic of the case (FIG. 2B). As shown in the figure, although there is some variation on the high electric field side,
By performing the heat treatment of 2 in two steps, it is possible to reduce variations in the IV characteristics.

FIG. 3A shows the first heat treatment at 550.
Annealing is performed at 30 ° C. for a short time, second annealing is performed at 750 ° C. for 30 seconds, and then a third annealing is performed.
FIG. 3B shows a reverse IV characteristic when a short time annealing at 800 ° C. for 30 seconds is performed as the heat treatment of FIG. As shown in the drawing, even when the third heat treatment higher than the temperature of the second heat treatment is performed after the second heat treatment, the variation in the IV characteristics can be significantly reduced.

FIG. 10B shows the first heat treatment 55.
This is a case where short-time annealing at 0 ° C. for 30 seconds and short-time annealing at 800 ° C. for 30 seconds are performed as the second heat treatment. Thus, almost no improvement in the IV characteristics is observed only by raising the temperature of the second heat treatment to 800 ° C., and it is understood that the effect of performing the second heat treatment in two stages is great. Next, the optimum processing temperature in the first heat treatment will be described.

FIGS. 4 and 5 are diagrams showing the condition dependence of the first heat treatment when the second heat treatment is performed in two steps. 4 (a) uses a furnace anneal (FA) of 450 ° C. for 30 minutes as the first heat treatment, and FIG. 4 (b) uses a short-time anneal of 500 ° C. for 30 seconds as the first heat treatment. 5 shows a case where short-time annealing at 650 ° C. for 30 seconds is used as the first heat treatment.

As shown in the figure, the variation of the IV characteristics is caused by the first heat treatment temperature of 450 ° C., 500 ° C., 550.
The higher the temperature becomes (° C (Fig. 2 (a)), the smaller the temperature becomes. However, if the first heat treatment temperature is raised to 650 ° C., the LO
The cobalt silicide film creeps up at the edge of the COS oxide film, increasing the leak current. Therefore, it is desirable that the first heat treatment is performed at about 525 to 625 ° C. so that the variation in characteristics is small and the leak current is small.

Next, the optimum processing temperature in the second heat treatment will be described. FIG. 6 shows 55 as the first heat treatment.
Second case when short-time annealing at 0 ° C. for 30 seconds is performed, and short-time annealing at 800 ° C. for 30 seconds is performed as the third heat treatment.
FIG. 6 is a diagram showing the heat treatment condition dependency of the heat treatment of FIG. Figure 6
6A shows a case where a second heat treatment is performed at 725 ° C. for a short time of 30 seconds, and FIG.
This is the case where short-time annealing at 75 ° C. for 30 seconds is performed.

As shown, the temperature of the second heat treatment is set to 7
By setting the temperature higher than 25 ° C., it is possible to greatly reduce the variation in the IV characteristics. Next, the third
The optimum processing temperature in the heat treatment of is described. FIG. 7 shows the condition dependence of the heat treatment of the third heat treatment when the first heat treatment is a short-time anneal at 550 ° C. for 30 seconds and the second heat treatment is a short-time anneal at 750 ° C. for 30 seconds. It is a figure. FIG. 7A shows the case where short-time annealing at 825 ° C. for 30 seconds is performed as the third heat treatment, and FIG. 7B shows the case where short-time annealing at 850 ° C. for 30 seconds is performed as the third heat treatment.

As shown in the figure, there is almost no dependency on the temperature of the third heat treatment, but if the temperature of the third heat treatment is set to 800 ° C. or higher, good IV characteristics can be obtained. . As described above, the second heat treatment is performed at two temperatures, or the third heat treatment is performed after the second heat treatment, so that variation in reverse IV characteristic of the pn junction and leakage current are reduced. be able to.

Next, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. First, p
An element isolation film 12 having a thickness of about 250 nm is formed on the type silicon substrate 10 by the LOCOS method or the like. Then, a film thickness 10 is formed on the device region defined by the device isolation film 12.
A gate oxide film 14 of about nm is formed by thermal oxidation.

Then, a film thickness of 15 is formed on the gate oxide film 14.
A polycrystalline silicon film 16 of about 0 nm is deposited by the CVD method, and B, P or As is ion-implanted. As a result, p-type or n-type impurities are introduced into the polycrystalline silicon film 16 (FIG. 8A). After that, the polycrystalline silicon film 16 is formed by usual lithography and etching techniques.
Is patterned to form a gate electrode 18 having a gate length of 0.25 μm (FIG. 8B).

Next, after depositing a silicon oxide film with a film thickness of about 150 nm by the CVD method, anisotropic etching is performed until the gate electrode 18 is exposed, and a sidewall 20 is formed on the side wall of the gate electrode 18. After forming a silicon oxide film having a film thickness of about 5 nm by thermal oxidation, As ions are ion-implanted under the conditions of an acceleration voltage of 25 keV and an implantation amount of 2 × 10 ¹⁵ cm ^{-2 using} the gate electrode 18 and the sidewall 20 as a mask, Impurity diffusion layers 22 to be the source / drain regions are formed (FIG. 8C).

Subsequently, heat treatment is performed at 850 ° C. for about 10 minutes to diffuse and activate the injected As. After that, the silicon oxide film on the surface of the gate electrode 18 and the impurity diffusion layer 22 is removed by immersing in a mixed solution of hydrofluoric acid and water (HF: H ₂ O = 2: 100) for about 60 seconds. Then, a Co film 24 having a film thickness of about 10 nm and a TiN film 26 having a film thickness of about 30 nm are continuously formed. Both the Co film 24 and the TiN film 26 are deposited by the sputtering method. When the Co film is formed, the pressure is 0.1 Pa, the argon flow rate is 100 sccm, the RF power applied to the target is 3.7 W / cm ^2, and T
When forming the iN film, the pressure was 0.1 Pa, the argon flow rate was 50 sccm, the nitrogen flow rate was 50 sccm, and the RF power applied to the target was 3.7 W / cm ² (FIG. 8).
(D)).

In this way, the Co film 24 and the TiN film 2 are
After forming the laminated film of No. 6, as the first heat treatment, 550 ° C.
Annealing is performed for a short time of 30 seconds to selectively form the cobalt silicide film 28 in the region where silicon is exposed (FIG. 9A). Then, the TiN film 26 is removed by immersing in a mixed solution of ammonia water and hydrogen peroxide solution heated to 70 ° C., and unreacted Co is immersed in a mixed solution of sulfuric acid and hydrogen peroxide solution. The film 24 is removed. Thereby, the gate electrode 1
8 and the cobalt silicide film is selectively left on the impurity diffusion layer 22.

Then, as the second heat treatment, 750 ° C. 30
Second short time annealing, 800 ° C 3 as the third heat treatment
Annealing is performed for a short time of 0 second to reduce the resistance of the cobalt silicide film 28 formed by the first heat treatment (FIG. 9).
(B)). Then, a silicon oxide film having a thickness of about 700 nm is deposited by the CVD method to form the interlayer insulating film 30.

Subsequently, the contact hole 32 is formed by the usual lithography technique and etching technique.
After that, a titanium (Ti) film with a thickness of about 20 nm and TiN
A wiring layer 34 composed of a film and a laminated film of an aluminum (Al) film is formed (FIG. 9C). MO in this way
By forming the S-type transistor, the reliability of the pn junction can be secured without increasing the diffusion layer resistance even when the impurity diffusion layer 22 becomes shallow.

As described above, according to this embodiment, after the cobalt silicide film is selectively formed by the first heat treatment to remove the unreacted cobalt, the second heat treatment at a temperature higher than the first heat treatment temperature is performed. Since the heat treatment and the third heat treatment at a temperature higher than the second heat treatment temperature are performed, good leak characteristics can be obtained even when the impurity diffusion layer becomes shallow as 0.1 μm or less.

As a result, since a low resistance cobalt silicide film can be formed, it is possible to suppress a signal transmission delay and the like due to the diffusion layer resistance. In the above example, short-time annealing was used for the first heat treatment,
The cobalt silicide film may be formed using furnace annealing. In this case, the heat treatment temperature is preferably set in the temperature range of about 400 to 500 ° C.

Further, in the above embodiment, the first heat treatment was carried out in the state where the Co film and the TiN film were laminated to form the cobalt silicide film. However, immediately after the Co film was deposited, the first heat treatment was carried out to perform the cobalt silicide. A film may be formed.

[0040]

As described above, according to the present invention, after the refractory metal which has not reacted is selectively formed by the first heat treatment to remove the unreacted refractory metal, the temperature is higher than the first heat treatment temperature. By performing the second heat treatment at a temperature and the third heat treatment at a temperature higher than the second heat treatment temperature, the reverse leakage characteristic of the pn junction formed immediately below the refractory metal silicide film is improved. The diffusion layer resistance can be reduced even when the depth becomes 0.1 μm or less.

After the second heat treatment step is finished, the temperature is raised from the second temperature to the third temperature and the heat treatment step at the third temperature is performed. Therefore, the pn formed directly below the refractory metal silicide film is used. The reverse leakage characteristic of the junction is improved, and the resistance of the diffusion layer can be reduced even when the impurity diffusion layer is as shallow as 0.1 μm or less. Further, in the above-described method for manufacturing a semiconductor device, a cobalt film can be applied as the refractory metal film.

In the first heat treatment step,
Improving the reverse leakage characteristic of the pn junction formed directly under the refractory metal silicide film by performing short-time annealing at a temperature of 625 ° C. and performing short-time annealing at a temperature of 735 ° C. or higher in the second heat treatment step. You can
In addition, by performing short-time annealing at a temperature of 800 ° C. or higher in the third heat treatment step, it is possible to improve the reverse leakage characteristic of the pn junction formed immediately below the refractory metal silicide film.

In the first heat treatment step, 400 to
By performing furnace annealing at a temperature of 500 ° C., it is possible to improve the reverse leakage characteristic of the pn junction formed immediately below the refractory metal silicide film.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a method of measuring a reverse leak characteristic in a pn junction.

FIG. 2 is a graph showing a reverse leakage characteristic of a pn junction formed according to the present invention and a graph showing a heat treatment temperature profile (No. 1).

FIG. 3 is a graph showing a reverse leakage characteristic of a pn junction formed according to the present invention and a graph showing a heat treatment temperature profile (No. 2).

FIG. 4 is a graph (No. 1) showing the temperature dependence of the first heat treatment in the present invention.

FIG. 5 is a graph (No. 2) showing the temperature dependence of the first heat treatment in the present invention.

FIG. 6 is a graph showing the temperature dependence of the second heat treatment in the present invention.

FIG. 7 is a graph showing the temperature dependence of the third heat treatment in the present invention.

FIG. 8 is a process sectional view (1) showing the method for manufacturing the semiconductor device in which the refractory metal silicide film is formed by self-alignment.

FIG. 9 is a process sectional view (2) showing the method for manufacturing the semiconductor device in which the refractory metal silicide film is formed in a self-aligned manner.

FIG. 10 is a graph showing reverse leakage characteristics in a pn junction formed by a conventional semiconductor device manufacturing method.

[Description of Reference Signs] 10 ... Silicon substrate 12 ... Element isolation film 14 ... Gate oxide film 16 ... Polycrystalline silicon film 18 ... Gate electrode 20 ... Sidewall 22 ... Impurity diffusion layer 24 ... Co film 26 ... TiN film 28 ... Cobalt silicide Film 30 ... Interlayer insulating film 32 ... Contact hole 34 ... Wiring layer

Claims (6)

[Claims] 1. A refractory metal film deposition step of depositing a refractory metal film on an impurity diffusion layer, and heat treatment at a first temperature to form a refractory metal silicide film on the impurity diffusion layer. A first heat treatment step, a refractory metal film removal step of removing the refractory metal film that has not reacted in the first heat treatment step, and a second heat treatment at a second temperature higher than the first temperature. A method of manufacturing a semiconductor device, comprising: a heat treatment step; and a third heat treatment step of performing heat treatment at a third temperature higher than the second temperature. 2. The method of manufacturing a semiconductor device according to claim 1, wherein after the second heat treatment step is completed, the temperature is raised from the second temperature to the third temperature, and the third heat treatment step is performed. A method of manufacturing a semiconductor device, comprising: 3. The method of manufacturing a semiconductor device according to claim 1, wherein the refractory metal film is a cobalt film. 4. The method of manufacturing a semiconductor device according to claim 1, wherein in the first heat treatment step, short-time annealing is performed at a temperature of 525 to 625 ° C., and the second heat treatment step is performed. Then, a method of manufacturing a semiconductor device, characterized in that annealing is performed for a short time at a temperature of 735 ° C. or higher. 5. The method of manufacturing a semiconductor device according to claim 4, wherein in the third heat treatment step, short-time annealing is performed at a temperature of 800 ° C. or higher. 6. The method of manufacturing a semiconductor device according to claim 1, wherein in the first heat treatment step, furnace annealing is performed at a temperature of 400 to 500 ° C. Production method.