JPS59161070A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59161070A JPS59161070A JP3442783A JP3442783A JPS59161070A JP S59161070 A JPS59161070 A JP S59161070A JP 3442783 A JP3442783 A JP 3442783A JP 3442783 A JP3442783 A JP 3442783A JP S59161070 A JPS59161070 A JP S59161070A
- Authority
- JP
- Japan
- Prior art keywords
- thermal
- film
- oxide film
- nitride film
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 150000004767 nitrides Chemical class 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 150000002500 ions Chemical class 0.000 claims abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 2
- 238000005121 nitriding Methods 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 238000000206 photolithography Methods 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 229910021529 ammonia Inorganic materials 0.000 abstract description 2
- 229910000069 nitrogen hydride Inorganic materials 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
この発明は、微細で信頼性の高い半導体装置を得ること
のできる半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a semiconductor device, which makes it possible to obtain a fine and highly reliable semiconductor device.
（従来技術）
従来のＭＯ８型半導体装置でソース、ドレイン、ダート
領域上へコンタクト孔を形成する場合、ソース、ドレイ
ン、ダート上に薄く熱酸化したシリコン酸化膜および厚
いＰＳＧ膜上にホトレジスト膜を塗布し、ホトリソグラ
フィにより、・′？ターン形成を行なった後、薄い弗酸
で厚いＰＳＧ膜および薄いシリコン酸化膜を選択的にエ
ツチングしていた６、
この方法を用いた場合、ＰＳＧ膜厚のバラツキ全考慮し
てコンタクト孔の開口ミスを防ぐためエツチング終了後
に、さらに多口にエツチングを追加すると、薄いシリコ
ン酸化膜の開口面積が大きくなシ、コンタクト孔の寸法
制御が難かしく、かつゲート、ソース間またはケ°−ト
、ドレイン間での電気的な短絡を発生させる危険性が犬
であった。(Prior art) When forming contact holes on the source, drain, and dirt regions in a conventional MO8 type semiconductor device, a photoresist film is applied on a thin thermally oxidized silicon oxide film and a thick PSG film on the source, drain, and dirt. Then, by photolithography, ・′? After forming a turn, the thick PSG film and thin silicon oxide film were selectively etched with thin hydrofluoric acid6. When this method is used, it is difficult to open contact holes by taking into account all the variations in the PSG film thickness. If more etching is added after the etching has been completed to prevent this, the opening area of the thin silicon oxide film will be large, and it will be difficult to control the size of the contact hole. There was a risk of causing an electrical short circuit in the dog.
（発明の目的）
この発明は、上記従来の欠点を除去するためになされた
もので、簡便な工程でかつエツチング制御性が良好で、
しかも微細刀ロエにおい゛ても電極間の短絡に対する信
頼性を向上させることのできる半導体装置の製造方法を
提供することを目的とする。(Object of the Invention) The present invention was made in order to eliminate the above-mentioned drawbacks of the conventional technology.
Moreover, it is an object of the present invention to provide a method for manufacturing a semiconductor device that can improve reliability against short circuits between electrodes even in the case of fine blades.
（発明の構成）
この発明の半導体装置の製造方法は、半導体基板上にダ
ート絶縁膜とポリシリコンゲート電極を形成した後にポ
リシリコンゲート電極、ソース領域、ドレイン領域を薄
い熱酸化膜で被ｂ、この薄い熱酸化膜を高温のＮＨ，雰
囲気で熱窒化して熱窒化膜を形成し、この熱窒化膜を通
してソース、ドレイン拡散層形成のためのイオン注入を
行ない、このイオン注入後にホトリングラフィによりコ
ンタクト孔形成のためのパターン形成を行ない、こツバ
ターン形成後熱屋化膜をエツチングし、ＰＳＧＳ金膜−
ス、ドレイン領域上に形成するようにしたものでわる。(Structure of the Invention) The method for manufacturing a semiconductor device of the present invention includes forming a dirt insulating film and a polysilicon gate electrode on a semiconductor substrate, and then covering the polysilicon gate electrode, source region, and drain region with a thin thermal oxide film. This thin thermal oxide film is thermally nitrided in a high-temperature NH atmosphere to form a thermal nitride film, and ions are implanted through this thermal nitride film to form source and drain diffusion layers. After forming a pattern to form a contact hole, etching the heat treatment film and removing the PSGS gold film.
This is because the drain region is formed on the drain region.
（実施例）
以下、この発明の半導体装置の製造方法の実施例につい
て図面に基づき説明する。第１図ないし第５図はその一
実施例の工程説明図であり、この発明ｔＭＯＳ型半導体
のトランジスタに適用した場合を示している。(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings. 1 to 5 are process explanatory diagrams of one embodiment of the present invention, and show a case where the present invention is applied to a tMOS type semiconductor transistor.
これらの第１図ないし第５図において、１は半導体基板
、２はダート酸化膜、３はダート電極、４はシリコン熱
酸化膜、５は熱窒化膜、６はソース、ドレイン形成のた
めの不純物、７はソース、ドレイン電極、８はコンタク
ト孔、９はＰＳＧ膜である。1 to 5, 1 is a semiconductor substrate, 2 is a dirt oxide film, 3 is a dirt electrode, 4 is a silicon thermal oxide film, 5 is a thermal nitride film, and 6 is an impurity for forming the source and drain. , 7 are source and drain electrodes, 8 is a contact hole, and 9 is a PSG film.
まず、第１図において、半導体基板１上にダート酸化膜
２およびケ゛−ト電極３全それぞれ熱酸化法、ＣＶＤ法
およびフォトリソグラフィにより形成する。First, in FIG. 1, a dirt oxide film 2 and a gate electrode 3 are formed on a semiconductor substrate 1 by thermal oxidation, CVD, and photolithography, respectively.
次に、第２図に示すように、ＭＯ８Ｉ−ランソスタ全体
を薄く酸化し、シリコン熱酸化膜４を成長させる。Next, as shown in FIG. 2, the entire MO8I-Lancester is thinly oxidized, and a silicon thermal oxide film 4 is grown.
さらに、第３図で第２図のシリコン熱酸化膜４を高温の
アンモニア雰囲気中にて熱窒化膜５に変化させ、次に、
ソース、ドレイン電極形成のための不純物６をイオン注
入する。Furthermore, in FIG. 3, the silicon thermal oxide film 4 of FIG. 2 is changed into a thermal nitride film 5 in a high temperature ammonia atmosphere, and then,
Impurity 6 for forming source and drain electrodes is ion-implanted.
次に、第４図において、フォトリングラフィによシ、金
属電極とのコンタクト領域にコンタクト孔８を薄いＨＦ
にてエツチングし形成する。Next, in FIG. 4, a contact hole 8 is formed in the contact area with the metal electrode by photolithography using a thin HF film.
Formed by etching.
熱窒化膜５は通常のシリコン熱酸化膜４に較べて耐ＨＦ
性が強く、かつＣＶＤ窒化膜のエツチングに必要となる
プラズマエツチング技術を必要としないという特徴があ
る。Thermal nitride film 5 has higher resistance to HF than normal silicon thermal oxide film 4.
It has the characteristics that it has strong etching properties and does not require the plasma etching technique required for etching CVD nitride films.
第５図において、ＰＳＧ膜９を形成し、後に通常のＭＯ
Ｓ）ランノスタ製造工程にょシＭＯ８）ランノスタの形
成を行なう。In FIG. 5, a PSG film 9 is formed, and later a normal MO
S) Runnostar manufacturing process MO8) Form a runnostar.
以上説明したように、第１の実施例ではダート、ソース
間およびゲート、ドレイン間に熱窒化膜５を介在させて
いるため、熱窒化膜の特徴である（］）耐ＨＦ性がシリ
コン熱酸化膜よりも強い。As explained above, in the first embodiment, the thermal nitride film 5 is interposed between the dirt and the source and between the gate and the drain, so that the HF resistance, which is a characteristic of the thermal nitride film, is improved by silicon thermal oxidation. Stronger than membranes.
（２） 電気耐圧が向上する。(2) Electrical withstand voltage is improved.
（３） 薄い弗酸液でエツチングができる。(3) Can be etched with a dilute hydrofluoric acid solution.
（４）熱窒化技術に特別な装置を必要としないで実現で
きる。(4) Thermal nitriding technology can be realized without requiring any special equipment.
などによシ。etc.
（１） 信頼性が高く、安定性の高いコンタクト孔形
成ができる。(1) Contact holes can be formed with high reliability and stability.
（２）微細加工技術にも有効である。(2) It is also effective in microfabrication technology.
などの利点がある。There are advantages such as
（発明の効果）
以上のように、この発明の半導体装置の製造方法によれ
ば、薄い酸化膜を高温のＮＨ３雰囲気で熱窒化膜を形成
し、この熱窒化膜を電極間に介在させるようにしたので
、コンタクト形式１程におけルコンタクト孔寸法の制御
性、エツチングでの安定性、制御性に−ｉ−ぐ九でおり
、しかも電極間の短絡に対する１６頼性も向上できるば
かりか、微細加工技術を必要とする半導体の製造方法全
般に有効である。(Effects of the Invention) As described above, according to the method of manufacturing a semiconductor device of the present invention, a thin oxide film is formed into a thermal nitride film in a high-temperature NH3 atmosphere, and this thermal nitride film is interposed between electrodes. As a result, the controllability of the contact hole size, the stability in etching, and the controllability in contact type 1 are improved, and the reliability against short circuits between electrodes is also improved. It is effective for all semiconductor manufacturing methods that require processing technology.
【図面の簡単な説明】
第１図ないし第５図はそれぞれこの発明の半導体装置の
製造方法の一実施例の工程説明図である。
１・・・半導体基板、２・・・ケ９−ト酸化膜、３・・
・ダート電極、４・・・シリコン熱酸化膜、５ ・熱窒
化膜、６・・・不純物、７・・・ソース、ドレイン電極
、８・・・コンタクト孔、９・・・ＰＳＧ膜。
第１図
第３図
第５図
第 ２ 図
第４図BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 5 are process explanatory diagrams of an embodiment of the method for manufacturing a semiconductor device of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Ke9-to oxide film, 3...
- Dirt electrode, 4... Silicon thermal oxide film, 5 - Thermal nitride film, 6... Impurity, 7... Source, drain electrode, 8... Contact hole, 9... PSG film. Figure 1 Figure 3 Figure 5 Figure 2 Figure 4
Claims (1)
を形成する工程と、上記ポリシリコンゲ−ト電極、ソー
ス領域、ドレイン領域を薄い熱酸化膜で被ってこの薄い
熱酸化膜を高温のＮ Ｈｓ雰囲気にて熱窒化して熱窒化
膜を形成する工程と、この熱窒化膜を通してソース、ド
レイン拡散層形成のためのイオン注入を行なう工程と、
このイオン注入後に熱窒化膜上にコンタクト孔形成のた
めの７４ターン形成を行なった後に熱窒化膜をエツチン
グする工程と、ＰＳＧ膜をソース、ダート、ドレイン領
域上に形成する工程とより成ることを特徴とする半導体
装置の製造方法。A process of forming a gate insulating film and a polysilicon gate electrode on a semiconductor substrate, covering the polysilicon gate electrode, source region, and drain region with a thin thermal oxide film, and then coating this thin thermal oxide film in a high-temperature NHs atmosphere. a step of thermal nitriding to form a thermal nitride film; a step of implanting ions through the thermal nitride film to form source and drain diffusion layers;
After this ion implantation, 74 turns are formed on the thermal nitride film for forming contact holes, and then the thermal nitride film is etched, and a PSG film is formed on the source, dirt, and drain regions. A method for manufacturing a featured semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3442783A JPS59161070A (en) | 1983-03-04 | 1983-03-04 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3442783A JPS59161070A (en) | 1983-03-04 | 1983-03-04 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59161070A true JPS59161070A (en) | 1984-09-11 |
Family
ID=12413909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3442783A Pending JPS59161070A (en) | 1983-03-04 | 1983-03-04 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59161070A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02130834A (en) * | 1988-11-10 | 1990-05-18 | Nec Yamagata Ltd | Manufacture of semiconductor integrated circuit device |
| JPH03278576A (en) * | 1990-03-28 | 1991-12-10 | Nippon Precision Circuits Kk | Manufacture of mos transistor |
-
1983
- 1983-03-04 JP JP3442783A patent/JPS59161070A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02130834A (en) * | 1988-11-10 | 1990-05-18 | Nec Yamagata Ltd | Manufacture of semiconductor integrated circuit device |
| JPH03278576A (en) * | 1990-03-28 | 1991-12-10 | Nippon Precision Circuits Kk | Manufacture of mos transistor |
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