JPS5815278A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5815278A JPS5815278A JP11471881A JP11471881A JPS5815278A JP S5815278 A JPS5815278 A JP S5815278A JP 11471881 A JP11471881 A JP 11471881A JP 11471881 A JP11471881 A JP 11471881A JP S5815278 A JPS5815278 A JP S5815278A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- insulating film
- insulating
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 3
- 239000002184 metal Substances 0.000 claims abstract description 3
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 230000003647 oxidation Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 239000000126 substance Substances 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract 1
- 239000012808 vapor phase Substances 0.000 abstract 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 5
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、特にシリコンゲ
ートＭＯ８ＦＥＴのソース及ヒトレイン電極のコンタク
ト窓の自己整合法による開口方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for opening contact windows of source and drain electrodes of a silicon gate MO8FET using a self-alignment method.
半導体装置を高集積化するため、その構成要素の各素子
がますます微細化され、高集積化される現況下にあって
、ＭＯＳ ＦＥＴのソース及びドレイン電極のコンタク
ト窓を開口する工程における位置合わせ余裕を不要化す
ることが重要な課題となっている。特にＭＯＳ ＦＥＴ
を短チヤネル化する場合には、この位置合わせ余裕を排
除することが素子の微細化にとって不可欠の要件となる
。In order to increase the integration of semiconductor devices, each component element is becoming increasingly finer and more integrated, so alignment in the process of opening contact windows for the source and drain electrodes of MOS FETs is becoming increasingly important. Eliminating the need for margins has become an important issue. Especially MOS FET
When shortening the channel, eliminating this alignment margin is an essential requirement for device miniaturization.
そのため上記コンタクト窓を開口する際の位置合せ余裕
を不要化するための製造方法が種々提唱されているが、
いずれも十分に満足し得るものとは言い難い。Therefore, various manufacturing methods have been proposed to eliminate the need for alignment margin when opening the contact window.
It is hard to say that either of them is fully satisfactory.
本発明の目的ばソース及びドレイン電極のコンタクト窓
をゲート電極と自己整合して形成し得る半導体装置の製
造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device in which contact windows for source and drain electrodes can be formed in self-alignment with gate electrodes.
本発明の特徴は、半導体基板表面に形成された素子間絶
縁分離領域により画定された素子形成領域に、上面を厚
い第１の絶縁膜で被覆されたシリコンまたは金属の硅化
物よりなるゲート電極を形成し、該ゲート電極表面及び
素子形成領域表面に薄い第２の絶縁膜を形成し、次いで
プラズマ化学気相成長法により基板上全面に第８の絶縁
膜を形成し、次いで該第８の絶縁膜のうち前記ゲート電
極の側壁面に付着せる部分の被エツチレートが大である
ことを利用してこれを除去し、次いで残留せる第８の絶
縁膜をマスクとして酸化処理を施こして前記ゲート電極
側壁面に厚い酸化膜を形成した後、曲起第８の絶縁膜と
その下層の薄い第２の絶縁膜を除去することにより、ソ
ース及びドレイン電極のコンタクト窓、を開口する工程
を含むことにある。A feature of the present invention is that a gate electrode made of silicon or metal silicide whose upper surface is covered with a thick first insulating film is provided in an element formation region defined by an inter-element insulation isolation region formed on the surface of a semiconductor substrate. a thin second insulating film is formed on the surface of the gate electrode and the surface of the element formation region, then an eighth insulating film is formed on the entire surface of the substrate by plasma chemical vapor deposition; Taking advantage of the fact that the portion of the film to be attached to the side wall surface of the gate electrode is highly etched, this is removed, and then an oxidation treatment is performed using the remaining eighth insulating film as a mask to form the gate electrode. After forming a thick oxide film on the side wall surface, the method includes a step of opening contact windows for the source and drain electrodes by removing the curved eighth insulating film and the thin second insulating film thereunder. be.
以下本発明の一実施例を図面を用いて説明する。An embodiment of the present invention will be described below with reference to the drawings.
第１図〜第８図は本発明め一実施例をその製造工程の順
に説明する要部断面図である。第１図において１はシリ
コン（８１）基板、２は選択酸化法に工って形成したフ
ィールド酸化膜、８はフィールド酸化膜によシ画定され
た素子形成領域、４はゲート酸化膜、５は例えばシリコ
ン多結晶よりなるゲート電極、６はゲー）［極５の上面
を被覆する第１の絶縁膜で、本実施例では二酸化シリコ
ン（Ｓ’ｚＯｇ ）膜を用いた。FIGS. 1 to 8 are sectional views of essential parts for explaining a first embodiment of the present invention in the order of its manufacturing process. In FIG. 1, 1 is a silicon (81) substrate, 2 is a field oxide film formed by a selective oxidation method, 8 is an element formation region defined by the field oxide film, 4 is a gate oxide film, and 5 is a gate oxide film. For example, a gate electrode made of polycrystalline silicon (6 is a gate electrode) [a first insulating film covering the upper surface of the electrode 5, and in this embodiment, a silicon dioxide (S'zOg) film was used.
ここまでは通常の製造工程に従って進めてよい。Up to this point, the process may proceed according to the normal manufacturing process.
即ち、８１基板１表面にフィールド酸化膜２を形成し、
素子形成領域８表面を一旦露出させ、次いで素子形成領
域８表面に加熱酸化法により約５００［人コの厚さのゲ
ート酸化膜４を形成し、その上に化学気相成長（ＣｖＤ
）法によりシリコン多結晶層６を成長させ、更にこれを
酸化する等の方法で第１のＳｉＯ２膜６を凡そ３０００
〜４０００［：Ａコの厚さに形成した後、パターニング
工程を経て、同図に示すようにゲート酸化膜４．ゲー）
ｆｉ４ｉ（厚さ凡そ４０００〜５０００［入コ）、第１
の５ｉｎ２膜６が形成される。That is, a field oxide film 2 is formed on the surface of the 81 substrate 1,
The surface of the element formation region 8 is once exposed, and then a gate oxide film 4 with a thickness of approximately 500 mm is formed on the surface of the element formation region 8 by a thermal oxidation method, and chemical vapor deposition (CvD) is applied thereon.
) method to grow a silicon polycrystalline layer 6, and further oxidize it to form a first SiO2 film 6 with a thickness of about 3,000 yen.
After forming the gate oxide film to a thickness of ~4000[:A], a patterning process is performed to form a gate oxide film 4. game)
fi4i (thickness approximately 4000 to 5000 [included]), 1st
A 5in2 film 6 is formed.
次いでこれに加熱酸化処理を施こして第２図に見られる
ように、素子形成領域８表面並びにゲート電砺５側面を
酸化して、１００〜５００［人］の厚さの第２のＳｉｎ
、膜７，８を形成する。Next, a heat oxidation treatment is performed on this to oxidize the surface of the element forming region 8 and the side surface of the gate wire 5, as shown in FIG.
, forming films 7 and 8.
次いでプラズマＣＶＤ法により第８図に示す如く基板１
上全面に窺化シリコン（５ｉａＮ、 ） ｆｉｌｌ （
第８の絶縁膜）９を５００〜ａｏｏｏｃ人］の厚さに形
成する。このようにプラズマＣＶＤ法によシ皮膜を形成
した場合には、ゲート電極６の側壁面のように直立面な
いしは直立に近い面に被着した部分ｄの膜質が非常に粗
となり、そのため平坦部に被着した膜に較べて薬品に対
する被エツチレートが著しく増大する。Next, as shown in FIG. 8, the substrate 1 is formed by plasma CVD method.
Vitrified silicon (5iaN, ) fill (
An eighth insulating film) 9 is formed to a thickness of 500 to 500 cm. When a film is formed by the plasma CVD method in this way, the quality of the film on the portion d deposited on an upright surface or a nearly upright surface such as the side wall surface of the gate electrode 6 becomes very rough, and therefore, the film quality on the flat portions becomes very rough. The etch rate for chemicals is significantly increased compared to the film deposited on the substrate.
そこで８１基板１を例えば濃度２［％コ程度に希釈した
弗酸（ＨＦ）溶液で処理すると、第４図に示すように８
１８Ｎ４＠９のうちゲート電極６の側壁面に被着された
部分９′のみが速やかに除去され、その下層の第２の５
１０２ ＠ ８が露呈する。この工程において、上記ゲ
ート電極５の側壁面以外に被着せる５１３Ｎ４膜９や第
２の５ｉ０９膜８は、上述の２、 ［５週度のＨＦ溶液
では殆んどおかされない。Therefore, when the 81 substrate 1 is treated with a hydrofluoric acid (HF) solution diluted to a concentration of about 2%, the 81
Of the 18N4@9, only the portion 9' adhered to the side wall surface of the gate electrode 6 is quickly removed, and the second layer 9' below it is removed.
102 @8 is exposed. In this step, the 513N4 film 9 and the second 5i09 film 8, which are deposited on areas other than the side wall surfaces of the gate electrode 5, are hardly damaged by the HF solution for 5 weeks as described above.
次いで上記残留せる５ｉａＮ４膜９をマスクとじて８１
基板ｌに加熱酸化処理を施こす。すると周知の如（Ｓｉ
３Ｎ４ｇ１１９に被覆されている部分ではＳｉ、０２膜
は成長せず、Ｓｉ３Ｎ４膜の存在しない部分ではＳｌの
酸化が進行して８１０Ｂ膜が成長する。従って第５図に
示すようにゲート電極５の側壁面の第２の５ｉ０２膜８
は厚さを増大する。その厚さは実用ト２０００〜４００
０［人コ程度に制御する。Next, the remaining 5iaN4 film 9 is removed as a mask 81.
A heating oxidation treatment is performed on the substrate l. Then, as is well known (Si
In the portion covered with 3N4g119, the Si, 02 film does not grow, and in the portion where the Si3N4 film does not exist, oxidation of Sl progresses and an 810B film grows. Therefore, as shown in FIG.
increases the thickness. Its thickness is practically 2000~400mm
0 [Control to human level.
次いで第６図に示すように燐酸（Ｈ３Ｐ０． ）等によ
り残留せる５ｊ−１１Ｎ４１１９を除去し、更にＨＦ糸
の薬品により基板１表面の薄い第２の５１０２膜７を除
去する。このときゲート電極６の上面及び側壁面のＳｉ
、Ｏ，ｆｉ６．８もおかされるが、前述の除去すべきＳ
ｉｎｇ膜７より遥かに厚いので、若干厚さを減じるがす
べて除去されることはない。Next, as shown in FIG. 6, the remaining 5j-11N4119 is removed using phosphoric acid (H3P0.) or the like, and the thin second 5102 film 7 on the surface of the substrate 1 is further removed using HF thread chemicals. At this time, Si on the upper surface and side wall surface of the gate electrode 6
, O, fi6.8 is also affected, but the above-mentioned S to be removed
Since it is much thicker than the ing film 7, the thickness is slightly reduced but not completely removed.
以上によりソース及びドレイン領域のコンタクト窓ｔｏ
、ｔｔが形成されたのであるがＳこのコンタク）窒１０
．・１１の位置はゲート［極５と自己整合して決定され
、位置決めのためのホト工程を使用していない。従って
コンタク）窓１０．１１を開口するための位置合わせ余
裕を設ける必要がなくなり、素子が微細化される。。As described above, the contact window to of the source and drain regions is
, tt was formed, but this contact) nitrogen 10
．． - The position of 11 is determined by self-alignment with the gate [pole 5, and no photo process is used for positioning. Therefore, there is no need to provide a positioning margin for opening the contact windows 10, 11, and the element can be miniaturized. .
このあとは通常の製造工程に従って進めてよく、即ち、
第７図に示すようにコンタクト窓１０．１１部にイオン
注入法或いは拡散法によシ所望の不純物［例えばｎチャ
ネル素子の場合には砒素（Ａｓ）。After this, you may proceed according to the normal manufacturing process, i.e.
As shown in FIG. 7, contact windows 10 and 11 are doped with a desired impurity (for example, arsenic (As) in the case of an n-channel device) by ion implantation or diffusion.
燐（Ｐ）コを導入してソース及びドレイン領域１２゜１
８を形成し、更に第８図に示すようにアルミニウム（Ａ
ｌ）のような導電材料よりなるソース及びドレインの電
極配線１４．１５を形成して本実施例によるＭＯＳ Ｆ
ＥＴの完成体が得られる。By introducing phosphorus (P), the source and drain regions 12°1
8, and as shown in FIG.
The MOS F according to this embodiment is formed by forming source and drain electrode wirings 14 and 15 made of a conductive material such as l).
A complete ET is obtained.
なおソース及びドレイン領域１２．１８は上記一実施例
の如く、コンタクト窓ｔｏ、ｔｔを開口した後に形成し
てもよく、前記第１図或いは第２図により説明した工程
のあとイオン注入法により形成してもよい。Note that the source and drain regions 12.18 may be formed after opening the contact windows to and tt as in the above embodiment, and may be formed by ion implantation after the steps explained in FIG. 1 or 2. You may.
以上説明した如く本発明によれば、ソース及びドレイン
領域のコンタクト窓をゲート電極と自己整合して形成し
得るので、位置合わせ余裕を設ける必要がない。従って
半導体装置の微細化、高密度化が容易となる。As described above, according to the present invention, the contact windows of the source and drain regions can be formed in self-alignment with the gate electrode, so there is no need to provide alignment margin. Therefore, it becomes easy to miniaturize and increase the density of semiconductor devices.
第１図〜第８図は本発明の一実施例を製造工程の順に示
す要部断面図であって、図中、ｌは半導体基板、２は素
子間絶縁分離領域、８は素子形成領域、４はゲート絶縁
膜、５はゲート電極、６は第１の絶縁膜、７．８は第２
の絶縁膜、９．９′は第８の絶縁膜、ｔｏ、ｔｔはソー
ス及びドレイン電極のコンタクト窓を示す。1 to 8 are cross-sectional views of main parts of an embodiment of the present invention showing the manufacturing process in order, in which l is a semiconductor substrate, 2 is an inter-element isolation region, 8 is an element formation region, 4 is a gate insulating film, 5 is a gate electrode, 6 is a first insulating film, and 7.8 is a second insulating film.
9.9' is an eighth insulating film, to and tt are contact windows for source and drain electrodes.
Claims (1)
離領域を形成する工程と、前記素子形成領域表面の所定
部分にゲート絶縁膜を介してｙｙコンまえは金属の硅化
物よりなるゲート電極とその上に第１の絶縁膜を形成す
る工程と、前記素子形成領域表面の残りの部分及び前記
ゲート電極の側面に第２の絶縁膜を形成する工程と、前
記ゲート電極上面部及び側面部を含む半導体基板上にプ
ラズマ化学気相成長法により第８の絶縁膜を形成する工
程と、前記ゲート電極側面部に被着せる第８の絶縁膜を
除去する工程と、残留せる前記第８の絶縁膜をマスクと
して半導体基板に酸化処理を施こすことにより前記ゲー
ト電極側面部にシリコンの酸化膜を成長せしめる工程と
前記第８及び第２の絶縁膜を除去する工程とを含むこと
を特徴とする半導体装置の製造方法。A step of forming an inter-element insulation isolation region for defining an element formation region on the surface of the semiconductor substrate, and forming a gate electrode made of metal silicide on a predetermined portion of the surface of the element formation region with a gate insulating film in front of the yy cone. forming a first insulating film on the surface of the element formation region and forming a second insulating film on the remaining portion of the surface of the element formation region and the side surfaces of the gate electrode; a step of forming an eighth insulating film on a semiconductor substrate by plasma chemical vapor deposition; a step of removing the eighth insulating film deposited on the side surface of the gate electrode; and a step of removing the eighth insulating film to remain. A semiconductor device comprising the steps of: growing a silicon oxide film on the side surface of the gate electrode by oxidizing the semiconductor substrate as a mask; and removing the eighth and second insulating films. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11471881A JPS5815278A (en) | 1981-07-21 | 1981-07-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11471881A JPS5815278A (en) | 1981-07-21 | 1981-07-21 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5815278A true JPS5815278A (en) | 1983-01-28 |
| JPH0217931B2 JPH0217931B2 (en) | 1990-04-24 |
Family
ID=14644875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11471881A Granted JPS5815278A (en) | 1981-07-21 | 1981-07-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5815278A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6068612A (en) * | 1983-09-26 | 1985-04-19 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
| FR2720331A1 (en) * | 1994-05-27 | 1995-12-01 | Ier | Printing machine with moving guide for material to be printed |
-
1981
- 1981-07-21 JP JP11471881A patent/JPS5815278A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6068612A (en) * | 1983-09-26 | 1985-04-19 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
| FR2720331A1 (en) * | 1994-05-27 | 1995-12-01 | Ier | Printing machine with moving guide for material to be printed |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0217931B2 (en) | 1990-04-24 |
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