GB2172743A - Forming gate sidewall oxide spacers - Google Patents
Forming gate sidewall oxide spacers Download PDFInfo
- Publication number
- GB2172743A GB2172743A GB08507600A GB8507600A GB2172743A GB 2172743 A GB2172743 A GB 2172743A GB 08507600 A GB08507600 A GB 08507600A GB 8507600 A GB8507600 A GB 8507600A GB 2172743 A GB2172743 A GB 2172743A
- Authority
- GB
- United Kingdom
- Prior art keywords
- mesa
- forming gate
- polysilicon
- drain regions
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 125000006850 spacer group Chemical group 0.000 title claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 17
- 239000007943 implant Substances 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 abstract description 7
- 238000002513 implantation Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- RFCAUADVODFSLZ-UHFFFAOYSA-N 1-Chloro-1,1,2,2,2-pentafluoroethane Chemical compound FC(F)(F)C(F)(F)Cl RFCAUADVODFSLZ-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- PAOKWJHEAWZUNI-UHFFFAOYSA-N [F].[F].[F].[F].[F].[F].[S] Chemical compound [F].[F].[F].[F].[F].[F].[S] PAOKWJHEAWZUNI-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 235000019406 chloropentafluoroethane Nutrition 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910021352 titanium disilicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Inorganic Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A layer of polysilicon capped with silicon nitride is anisotropically etched to form the gate of a transistor. The structure is heated in an oxidising atmosphere to oxidise only the side walls (16) of the mesa (13). The nitride cap (14) can be used as an implantation mask for forming source and drain regions (51,52). <IMAGE>
Description
SPECIFICATION
Improvements in integrated circuits
This invention relates to integrated circuits and in particular to methods of forming sidewall oxide spacers in such circuits.
As the dimensions of conventional CMOS circuits are reduced in an attempt to achieve a high degree of integration, the resistivity of the source-drain and polysilicon gate interconnects becomes a significant factor in limiting the circuit speed. One method of overcoming this constraint and improving the circuit speed is to shunt the polysilicon with a refractory metal silicide. If however the source and drain are to be silicided to obtain the full benefit of this technique then it is necessary to provide an insulating sidewall spacer on the silicon gate to prevent gate-drain shots. Conventionally this sidewall spacer is produced by anisotropic etching of a deposited silicon oxide layer. This process is somewhat difficult to control and can result in a reduction in yield.
The object of the present invention is to minimise or to overcome this disadvantage.
According to the invention there is provided a process for forming gate oxide sidewall spacers in an integrated circuit, the process including providing a silicon nitride capped polysilicon mesa on an oxide film on a semiconductor substrate, and oxidising the side walls of the mesa.
Advantageously the oxidation is performed at a temperature below 900 C.
An advantage of this technique is the masking effect of the nitride cap during implantation. Transmission of boron through the gate and into the underlying substrate is a problem with many CMOS processes since it affects the device terminal characteristics. Conventionally this is avoided by the use of a boron difluoride implant but defects generated in the active area by fluorine may then be a problem.
Use of nitride cap on polysilicon allows the use of a boron implant with the unwanted boron being stopped in the nitride above the gate.
An embodiment of the invention will now be described with reference to the accompanying drawings in which Figs. 1 to 7 show successive stages in the fabrication of a field effect transistor structure.
Referring to the drawings, a clean polished silicon wafer 11 (Fig. 1) is provided with a surface oxide film 12 on which a polysilicon layer 13 is deposited. Typically the polysilicon 13 is doped to reduced its resistivity. Doping can be effected during the deposition process or, subsequently, by ion implantation.
After deposition and doping of the polysilicon layer 13 a thin layer, typically 40 to 60nm, of silicon nitride 14 (Fig. 2) is deposited thereon. This can be effected by plasma deposition process. A photolithographic mask 15 is then applied to define the gate region of the device. The composite silicon nitride/polysilicon structure is etched anisotropically in a plasma or reactive ion etching system. For this purpose we prefer to employ a mixture of sulphur hexafluorine and FREON 115 (registered Trade Mark). The purpose of the etch is to remove the unmasked nitride and polysilicon with substantially no undercut, to leave a 'mesa' structure as shown in Fig. 3.
The photoresist mask 15 is next removed and a low dose ion implant, e.g. of boron or arsenic, may be performed using the silicon nitride cap as a mask to form doped regions 41, 42 (Fig. 4). This implant may be omitted if the light doped drain option is not required.
The assembly is then heated in an oxidising atmosphere to provide oxide sidewalls 16 (Fig. 4) on the remaining polysilicon 13. No oxide grows on the nitride capped surface of the polysilicon. To take full advantage of the differential oxidation ratio of polysilicon and single crystal silicon we prefer to employ a relatively low oxidation temperature typically below 900 C.
After oxidation has been completed a second implant of high dose and energy may be performed to define the source and drain regions 51 and 52 (Fig. 5) of the device. The nitride is again used to stop penetration of dopants into the polysilicon gate. The source and drain regions are thus self aligned with the gate. The silicon nitride layer 14 is removed with a suitable etch to form the structure of Fig. 6. The device may then be further processed by conventional techniques e.g. to form the completed SALICIDE structure shown in Fig. 7. Typically the source drain oxide is removed in hydrofluoric acid. This exposes silicon on the source drain region and on the polysilicon gate. A thin layer of titanium is deposited and reacted with the silicon by a suitable heat treatment. Titanium disilicide 71 forms where the metal contacts the silicon but no reaction occurs on the oxide regions. The unreacted titanium is then removed with a selective etch. This leaves the SALACIDE structure shown in Fig. 7.
Claims (8)
1. A process for forming gate oxide sidewall spacers in an integrated circuit, the process including providing a silicon nitride capped polysilicon mesa on an oxide film on a semiconductor substrate, and oxidising the side walls of the mesa.
2. A process as claimed in claim 1, wherein the mesa walls are oxidised at a temperature below 900 C.
3. A process as claimed in claim 1 or 2, wherein the mesa is formed by selective anisotropic gas phase etching.
A process as claimed in claim 1, 2 or 3, wherein the capped mesa provides a mask whereby source and drain regions are ion im planted.
5. A process as claimed in claim 4, wherein said source drain regions are implanted with boron.
6. A process as claimed in claim 5, wherein said regions each comprise a first low energy implant and a second high energy implant.
7. A process for forming gate oxide sidewall spacers substantially as described herein with reference to the accompanying drawings.
8. An integrated circuit fabricated by a process as claimed in any one of the preceding claims.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08507600A GB2172743B (en) | 1985-03-23 | 1985-03-23 | Improvements in integrated circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08507600A GB2172743B (en) | 1985-03-23 | 1985-03-23 | Improvements in integrated circuits |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8507600D0 GB8507600D0 (en) | 1985-05-01 |
| GB2172743A true GB2172743A (en) | 1986-09-24 |
| GB2172743B GB2172743B (en) | 1988-11-16 |
Family
ID=10576522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08507600A Expired GB2172743B (en) | 1985-03-23 | 1985-03-23 | Improvements in integrated circuits |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2172743B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0327152A1 (en) * | 1988-01-29 | 1989-08-09 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device, in which metal silicide is provided in a self-registered manner |
| EP0524499A1 (en) * | 1991-07-11 | 1993-01-27 | Canon Kabushiki Kaisha | Method for forming a photomask pattern |
| EP0592039A2 (en) * | 1992-10-07 | 1994-04-13 | Koninklijke Philips Electronics N.V. | Method of manufacturing an integrated circuit with a non-volatile memory element |
| WO1999017351A1 (en) * | 1997-09-30 | 1999-04-08 | Infineon Technologies Ag | Reduction of gate-induced drain leakage in semiconductor devices |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1477083A (en) * | 1974-12-03 | 1977-06-22 | Ibm | Insulated gate field effect transistors |
| US4085498A (en) * | 1976-02-09 | 1978-04-25 | International Business Machines Corporation | Fabrication of integrated circuits containing enhancement-mode FETs and depletion-mode FETs with two layers of polycrystalline silicon utilizing five basic pattern delineating steps |
| US4411929A (en) * | 1980-08-19 | 1983-10-25 | Mitsubishi Denki Kabushiki Kaisha Lsi Development Laboratory | Method for manufacturing semiconductor device |
| EP0098652A2 (en) * | 1982-07-05 | 1984-01-18 | Koninklijke Philips Electronics N.V. | Method of manufacturing an insulated gate field effect device and device manufactured by the method |
-
1985
- 1985-03-23 GB GB08507600A patent/GB2172743B/en not_active Expired
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1477083A (en) * | 1974-12-03 | 1977-06-22 | Ibm | Insulated gate field effect transistors |
| US4085498A (en) * | 1976-02-09 | 1978-04-25 | International Business Machines Corporation | Fabrication of integrated circuits containing enhancement-mode FETs and depletion-mode FETs with two layers of polycrystalline silicon utilizing five basic pattern delineating steps |
| US4411929A (en) * | 1980-08-19 | 1983-10-25 | Mitsubishi Denki Kabushiki Kaisha Lsi Development Laboratory | Method for manufacturing semiconductor device |
| EP0098652A2 (en) * | 1982-07-05 | 1984-01-18 | Koninklijke Philips Electronics N.V. | Method of manufacturing an insulated gate field effect device and device manufactured by the method |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0327152A1 (en) * | 1988-01-29 | 1989-08-09 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device, in which metal silicide is provided in a self-registered manner |
| EP0524499A1 (en) * | 1991-07-11 | 1993-01-27 | Canon Kabushiki Kaisha | Method for forming a photomask pattern |
| US5472812A (en) * | 1991-07-11 | 1995-12-05 | Canon Kabushiki Kaisha | Method for forming a photomask pattern |
| EP0592039A2 (en) * | 1992-10-07 | 1994-04-13 | Koninklijke Philips Electronics N.V. | Method of manufacturing an integrated circuit with a non-volatile memory element |
| EP0592039A3 (en) * | 1992-10-07 | 1994-07-06 | Koninkl Philips Electronics Nv | Method of manufacturing an integrated circuit with a non-volatile memory element |
| WO1999017351A1 (en) * | 1997-09-30 | 1999-04-08 | Infineon Technologies Ag | Reduction of gate-induced drain leakage in semiconductor devices |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2172743B (en) | 1988-11-16 |
| GB8507600D0 (en) | 1985-05-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
| 732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20030323 |