JPH02218164A - Mis type field-effect transistor - Google Patents
Mis type field-effect transistorInfo
- Publication number
- JPH02218164A JPH02218164A JP3864289A JP3864289A JPH02218164A JP H02218164 A JPH02218164 A JP H02218164A JP 3864289 A JP3864289 A JP 3864289A JP 3864289 A JP3864289 A JP 3864289A JP H02218164 A JPH02218164 A JP H02218164A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- silicon
- silicon nitride
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 14
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 238000002844 melting Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 230000008018 melting Effects 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 10
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 5
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 5
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 description 16
- 239000012535 impurity Substances 0.000 description 12
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 108091006146 Channels Proteins 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- -1 phosphorus ions Chemical class 0.000 description 3
- 230000005284 excitation Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 241000234435 Lilium Species 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 244000089486 Phragmites australis subsp australis Species 0.000 description 1
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は高速化、高密度化が要求されている半導体集積
回路（以下、ＭＯＳ−ＬＳＩと記す）において、微細化
されたＭＩＳ型電界効果トランジスタ（以下、ＭＩＳ型
トランジスタと記す）に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applied to miniaturized MIS field effect transistors (hereinafter referred to as MOS-LSI) in semiconductor integrated circuits (hereinafter referred to as MOS-LSI) that are required to have higher speed and higher density. (hereinafter referred to as MIS type transistor).
従来の技術
近年、ＭＩＳ型トランジスタは高速化、高密度化など高
性能化の要求が強まっ°てきている。ＭＯＳ・ＬＳＩの
高性能化に最も有効な手法の１つはスケーリング則に従
った微細化である。一方、高速化に対応する技術として
、多結晶シリコン膜の上に高融点金属とシリコンとの二
元素系膜（シリサイド膜）を積層した２層構造のゲート
電極、即ちポリサイド・ゲート構造が挙げられる。BACKGROUND OF THE INVENTION In recent years, there has been an increasing demand for higher performance MIS transistors such as higher speeds and higher densities. One of the most effective methods for improving the performance of MOS/LSI is miniaturization according to scaling laws. On the other hand, as a technology that can support higher speeds, there is a two-layer gate electrode structure in which a two-element film (silicide film) of a high melting point metal and silicon is laminated on a polycrystalline silicon film, that is, a polycide gate structure. .
発明が解決しようとする課題
このポリサイド・ゲートの技術的課題として、■） シ
リサイド膜自体の応力の方向は引張り張力であり、シリ
コンの含有率が低（なったり、熱処理が加わったりする
と特に顕著となる。この結果、下地の多結晶ポリシリコ
ン膜と密着不良を起こし、はがれ現象が発生する。Problems to be Solved by the Invention The technical problems with this polycide gate are as follows: ■) The direction of stress in the silicide film itself is tensile stress, which becomes especially noticeable when the silicon content is low (or when heat treatment is applied). As a result, poor adhesion with the underlying polycrystalline silicon film occurs, resulting in a peeling phenomenon.
２） シリサイド膜は酸化を含めた熱処理に弱い。2) Silicide films are susceptible to heat treatment including oxidation.
この結果、微細化に必要なＬＤＤ （ＬｉｇｈｔｙＤｏ
ｐｅｄ Ｄｒａｉｎ）構造のＭＩＳ型トランジスタに
適用しようとすると、最低２回の熱酸化工程が必要とな
るが、２回目の酸化工程でゲート電極側面にサイドウオ
ール用の酸化シリコン膜を形成するとき、シリサイド膜
が表面に露出しているためシリサイド膜が異常酸化を起
こし、パターン破壊が発生する。As a result, the LDD (LightyDo
If it is applied to a MIS type transistor with a ped drain) structure, at least two thermal oxidation steps are required, but when forming a silicon oxide film for sidewalls on the side surface of the gate electrode in the second oxidation step, silicide Since the film is exposed on the surface, abnormal oxidation of the silicide film occurs, resulting in pattern destruction.
本発明は、前述の如くポリサイド・ゲートのはがれや異
常酸化現象をより簡便で低コストな手法を用いて解決す
るポリサイド・ゲート構造のＭＩＳ型トランジスタを提
供することを目的とするものである。An object of the present invention is to provide an MIS transistor having a polycide gate structure, which solves the problem of polycide gate peeling and abnormal oxidation using a simpler and lower cost method, as described above.
課題を解決するための手段
本発明のＭＩＳ型トランジスタは、−導電型の半導体基
板表面に選択的に形成されたゲート絶縁膜と、同ゲート
絶縁膜の上に、導電性の多結晶シリコン膜と、高融点金
属とシリコンとの二元素系からなるシリサイド膜とが順
次積層されたゲート電極と、同ゲート電極の上に形成さ
れた窒化シリコン膜、および前記半導体基板の所定領域
に形成されたソース領域とドレイン領域とを葦えたちの
である。Means for Solving the Problems The MIS transistor of the present invention includes a gate insulating film selectively formed on the surface of a -conductive type semiconductor substrate, and a conductive polycrystalline silicon film on the gate insulating film. , a gate electrode in which a silicide film made of a two-element system of high-melting point metal and silicon are sequentially stacked, a silicon nitride film formed on the gate electrode, and a source formed in a predetermined region of the semiconductor substrate. The area and the drain area are reeds.
作用
シリサイド膜はシリコンの含有率が低い場合および熱処
理が加えられて行くに従い、引張り方向の張力が増加す
る。一方、プラズマ励起によるＣＶＤ法で形成された窒
化シリコン膜は圧縮方向の応力が働く。In the active silicide film, the tension in the tensile direction increases as the silicon content decreases and as heat treatment is applied. On the other hand, stress in the compressive direction acts on a silicon nitride film formed by a CVD method using plasma excitation.
本発明では、この２つの生成膜を直接接触させ、それぞ
れ逆方向のストレスを緩和させることで、ゲート電極形
成以後のはがれ現象を防止することができる。In the present invention, by bringing these two produced films into direct contact and relieving stress in opposite directions, it is possible to prevent the peeling phenomenon after the formation of the gate electrode.
さらに、ＬＤＤ構造を適用した場合、本発明では、ゲー
ト電極となるシリサイド膜の上に窒化シリコン膜が形成
されているため、ゲート電極の側面にサイドウオール用
の酸化シリコン膜を形成してもシリサイド膜が異常酸化
することがなくなる。Furthermore, when an LDD structure is applied, in the present invention, the silicon nitride film is formed on the silicide film that becomes the gate electrode, so even if a silicon oxide film for sidewalls is formed on the side surface of the gate electrode, the silicide Abnormal oxidation of the film is eliminated.
実施例
本発明のＭＩＳ型トランジスタの実施例を図面を用いて
説明する。Embodiment An embodiment of the MIS type transistor of the present invention will be described with reference to the drawings.
第１図は、ゲート寸法１．２μｍのＬＤＤ構造のＮチャ
ンネルＭＯ３型トランジスタに、本発明を適用した場合
の断面図である。これは、Ｐ型シリコン基板１の上に選
択的にＰウェル拡散層２が形成され、ＬＯＣＯ８酸化法
によりＰ型シリコン基板１の表面に選択的に厚膜の分離
酸化膜（以後ＬＯＣＯ３酸化膜３と記す）が、この下に
Ｐ型のチャンネルストッパ領域４が形成され、ＬＯＧＯ
３酸化膜３に囲まれたＰウェル拡散層２の表面の中央に
ゲート酸化膜５が形成され、ゲート酸化膜５の上に多結
晶シリコン膜６とタングステンシリサイド１１１７によ
るゲート電極と、窒化シリコン膜８が順次積層され、ゲ
ート電極の側面にサイドウオール用の酸化シリコン膜９
が形成され、サイドウオール用の酸化シリコン膜９の下
のＰウェル拡散層２の中に低不純物濃度のＮ型拡散層１
０と１０１が、これに接続してゲート酸化膜５とサイド
ウオール用の酸化シリコン膜９およびＬＯＧＯ５酸化膜
３以外のＰウェル拡散層２に高不純物濃度のＮ型拡散層
１１と１１１が形成された構造である。窒化シリコン膜
８はポリサイドゲート電極の上部表面のみを覆っている
。なお、高不純物濃度のＮ型拡散層１１と１１１におい
て、一方がソース領域のとき、他方がドレイン領域とな
る。FIG. 1 is a sectional view when the present invention is applied to an N-channel MO3 type transistor having an LDD structure with a gate size of 1.2 μm. A P-well diffusion layer 2 is selectively formed on a P-type silicon substrate 1, and a thick isolation oxide film (hereinafter referred to as LOCO3 oxide film 3) is selectively formed on the surface of the P-type silicon substrate 1 using the LOCO8 oxidation method. ), a P-type channel stopper region 4 is formed below this, and LOGO
A gate oxide film 5 is formed at the center of the surface of the P-well diffusion layer 2 surrounded by the oxide film 3, and a gate electrode made of a polycrystalline silicon film 6 and tungsten silicide 1117 and a silicon nitride film are formed on the gate oxide film 5. 8 are sequentially laminated, and a silicon oxide film 9 for a sidewall is formed on the side surface of the gate electrode.
is formed, and an N-type diffusion layer 1 with a low impurity concentration is formed in the P-well diffusion layer 2 under the silicon oxide film 9 for the sidewall.
0 and 101 are connected to this, and N-type diffusion layers 11 and 111 with high impurity concentration are formed in the gate oxide film 5, the sidewall silicon oxide film 9, and the P-well diffusion layer 2 other than the LOGO 5 oxide film 3. It has a similar structure. Silicon nitride film 8 covers only the upper surface of the polycide gate electrode. Note that when one of the high impurity concentration N-type diffusion layers 11 and 111 is a source region, the other is a drain region.
次に、この構造を得るための製造方法を第２図に示した
工程断面図を参照して説明する。Next, a manufacturing method for obtaining this structure will be explained with reference to process cross-sectional views shown in FIG.
まず、抵抗率１０Ω・Ｃ１１程度のＰ型シリコン基板１
を用意する。この上にＰ型不純物（例えばボロン等）を
イオン注入し、この後熱拡散により、Ｐウェル拡散層２
を形成する。次に分離形成領域のみにＰ型のボロン不純
物をイオン注入し、チャンネル・ストッパ領域４を形成
する。その後、分離領域のみ選択的に酸化し、ＬＯＣＯ
３酸化Ｉｌ＊３を形成する（第２図ａ）。First, a P-type silicon substrate 1 with a resistivity of about 10Ω・C11
Prepare. P-type impurity (for example, boron, etc.) is ion-implanted onto this, and then thermal diffusion is applied to the P-well diffusion layer 2.
form. Next, P-type boron impurity ions are implanted only into the isolation formation region to form the channel stopper region 4. After that, only the isolation region is selectively oxidized, and the LOCO
Il trioxide*3 is formed (Figure 2a).
ＬＯＧＯ８酸化膜３以外の領域はＭＯ８型トランジスタ
の能動領域となる。この能動領域に、トランジスタのし
きい値電圧制御用としてＰ型の不純物（例えばボロン等
）をイオン注入し、チャンネル不純物層１２を形成する
。次に、Ｐウェル拡散層２の表面を酸化させてゲート酸
化膜５を形成し、続けて、ポリサイド・ゲートを構成す
る多結晶シリコン膜６を形成する。多結晶シリコン膜６
にトランジスタのしきい値電圧を制御するためとシリコ
ン自体の抵抗を下げるために、燐イオンをガス状態の中
で拡散させる。この時、生成される燐ガラス層を除去し
、前処理を施した後、減圧方式の気相成長（ＣＶＤ）に
より、タングステンシリサイド膜７を形成する。The area other than the LOGO8 oxide film 3 becomes the active area of the MO8 type transistor. P-type impurity (for example, boron, etc.) is ion-implanted into this active region to control the threshold voltage of the transistor, thereby forming a channel impurity layer 12. Next, the surface of the P-well diffusion layer 2 is oxidized to form a gate oxide film 5, and then a polycrystalline silicon film 6 constituting a polycide gate is formed. Polycrystalline silicon film 6
In order to control the threshold voltage of the transistor and to lower the resistance of silicon itself, phosphorus ions are diffused in a gaseous state. After removing the phosphorus glass layer produced at this time and performing a pretreatment, a tungsten silicide film 7 is formed by vacuum vapor deposition (CVD).
次に、プラズマ励起による気相成長で窒化シリコン膜８
を形成する（第２図ｂ）。Next, a silicon nitride film 8 is grown by vapor phase growth using plasma excitation.
(Figure 2b).
写真食刻法により形成されたフォトレジストをマスクに
して、Ｐ型シリコン基板１と垂直な形状を保つように、
窒化シリコン膜８とタングステンシリサイド膜７と多結
晶シリコン膜６およびゲート酸化膜５を化学的に順次除
去し、ゲート電極を形成する。こののち、ゲート電極を
マスクにして砒素イオンを注入して低不純物濃度のＮ型
拡散層１０と１０１を形成する。次に窒化シリコン膜８
をマスクとしてゲート電極の側面とＰウェル拡散層２の
表面に酸化シリコン膜を形成し、異方性ドライエツチン
グによりゲート電極の側面のみにサイドウオール用の酸
化シリコン膜９を残す（第２図Ｃ）。Using a photoresist formed by photolithography as a mask, the P-type silicon substrate 1 is kept perpendicular to the shape.
Silicon nitride film 8, tungsten silicide film 7, polycrystalline silicon film 6, and gate oxide film 5 are chemically removed in sequence to form a gate electrode. Thereafter, using the gate electrode as a mask, arsenic ions are implanted to form N-type diffusion layers 10 and 101 with low impurity concentration. Next, silicon nitride film 8
A silicon oxide film is formed on the side surfaces of the gate electrode and the surface of the P-well diffusion layer 2 using as a mask, and by anisotropic dry etching, the silicon oxide film 9 for sidewalls is left only on the side surfaces of the gate electrode (see Fig. 2C). ).
続いて、燐イオンを注入して、高不純物濃度のＮ型拡散
層１１と１１１を形成して、ＬＤＤ構造のＭＯ８型トラ
ンジスタを形成する（第１図）。Subsequently, phosphorus ions are implanted to form N-type diffusion layers 11 and 111 with high impurity concentration, thereby forming an MO8 type transistor with an LDD structure (FIG. 1).
なお、実施例ではゲート絶縁膜として酸化膜を用いたが
窒化膜でもよい。Note that in the embodiment, an oxide film was used as the gate insulating film, but a nitride film may also be used.
発明の効果
本発明のＭＴＳ型トランジスタによれば、ポリサイド・
ゲート電極の上部表面に窒化シリコンを被膜することに
より、シリサイド膜と窒化シリコン膜の応力を打ち消し
合ってゲート電極のはがれ現象を防止することができる
とともに、ＬＤＤ構造を用いた場合、ゲート電極の側面
にサイドウオール用の酸化シリコン膜を形成してもシリ
サイド膜が異常酸化されることがな（なり、信頼性を向
上させることができる。Effects of the Invention According to the MTS transistor of the present invention, polycide
By coating the upper surface of the gate electrode with silicon nitride, the stress of the silicide film and the silicon nitride film can be canceled out and the peeling phenomenon of the gate electrode can be prevented. Even if a silicon oxide film is formed for the sidewall, the silicide film will not be abnormally oxidized, and reliability can be improved.
第１図は本発明のＭＩＳ型トランジスタの実施例を示す
断面図、第２図は本発明のＭＩＳ型トランジスタの構造
を得るための製造方法を示す工程断面図である。
１・・・・・・Ｐ型シリコン基板、２・・・・・・Ｐウ
ェル拡散層、３・・・・・・ＬＯＣＯ３酸化膜、４・・
・・・・チャンネルストッパ領域、５・・・・・・ゲー
ト酸化膜、６・・・・・・多結晶シリコン膜、７・・・
・・・タングステンシリサイド嘩、８・・・・・・窒化
シリコン膜、９・・・・・・サイドウオール用の酸化シ
リコン膜、１０，１０１・・・・・・低不純物濃度のＮ
型拡散層、１１．１１１・・・・・・高不純物濃度のＮ
型拡散層、１２・・・・・・チャンネル不純物層。
代理人の氏名 弁理士 粟野重孝 ほか１名ｔ−Ｐ’ｔ
シリコーＪ基ｊ反
２−Ｐつｘ）Ｌ紘帽０脅
３−−− ＬＯｃｏｓ ｆｉｌｌ化ｌ１１１−−−今１
１ｉ−シリ］ソｌｌル
アー＃ソ７’Ｚテソ シリプ化月凭
８−−−窒化リリ１ソ川屹FIG. 1 is a cross-sectional view showing an embodiment of the MIS type transistor of the present invention, and FIG. 2 is a process cross-sectional view showing a manufacturing method for obtaining the structure of the MIS type transistor of the present invention. 1...P type silicon substrate, 2...P well diffusion layer, 3...LOCO3 oxide film, 4...
... Channel stopper region, 5 ... Gate oxide film, 6 ... Polycrystalline silicon film, 7 ...
...Tungsten silicide, 8...Silicon nitride film, 9...Silicon oxide film for sidewall, 10,101...Low impurity concentration N
Type diffusion layer, 11.111...N with high impurity concentration
Type diffusion layer, 12...Channel impurity layer. Name of agent: Patent attorney Shigetaka Awano and one other persont-P't
silicone
1i-Siri] Soll Lure #So7'Z Teso Shirippized Moonlight 8 --- Nitride Lily 1Sokawa
Claims (1)
絶縁膜と、同ゲート絶縁膜の上に、導電性の多結晶シリ
コン膜と、高融点金属とシリコンとの二元素系からなる
シリサイド膜とが順次積層されたゲート電極と、同ゲー
ト電極の上に形成された窒化シリコン膜、および前記半
導体基板の所定領域に形成されたソース領域とドレイン
領域とを備えたことを特徴とするＭＩＳ型電界効果トラ
ンジスタ。A gate insulating film selectively formed on the surface of a semiconductor substrate of one conductivity type, a conductive polycrystalline silicon film, and a silicide film made of a two-element system of high melting point metal and silicon on the gate insulating film. and a silicon nitride film formed on the gate electrode, and a source region and a drain region formed in predetermined regions of the semiconductor substrate. field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3864289A JPH02218164A (en) | 1989-02-17 | 1989-02-17 | Mis type field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3864289A JPH02218164A (en) | 1989-02-17 | 1989-02-17 | Mis type field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02218164A true JPH02218164A (en) | 1990-08-30 |
Family
ID=12530900
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3864289A Pending JPH02218164A (en) | 1989-02-17 | 1989-02-17 | Mis type field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02218164A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6346483B1 (en) | 1999-07-02 | 2002-02-12 | Sharp Kabushiki Kaisha | Film forming method and film formed by the method |
| US7452764B2 (en) * | 2003-06-12 | 2008-11-18 | Intel Corporation | Gate-induced strain for MOS performance improvement |
-
1989
- 1989-02-17 JP JP3864289A patent/JPH02218164A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6346483B1 (en) | 1999-07-02 | 2002-02-12 | Sharp Kabushiki Kaisha | Film forming method and film formed by the method |
| US7452764B2 (en) * | 2003-06-12 | 2008-11-18 | Intel Corporation | Gate-induced strain for MOS performance improvement |
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