JPH06151834A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH06151834A
JPH06151834A JP32870092A JP32870092A JPH06151834A JP H06151834 A JPH06151834 A JP H06151834A JP 32870092 A JP32870092 A JP 32870092A JP 32870092 A JP32870092 A JP 32870092A JP H06151834 A JPH06151834 A JP H06151834A
Authority
JP
Japan
Prior art keywords
film
polycrystalline silicon
thin film
silicon thin
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP32870092A
Other languages
Japanese (ja)
Inventor
Yasuo Sato
康夫 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP32870092A priority Critical patent/JPH06151834A/en
Publication of JPH06151834A publication Critical patent/JPH06151834A/en
Withdrawn legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To reduce damage to a substrate when forming the gate electrode of a MIS type transistor. CONSTITUTION:After a polycrystalline silicon thin film 3 is formed on a gate dielectric film 2, the surface of the first polycrystalline silicon thin film 3 is naturally oxidized and then a second polycrystalline silicon thin film 4 is formed on it. Then, after the second polycrystalline silicon thin film 4 is etched to the pattern of gate electrode, the first polycrystalline silicon thin film 3 at a part which is not covered with the second polycrystalline silicon thin film 4 is completely oxidized thermally. Therefore, even if the gate dielectric film 2 is extremely thin, the first polycrystalline silicon thin film 3 and a natural oxide film 9 on it contribute to etching control, thus reducing the etching damage to the substrate when forming the gate electrode.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、例えばMIS型半導体
装置の製造方法に係り、特に、ゲート電極のエッチング
時に半導体基板へのダメージを防止した半導体装置の製
造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MIS type semiconductor device, for example, and more particularly to a method of manufacturing a semiconductor device in which damage to a semiconductor substrate is prevented during etching of a gate electrode.

【0002】[0002]

【従来の技術】近年、MIS型トランジスタの微細化に
伴い、そのゲート酸化膜は、スケーリング則に従ってよ
り一層薄膜化する傾向にある。一例を挙げて説明すれ
ば、現在、研究開発レベルで検討されている0.1〜
0.4μm程度のゲート長を有するMIS型トランジス
タでは、そのゲート酸化膜厚は、40〜150Å程度ま
で薄膜化する必要がある。
2. Description of the Related Art In recent years, with the miniaturization of MIS transistors, the gate oxide film thereof tends to be further thinned according to the scaling rule. To give an example, 0.1-0.1 which is currently being considered at the research and development level
In a MIS transistor having a gate length of about 0.4 μm, it is necessary to reduce the gate oxide film thickness to about 40 to 150 Å.

【0003】[0003]

【発明が解決しようとする課題】従来技術の問題点を図
2を用いて説明する。
Problems of the prior art will be described with reference to FIG.

【0004】通常のMIS型トランジスタの製造方法に
従い、まず、図2(a)に示すように、例えばp型シリ
コン基板11上にゲート酸化膜12を、例えば水素と酸
素の燃焼による水蒸気雰囲気中で熱処理することによ
り、例えば80Åの膜厚に形成する。
According to a usual method for manufacturing a MIS type transistor, first, as shown in FIG. 2A, for example, a gate oxide film 12 is formed on a p-type silicon substrate 11 in a water vapor atmosphere by burning hydrogen and oxygen, for example. By heat treatment, for example, a film thickness of 80 Å is formed.

【0005】次に、図2(b)に示すように、多結晶シ
リコン薄膜14を、減圧CVD法により、例えば300
0Åの膜厚に形成する。この後、ホトリソグラフィ技術
により、ゲート電極を形成すべき部分にホトレジスト1
8を選択的に形成する。
Next, as shown in FIG. 2B, the polycrystalline silicon thin film 14 is formed, for example, by a low pressure CVD method, for example, 300.
It is formed to a film thickness of 0Å. After that, the photoresist 1 is formed on the portion where the gate electrode is to be formed by the photolithography technique.
8 is selectively formed.

【0006】次に、図2(c)に示すように、反応性イ
オンエッチングを行うことにより、多結晶シリコン薄膜
14のホトレジスト18で被覆されていない部分を選択
的に除去し、ゲート電極14を形成する。
Next, as shown in FIG. 2C, reactive ion etching is performed to selectively remove a portion of the polycrystalline silicon thin film 14 which is not covered with the photoresist 18 to remove the gate electrode 14. Form.

【0007】この時、上述した微細化レベルのMIS型
トランジスタにおいては、そのゲート電極をドライエッ
チングにより加工する時に、例えば多結晶シリコンから
なるゲート電極に用いられる半導体薄膜と、その半導体
薄膜の下地の例えばシリコン酸化膜からなるゲート誘電
体膜とのエッチング選択比(エッチングレートの比)を
充分に確保しないと、ゲート誘電体膜がエッチングスト
ッパーとして機能せず、シリコン基板上にプラズマによ
るダメージ層10ができてしまう。
At this time, in the above-mentioned miniaturization level MIS transistor, when the gate electrode is processed by dry etching, for example, a semiconductor thin film used for the gate electrode made of polycrystalline silicon and a base of the semiconductor thin film are formed. For example, unless a sufficient etching selection ratio (ratio of etching rates) with the gate dielectric film made of a silicon oxide film is secured, the gate dielectric film does not function as an etching stopper, and the damage layer 10 due to plasma on the silicon substrate is not formed. I can do it.

【0008】また、図2(d)に示すように、ゲート誘
電体膜であるゲート酸化膜12が、ゲート電極直下の部
分を除いて完全に除去されてしまい、シリコン基板11
も不必要にエッチングされてしまう。
Further, as shown in FIG. 2D, the gate oxide film 12, which is the gate dielectric film, is completely removed except for the portion directly below the gate electrode, and the silicon substrate 11 is removed.
Is unnecessarily etched.

【0009】上述したようなダメージを受けた状態でM
IS型トランジスタを形成した場合には、そのドレイン
拡散層における過大なリーク電流等により、正常なトラ
ンジスタ動作を実現することは不可能である。
In the state of being damaged as described above, M
When the IS type transistor is formed, it is impossible to realize a normal transistor operation due to an excessive leakage current in the drain diffusion layer.

【0010】[0010]

【課題を解決するための手段】上述した課題を解決する
ために、本発明の半導体装置の製造方法は、第1導電型
半導体基板の一主面上に絶縁膜を形成する工程と、該絶
縁膜上に第1の半導体膜を形成する工程と、該第1の半
導体膜上に第2の半導体膜を形成する工程と、該第2の
半導体膜を部分的にエッチング除去し、ゲート電極を形
成する工程と、前記第1の半導体膜を部分的に熱処理す
る工程とを具備する。
In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming an insulating film on one main surface of a first conductivity type semiconductor substrate, and a step of forming the insulating film. A step of forming a first semiconductor film on the film, a step of forming a second semiconductor film on the first semiconductor film, and a step of partially etching away the second semiconductor film to form a gate electrode. The method includes a step of forming and a step of partially heat-treating the first semiconductor film.

【0011】本発明の好ましい態様においては、前記第
1の半導体膜の膜厚が前記第2の半導体膜の膜厚よりも
小さい。
In a preferred aspect of the present invention, the film thickness of the first semiconductor film is smaller than the film thickness of the second semiconductor film.

【0012】[0012]

【作用】本発明の半導体装置の製造方法においては、第
1の半導体膜を例えばゲート誘電体膜である絶縁膜の上
に形成した後、その上に第2の半導体膜を形成し、該第
2の半導体膜をゲート電極となる部分のみを残して選択
的にエッチングした後、例えば酸化雰囲気中で熱処理を
施すことにより、前記第1の半導体膜のうちのゲート電
極の部分以外の部分を全て酸化膜に変質させる。
In the method of manufacturing a semiconductor device according to the present invention, the first semiconductor film is formed on the insulating film which is, for example, the gate dielectric film, and then the second semiconductor film is formed on the insulating film. After selectively etching the second semiconductor film, leaving only the portion to be the gate electrode, heat treatment is performed in, for example, an oxidizing atmosphere to remove all the portion of the first semiconductor film other than the portion of the gate electrode. Transform into an oxide film.

【0013】[0013]

【実施例】以下、本発明をMIS型トランジスタの製造
方法に適用した一実施例を図1を参照して説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a method for manufacturing a MIS type transistor will be described below with reference to FIG.

【0014】まず、図1(a)に示すように、例えばp
型シリコン基板1上にゲート酸化膜2を、例えば水素と
酸素の燃焼による水蒸気雰囲気中で熱処理することによ
り、例えば80Åの膜厚に形成した後、第1の多結晶シ
リコン薄膜3を、減圧CVD法により、例えば200Å
の膜厚に形成し、その後、大気中で一定時間放置する。
そして、この後、第2の多結晶シリコン薄膜4を、減圧
CVD法により、例えば3000Åの膜厚に形成する。
First, as shown in FIG. 1A, for example, p
The gate oxide film 2 is heat-treated in a water vapor atmosphere by burning hydrogen and oxygen, for example, to have a film thickness of, for example, 80 Å, and then the first polycrystalline silicon thin film 3 is subjected to low pressure CVD. Depending on the law, for example, 200Å
The film is formed to a film thickness of, and then left in the atmosphere for a certain period of time.
Then, after this, the second polycrystalline silicon thin film 4 is formed to a film thickness of, for example, 3000 Å by the low pressure CVD method.

【0015】上記工程によれば、第1の多結晶シリコン
薄膜3と第2の多結晶シリコン薄膜4の間には、第1の
多結晶シリコン薄膜3を大気中に放置した際に付着した
自然酸化膜9が例えば10Å程度存在し、第1の多結晶
シリコン薄膜3と第2の多結晶シリコン薄膜4とは、電
気的には導通しているが、間に自然酸化膜9を挟んだ構
造となっている。
According to the above-mentioned process, between the first polycrystalline silicon thin film 3 and the second polycrystalline silicon thin film 4, the natural deposits that are adhered when the first polycrystalline silicon thin film 3 is left in the atmosphere. The oxide film 9 exists, for example, about 10 Å, and the first polycrystalline silicon thin film 3 and the second polycrystalline silicon thin film 4 are electrically connected to each other, but the natural oxide film 9 is sandwiched therebetween. Has become.

【0016】次に、図1(b)に示すように、ホトリソ
グラフィ技術により、ゲート電極を形成すべき部分にホ
トレジスト8を選択的に形成し、この状態で、反応性イ
オンエッチングを行うことにより、第2の多結晶シリコ
ン薄膜4のホトレジスト8で被覆されていない部分を選
択的に除去する。
Next, as shown in FIG. 1B, a photoresist 8 is selectively formed by photolithography on the portion where the gate electrode is to be formed, and reactive ion etching is performed in this state. , A portion of the second polycrystalline silicon thin film 4 not covered with the photoresist 8 is selectively removed.

【0017】この時、本実施例においては、第2の多結
晶シリコン薄膜4が除去された後には自然酸化膜9がエ
ッチングされることになり、この結果、反応性イオンエ
ッチング装置におけるエッチングの終点が検出され、第
1の多結晶シリコン薄膜3が露出した状態、若しくは、
一部、自然酸化膜9が表面に残った状態になる。
At this time, in this embodiment, the natural oxide film 9 is etched after the second polycrystalline silicon thin film 4 is removed, and as a result, the etching end point in the reactive ion etching apparatus is finished. Is detected and the first polycrystalline silicon thin film 3 is exposed, or
A part of the native oxide film 9 remains on the surface.

【0018】この後、図1(c)に示すように、例えば
乾燥酸素雰囲気中で熱処理を施すことにより、第1の多
結晶シリコン薄膜3のゲート電極直下以外の部分を完全
に酸化膜5に変質させる。そして、例えば5×1015
-2でヒ素イオン6をイオン注入してイオン注入層7を
形成した後、窒素雰囲気中で熱処理を行うことにより、
図1(d)に示すように、n型のソース/ドレイン拡散
層7′を形成する。
Thereafter, as shown in FIG. 1C, a heat treatment is performed in, for example, a dry oxygen atmosphere to completely form the oxide film 5 in the portion other than immediately below the gate electrode of the first polycrystalline silicon thin film 3. Transform. And, for example, 5 × 10 15 c
Arsenic ions 6 are ion-implanted at m −2 to form the ion-implanted layer 7, and then heat treatment is performed in a nitrogen atmosphere.
As shown in FIG. 1D, an n-type source / drain diffusion layer 7'is formed.

【0019】[0019]

【発明の効果】本発明の半導体装置の製造方法によれ
ば、例えば、ゲート電極を形成する際、ゲート誘電体膜
がエッチングストッパーとして機能せずにシリコン基板
上に例えばプラズマによるダメージが入り、延いてはゲ
ート誘電体膜が完全に除去されて、シリコン基板も不必
要にエッチングされてしまうような不具合を防止するこ
とができる。
According to the method of manufacturing a semiconductor device of the present invention, for example, when a gate electrode is formed, the gate dielectric film does not function as an etching stopper, and the silicon substrate is damaged by, for example, plasma and spreads. In addition, it is possible to prevent the problem that the gate dielectric film is completely removed and the silicon substrate is unnecessarily etched.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例による半導体装置の製造方法
を示す断面図である。
FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

【図2】従来の半導体装置の製造方法を示す断面図であ
る。
FIG. 2 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 p型シリコン基板 2 ゲート酸化膜 3 第1の多結晶シリコン薄膜 4 第2の多結晶シリコン薄膜 5 酸化膜 7′ ソース/ドレイン拡散層 8 ホトレジスト 9 自然酸化膜 1 p-type silicon substrate 2 gate oxide film 3 first polycrystalline silicon thin film 4 second polycrystalline silicon thin film 5 oxide film 7'source / drain diffusion layer 8 photoresist 9 natural oxide film

フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/336 Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 21/336

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 第1導電型半導体基板の一主面上に絶縁
膜を形成する工程と、 該絶縁膜上に第1の半導体膜を形成する工程と、 該第1の半導体膜上に第2の半導体膜を形成する工程
と、 該第2の半導体膜を部分的にエッチング除去し、ゲート
電極を形成する工程と、 前記第1の半導体膜を部分的に熱処理する工程とを具備
したことを特徴とする半導体装置の製造方法。
1. A step of forming an insulating film on one main surface of a first conductivity type semiconductor substrate, a step of forming a first semiconductor film on the insulating film, and a step of forming a first semiconductor film on the first semiconductor film. A step of forming a second semiconductor film, a step of partially etching away the second semiconductor film to form a gate electrode, and a step of partially heat-treating the first semiconductor film. A method for manufacturing a semiconductor device, comprising:
【請求項2】 前記第1の半導体膜の膜厚が前記第2の
半導体膜の膜厚よりも小さいことを特徴とする請求項1
記載の半導体装置の製造方法。
2. The film thickness of the first semiconductor film is smaller than the film thickness of the second semiconductor film.
A method for manufacturing a semiconductor device as described above.
JP32870092A 1992-11-13 1992-11-13 Manufacture of semiconductor device Withdrawn JPH06151834A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32870092A JPH06151834A (en) 1992-11-13 1992-11-13 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32870092A JPH06151834A (en) 1992-11-13 1992-11-13 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH06151834A true JPH06151834A (en) 1994-05-31

Family

ID=18213203

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32870092A Withdrawn JPH06151834A (en) 1992-11-13 1992-11-13 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH06151834A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0915510A1 (en) * 1997-10-31 1999-05-12 Nec Corporation CMOS semiconductor device and method of fabricating the same
US6037630A (en) * 1997-05-26 2000-03-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with gate electrode portion and method of manufacturing the same
US6229155B1 (en) * 1998-05-29 2001-05-08 International Business Machines Corporation Semiconductor and method of fabricating
US6261885B1 (en) 1999-01-26 2001-07-17 Advanced Micro Devices, Inc. Method for forming integrated circuit gate conductors from dual layers of polysilicon

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6037630A (en) * 1997-05-26 2000-03-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with gate electrode portion and method of manufacturing the same
EP0915510A1 (en) * 1997-10-31 1999-05-12 Nec Corporation CMOS semiconductor device and method of fabricating the same
US6137177A (en) * 1997-10-31 2000-10-24 Nec Corporation CMOS semiconductor device
US6229155B1 (en) * 1998-05-29 2001-05-08 International Business Machines Corporation Semiconductor and method of fabricating
US6261885B1 (en) 1999-01-26 2001-07-17 Advanced Micro Devices, Inc. Method for forming integrated circuit gate conductors from dual layers of polysilicon

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