JPH01161873A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make the temperature of heat treatment high, and reduce sheet resistance, by performing the formation of a source region and a drain region and the heat treatment for electric activation of the regions, before a Sohottky gate is formed. CONSTITUTION:On a channel layer 21 formed on a semiinsulative compound semiconductor substrate 20, a dummy gate 22 is formed. A source region 23 and a drain region 24 of high impurity concentration are formed by ion implantation using the dummy gate 22 as a mask. By another ion implantation, a source region 25 and a drain region 26 are formed. Both the impurity concentrations and the depths of the source region 25 and the drain region 26 are made large as compared with the source region 23 and the drain region 24. By heat-treating, each of the regions 23-26 are subjected to electric activation, and a Schottky gate 18 is formed by using the dummy gate 22. After that, electrodes 29, 30 are formed in the source region 25 and the drain region 26, thereby making heat-treating temperature high, increasing mutual inductance, and enabling high speed operation.

Description

[Detailed Description of the Invention] [Summary] L D D (Lightly Doped Drai
n) Structured shutkey gate field effect transistor (
HEtal-3en+1conductor Junc
Regarding the manufacturing method of tion FET:H[5FET], for the purpose of further improving the mutual fundance Gtn, a first step of forming a dummy gate on a channel layer formed on a semi-insulating compound semiconductor substrate; Using the dummy gate as a mask, a second source region and a second source region having a higher impurity concentration than the channel layer are formed by self-alignment ion implantation.
forming a train region, and performing at least another self-alignment ion implantation to form an impurity layer with a higher impurity concentration and deeper depth than each of the second source region and the second drain region for the dummy gate. a second step of forming a first source region and a first drain region at separate positions;
a third step in which heat treatment is performed to electrically activate each drain region; and a fourth step in which a Schottky gate is formed using the dummy gate by a pattern inversion method.
and a fifth step of forming an ohmic electrode in each of the first source region and the first drain region of the semiconductor device that has undergone the fourth step.

[Industrial application field]

The present invention relates to a method for manufacturing a ¥-conductor device, and particularly to a method for manufacturing a ¥-conductor device.
The present invention relates to a method for manufacturing a D-structure MESFET.

GaASMESFET with field effect i-transistor formed on semi-insulating gallium arsenide (S,I-GaAs) substrate
Among them, GaAs MES with LDD structure as shown in FIG.
FET is known. In the figure, 1 is S, l-GaAs
a substrate, 2 an n+ type first source region, 3 an n+ region n;
An n'-type second source region having an intermediate impurity concentration among the regions, 4 an n+-type first drain region, 5 an n'-type second drain region, and 6 an n-type channel layer. In addition, the first source region 2
An ohmic electrode 7.8 is formed on the first drain region 4, and a gate electrode 9 is formed on the channel layer 6.

Such LDD4M3ffi GaAs MESFET is
The short channel effect (rR value voltage shift to the negative side or transconductance Qt
Since it is possible to reduce the problem of n becoming small, it is currently being actively researched and developed, and high-speed computers,
It is used as one of the basic elements of high-performance large-scale integrated circuits (1-8I) required in high-speed communication systems and the like. In this DD structure GaAs MESFET, it is important to manufacture it so as to fully exhibit its original high speed performance.

[Conventional technology]

FIG. 6 shows a structural sectional view at each stage of an example of a conventional manufacturing method. First, as shown in FIG. 6(a), the S, I-GaAsW plate 1 on which the implantation mask 11 was formed was applied with an acceleration voltage of 30 keV and a dose of Iilt2X1012 cm-2.
An n-type channel layer 6 is formed by selectively implanting silicon (Sl) ions. Next, after removing the implantation mask 11, tungsten silicide (WS i
') is formed on the n-type channel layer 6 as a gate electrode 9 (FIG. 6(b)).

Next, as shown in FIG. 6(C), on the side surface of the gate electrode 9,
After forming the sidewall 12 of S f O2 with a thickness of 2500 mm by anisotropic dry etching, further S, I-
・After forming an implantation mask 13 with a predetermined pattern on the QaAsjJ board 1, as shown in FIG.
m-2, 3i is ion-implanted to form an n'-type first source region 2 and first drain region 4, respectively.

Next, as shown in FIG. 6(e), after one portion of the sidewall 12 is removed, 3i ions are implanted at an acceleration voltage of 50 KeV and a dose of 8 x 1012c IR-2 to form the n' type second source region 3 and the second source region 3 of n' type. Two train regions 5 are respectively formed.

Next, as shown in FIG. 6(), after removing the implantation mask 13, aluminum nitride (A4N) was formed to cover the S, l-GaAs 1 plate 1 and the gate electrode 9 as a heat-treated protective film 14. Source regions 2, 3, drain region 4
, 5 is subjected to heat treatment to activate the electrical properties. Thereafter, the heat treatment protective film 14 is removed, and after a predetermined process, A-mic electrodes 7 and 8 are formed on the first source region 2 and the first drain region 4, as shown in FIG. 6(g). do.

The ohmic electrodes 7 and 8 are made of gold (A) on AuGe, respectively.
It has a two-layer structure in which u) is formed.

FIG. 7 shows structural cross-sectional views at each step of another example of the conventional manufacturing method of the GaAs HESFET having the above-mentioned LDD structure.

In the figure, the same components as those in FIG. 6 are denoted by the same reference numerals, and the explanation thereof will be omitted. FIG. 7(a) shows the same manufacturing steps as FIG. 6(a), and then after forming the gate electrode 9 and the 5fOz implantation mask 16 in the same manner as FIG. 6(b),
As shown in figure (b), accelerated type If, 50 k e V
, 3i was ion-implanted at a dose of 18xlO121-2.
n' JflUl 7.18 respectively.

Next, with the gate electrode 9 and the implantation mask 16 remaining, an oxide film 5i0219 was deposited as shown in FIG.
Si is ion-implanted using IR-2 to form n+ layers as the first source region 2 and first drain region 4 in the n'1ili 17 and 18, respectively, and the regions of the n' layers 17 and 18 on the channel layer 6 side. are defined as a second source region 3 and a second drain region 5.

After that, annealing is performed using the oxide film 19 as a heat treatment protective film to electrically activate the implanted impurities, and then the oxide film 19, the implantation mask 16, etc. are removed, and further predetermined steps are performed, as shown in FIG. 7(d). As shown in < GaAsME with LDD structure
Obtain SFET.

[Problem that the invention seeks to solve]

All of the above conventional manufacturing methods involve high-melting point metal shots and
After forming the WSi gate electrode 9 which is the key gate,
n+Ji, which becomes the source regions 2 and 3 and the drain region 4°5
After forming the 5 and n' layers, a heat treatment is performed to electrically activate the impurities.

Therefore, the upper limit of the annealing temperature of the n+ layer and n' layer is limited by the Schottky gate material, and is generally 800°C to prevent deterioration of the Schottky gate characteristics.
The culm degree was ℃. However, at this temperature, the n+ layer (
There is a limit to the reduction in sheet resistance of the first source region 2 and first drain region 4), and as a result, there is a limit to the reduction in source resistance, and the resistance value is relatively large at submicron gate lengths. There was a problem in that the original high speed performance was not fully exhibited due to the influence of the source resistance (the mutual conductance Om was suppressed).

The present invention has been made in view of the above points, and an object of the present invention is to provide a method of manufacturing a semiconductor device that can further improve the mutual conductance Qm.

[Means for solving problems]

FIG. 1 shows a diagram explaining the principle of the present invention. The present invention is shown in Figure 1 (
It includes the first to fifth steps of obtaining each cross-sectional structure shown in a) to (e). As shown in FIG. 1(a), the first step is to form a channel layer 21 on a semi-insulating compound semiconductor substrate 20.
A dummy gate 22 is formed thereon.

The second step is as shown in FIG. 1(b), where the dummy gate 2
2 as a mask, a second source region 23 with a higher impurity concentration than the channel layer 21 is formed by self-alignment ion implantation.
and a second drain region 24, and at least another self-alignment ion implantation is performed to form a first source region 25 and a first drain region 26.

The first source region 25 and the first drain region 26 have a higher impurity content of 11 J degrees and are formed deeper than the second source region 23 and the second drain region 24.

The third step is to heat-treat the protective film 27 as shown in FIG. 1(C).
Each region 23 to 26 is electrically activated by performing heat treatment with it coated or directly without forming heat treatment protection film 27.

The fourth step is the dummy gate 2 as shown in FIG. 1(d).
Schottky gate 28 using pattern inversion method using
form.

In the fifth step, as shown in FIG. 1(e), an ohmic electrode 29 is placed on the first source region 25 and the first drain region 26.
．． form 30. In this way, according to the present invention, a semiconductor device having an LDD structure can be manufactured by applying a self-alignment process using a dummy gate.

[Effect]

In the present invention, after forming the first source region 25 and the first drain region 26 in the second step (FIG. 1(B)), heat treatment is performed in the third step (FIG. 1(C)). Step 4 (
A Schottky gate 28 is formed in FIG. 1(d).

That is, in the present invention, since the heat treatment for forming the first source region 25 and the first drain region 26 and for electrically activating the first source region 25 and the first drain region 26 is performed before forming the Schottky gate 28, the upper limit of the heat treatment temperature is the Schottky gate. There is no need to limit the temperature to a temperature that does not deteriorate the gate characteristics, and even higher temperatures (
For example, the temperature may be 800°C to 1200°C).

〔Example〕

FIG. 2 shows an explanatory diagram of each step of the first embodiment of the present invention.

First, as shown in FIG. 2(a), after forming a 5 fOz implantation mask 32 in a predetermined pattern on an S, l-GaAs substrate 31 as an example of a semi-insulating compound semiconductor substrate 20, an acceleration voltage of 30 keV was applied.

An n-type channel layer 33 corresponding to the channel layer 21 is formed by ion-implanting 3i at a dose of 2×10 12 c#I-2. Next, as shown in FIG. 2(b), the channel layer 3
A 0A to N film 34 with a thickness of 300 layers is formed on the surface of the GaAs substrate 31 on the side where the film 3 is formed by a sputtering method, and a 1 μm thick film 34 is formed on it by sputtering.
After depositing a thick SiN film, photolithography and dry etching techniques are used to leave only a predetermined portion of the SiN and remove other SiN film portions. As a result, the SiN film in the predetermined portion is formed as a dummy gate corresponding to the dummy gates 1 and 22 as shown by 35 in FIG. 2(b) (hereinafter referred to as the first gate).

Next, using the implantation mask 32 and the dummy gate 35 as masks, Si ion implantation was performed at an acceleration voltage of 50 keV, a dose Ei, and 6 x 1012 cm-2, as shown in FIG. 2(b). In the uncovered portion of the n-type channel layer 33, n' layers 36 and 37 are formed as a second source region and a second drain region.

After that, as shown in FIG. 2(C), the dummy gate 3
After forming a sidewall 38 made of SiO2 with a thickness of 0.3 μm on the side surface of the substrate 5 by anisotropic dry etching, an accelerating voltage of 120 keV and a dose of fft4Xio 14. ,−
In step 2, ion implantation of 3i is performed, and an n++ layer 39 with a higher impurity concentration and a deeper depth is implanted in the portion of the n' layer 36, 37 that is not covered by the implantation mask 32, dummy gate 35, and sidewall 38. and 40 as a first source region and a first drain region, respectively (the above is the second step).Next, the sidewall 38 is formed using hydrofluoric acid (HF).
After removing the injection mask 32 at the same time, a chemical vapor deposition method (CVD method) is applied to form a heat-treated protective film 41 (corresponding to the heat-treated protective film 27) with <5 iOz as shown in FIG. 2(d). form, do. After that, each area 3
3.36.37.39 and 40 (n, n' and n++
The electrical activation heat treatment of the layer) is performed at a temperature of 1100° C. for 5 seconds (this is the third step).

Next, after removing the heat-treated protective film 41 with, for example, phosphoric acid,
A photoresist is applied and planarized, and the photoresist 42 is etched by dry etching until the top of the dummy gate 35 is exposed as shown in FIG. 2(e).

Thereafter, after removing the dummy gate 35 and the portions of the Al1N film 34 corresponding to the dummy gate 35 by etching, the tungsten silicide W of the Schottky gate material is etched.
1. . As shown in FIG. 2(e), a Wl, OS' 0.6 film 43 is formed by sputtering S'0.6 on the photoresist 42. .

Next, only the Wl, OS' 0.6 film 43 formed on the n-type channel layer 33 is shot by the lift-off method.
The remaining portions of the Wl, OS' O, and [i films 43 are removed together with the photoresist 42, and the Al1N film 34 is also removed (FIG. 2(g)). . Figure 2 (e) and (f) above.
) The fourth step is realized by the pattern inversion method using the dummy gate 35 according to each step.

Finally, the first source region 25 and the first drain region 2
After depositing AuGe to a thickness of about 10,000 nm on each of 6, Au was formed thereon to a thickness of about 10,000 nm, as shown in FIG.
As shown in h), the ohmic electrodes 44°45 (29.
30) (this is the fifth step). This completes the LDD structure GaASMESFET.

According to this embodiment, the heat treatment is performed after forming the n+" layer 39.40 and the n' layer 36.37 by a self-alignment process using the dummy gate 35.
The heat treatment temperature can be increased to about 1100°C. Therefore, the sheet resistance of the n++ layer 39.degree. 40 can be lowered compared to the conventional one, thereby reducing the source resistance and increasing the mutual conductance Qm of the FET.

FIG. 3 shows the gate length vs. mutual conductance characteristics based on the results of the prototype experiment conducted by the present inventor, and the characteristics according to this example are as shown by the solid line, and the MES
Compared to the FET characteristic (2), a characteristic with an increased mutual conductance Om was obtained at the same gate length.

In the first embodiment described above, after forming the n' layers 36 and 37, side walls were formed on the side surfaces of the dummy gate 35 to form the n++ layers 39 and 40. After forming the wall, first
+ + F is formed by ion implantation, and then the sidewall is removed and ion implantation is performed again to form n.
' layer may be formed. In addition, Al1N film 3
A similar effect can be obtained even if the dummy gate 35 is formed directly on the channel layer 33 without using the dummy gate 4.

Next, a second embodiment of the present invention will be described with reference to FIG. 4. In the figure, the same components as those in FIG. This example differs from the first example in the culm, and the other steps (Fig. 4(a),
(b), (d) to (q)) are the same as in the first example of the first embodiment. However, in the ion implantation for forming the n' layer shown in FIG. 4(b), the dose flea is 8×1012 compared to the first actual flow side.
It is different from α-2.

After forming the above n' layers 36 and 37, as shown in FIG.
2, a 5tO2 film 47 with a thickness of 2,500 mm is formed as a film with good step coverage. At this time, the 5iOz film 47 is also formed on the side wall of the dummy gate 35 to a thickness substantially equal to the film thickness.

After this, as shown in Fig. 4(C), the acceleration voltage is 200K.
n4+ layers 39 and 40 are formed in the n'F336°37 as the first source region and the first drain region by ion implantation of 3i with a dose layer of 6x 10" an-2. After this, a 5iOz film is formed. Heat treatment is performed at 1100° C. for 5 seconds using No. 47 as a heat treatment protective film.

As described above, by going through the same steps as in the first embodiment, GaA with the l-D D structure as shown in FIG. 4(g) is finally obtained.
An sMESFET is manufactured. This embodiment also improves Qm like the first embodiment.

Whereas in the first embodiment, the sidewall 38 is provided and the n++ layers 39 and 40 are formed apart from the dummy gate 35, in this embodiment, the sidewall 38 is not provided. The energy at the time of ion implantation must be increased, the dose control must also be increased, and the sycote channel effect is also slightly larger than in the first embodiment (so the characteristics are better than those in the first embodiment). is good.

On the other hand, the second embodiment has the advantage that the number of steps is small because there is no sidewall forming step as in the first embodiment.

Note that in the second embodiment, the dummy gate 35 is S i N
Although 5 iOz was used as the M n ''+ layer through-injection film 47, it is not limited to this, and any material may be used as long as it is a combination that can selectively remove both. In this case, after removing the S!Oz film 47 and the implantation mask 32 made of 5fOz, the dummy gate 35 was flattened and the dummy gate 35 was located, but the planarization and the locating of the dummy gate 35 were carried out with both of them remaining. Further, the dummy gate 35 may be formed directly on the channel layer 33 without using the AeN film 34.

Further, in each of the above embodiments, the heat treatment was performed with the heat treatment protective film 41 and the SiO2 film 47 left, but they were removed and the A-N film 34 was left bare.
Annealing may be performed in a s pressure atmosphere, and in the case of the second embodiment, the
The heat treatment may be performed after removing the fOz film 47 and forming a new heat treatment protective film. Furthermore, dummy gate 35. Side wall 38. Of course, the materials of the Schottky gate 43 and the like are not limited to those in the embodiment.

〔Effect of the invention〕

As described above, according to the present invention, since the heat treatment temperature can be made higher than that of the conventional method, the sheet resistance of the first source region and the first drain region can be reduced, and thereby the mutual resistance of the FET can be reduced. A GaAs MESFET with an LDD structure that can increase the conductance Qm and is faster! It has features such as being able to be manufactured in a number of ways.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is an explanatory diagram of the first embodiment of the present invention, Fig. 3 is a diagram of gate length vs. mutual conductance characteristics, and Fig. 4 is a diagram of the characteristics of mutual conductance versus gate length. 2 Examples] [Culm explanatory diagram, Fig. 5 is GaAS
A structural cross-sectional view of an example of a MESFET, and FIGS. 6 and 7 are explanatory diagrams of each step in a conventional manufacturing method, respectively. In the figure, 20 is a semi-insulating compound semiconductor substrate, 21 is a channel layer 22 is a dummy gate, 23 is a second source region, 24 is a second drain region, 25 is a first source region, 26 is a first drain region, 28 is a Schottky gate, and 29.30 is an ohmic electrode. An explanatory diagram of the principle of the present invention. Fig. 1. Gate length (/Jm) y-t length versus mutual conductance characteristic. Fig. 3. Structural sectional view of an example of a GaAs 5FET. Fig. 1 to 5. Explanation of each step of an example of a conventional manufacturing method. Figure $6 Figure (Part 1) The twenty-fifth figure of the present invention (explanatory diagram of each process on the downstream side; Figure 4) Illustration of each process of an example of the conventional manufacturing method. Figure 6 Figure (Part 2) 6 layers. Figure 7

Claims (5)

[Claims] (1) A first step of forming a dummy gate (22) on a channel layer (21) formed on a semi-insulating compound semiconductor substrate (20), and self-alignment ion implantation using the dummy gate (22) as a mask. A second source region (23) and a second drain region (24) having a higher impurity concentration than the channel layer (21) are formed by performing at least another self-alignment ion implantation to form a second source region (23). The dummy gate (22) is an impurity layer having a higher impurity concentration and a deeper depth than the second drain region (24) and the second drain region (24).
), a second step of forming a first source region (25) and a first drain region (26) at positions apart from the first and second source regions (25, 23); A third step of performing heat treatment to electrically activate each of the second drain regions (26, 24), and forming a Schottky gate (28) using the dummy gate (22) by a pattern inversion method. a fourth step; and the first source region (2) of the semiconductor device that has undergone the fourth step.
5) and a fifth step of forming ohmic electrodes (29, 30) in each of the first drain regions (26). (2) In the second step, the second step is performed by self-alignment ion implantation using the dummy gate (22) as a mask.
A step of forming a source region (23) and a second drain region (24), forming a sidewall on the dummy gate (22), and performing self-alignment ion implantation using the dummy gate (22) and the sidewall as a mask. The second source region (23) and the second drain region (24)
2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming the first source region (25) and the first drain region (26) in each part of the semiconductor device. (3) In the second step, a sidewall is formed on the dummy gate (22), and the first source region (25) and the first source region (25) are After removing the sidewalls, the first source region (25) is formed by self-alignment ion implantation using the dummy gate (22) as a mask.
and forming the second source region (23) and the second drain region (24) in each part of the first drain region (26).
A method for manufacturing a semiconductor device according to section 1. (4) In the second step, the second step is performed by self-alignment ion implantation using the dummy gate (22) as a mask.
forming a source region (23) and a second drain region (24); coating a film on the semiconductor substrate (20) and the dummy gate (22); and performing self-alignment ion implantation through the film. Claim 1, characterized in that the method comprises a step of forming the first source region (25) and the first drain region (26).
A method for manufacturing a semiconductor device according to section 1. (5) The temperature range of the heat treatment in the third step is 80°C.
A method for manufacturing a semiconductor device according to any one of claims 1 to 4, characterized in that the temperature is selected to be 0°C to 1200°C.