JPH01161872A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce sheet resistance, by performing the formation of a source region and a drain region, and the heat treatment for the electric activation, before a Schottky gate is formed. CONSTITUTION:On a channel layer 17 formed on a semiinsulative compound semiconductor substrate 16, dummy gates 18, 19 are formed in order. By using the dummy gate 19 as a mask, ion-implanting and side.etching of side wall of the dummy gate 18 are performed in order, thereby forming a deep source region 20 and a deep drain region 21 whose impurity concentrations are higher than the channel layer 17. After the dummy gate 19 is eliminated, ion-implanting is performed by using a dummy gate 18 as a mask, and a shallow source region 22 and a shallow drain region 23 are formed, whose impurity concentrations are lower than the source region 20 and the drain region 21. By heat-treating, each of the regions 17, 20-23 is subjected to electric activation. After a Schottky electrode 25 is formed by using the dummy gate 18, electrodes 26, 27 are formed. Thereby the temperature of heat treatment is made high, the sheet resistance is reduced, and high speed operation is enabled.

Description

[Detailed description of the invention] Cm required] L D D (Lightly Doped Drai
n) Structure Schottky gate field effect transistor (HEtal-5EHICONDLICTQRJun
Regarding the manufacturing method of cation FET (HESFET), in order to further improve the mutual conductance Qrn, a first Schottky gate is placed on the channel layer formed on the semi-insulating compound semiconductor substrate at the position where the Schottky gate is to be formed. a first step of sequentially stacking a dummy gate and a second dummy gate; a self-alignment ion implantation using the second dummy gate as a mask; and a step of stacking the first dummy gate using the second dummy gate as a mask. By sequentially performing side etching to make the sidewall inside the sidewall of the second dummy gate in an arbitrary order, a first source region and a first train region having a higher impurity concentration and a deeper depth than the channel layer are formed. After removing the second dummy gate, self-alignment ion implantation is performed using the first dummy gate as a mask to form an impurity concentration lower than that of the first source region and the first drain region. forming a shallow second source region and a second drain region;
, a fourth heat treatment for electrically activating the second source region and the first and second drain regions, respectively;
culm, a fifth °Y culm in which a Schottky gate is formed by a pattern inversion method using the first dummy goo 1~, the first source region and the first A sixth electrode is formed to form an ohmic electrode in the drain region.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and in particular, 1.D.
This relates to the ¥lJ'#i method for D-structure MESFET.

Among GaASMESFETs in which a field effect transistor is formed on a semi-insulating gallium arsenide (S, 1-GaAs) substrate, a GaAsMESF with an LDD structure as shown in Fig. 5 is used.
ET is known. In the figure, 1 is S, I-GaAsW
plate, 2 is an n+ type first source region, 3 is an n+, region and n
4 is an n+ type first drain region, 5 is an n'5"! second drain region, and 6 is an n-type channel layer. Ohmic electrodes 7.8 are provided on the region 2 and the first drain region 4.
is formed, and a gate electrode 9 is formed on the channel layer 6.

GaAs MESFETs manufactured by DDMIJ are currently being actively researched and developed because they can reduce the short channel effect (a problem in which the threshold voltage shifts to the negative side or the mutual conductance gm decreases) even at submicron gate lengths. Takatake's integrated circuits (
1-81) is used as one of the basic elements. In this LDD structure GaAs MESFET, it is important to manufacture it so as to fully exhibit its original high speed performance.

[Conventional technology]

FIG. 6 shows structural cross-sectional views at each step of an example of a conventional manufacturing method. First, as shown in FIG. 6(a), 71
]m'i[j'30kOV, do7"m2xlO12G
-2, silicon (S i ) is selectively ion-implanted to form an n-type channel layer 6 . Next, after removing the implantation mask 11, as shown in FIG. 6(b), tungsten silicide (WS i ) is formed as a gate electrode 9 on the n-type channel layer 6 by sputtering, and then silicon dioxide (
1ff of SiC2) film 12 is deposited, and a predetermined width is left at the position where the Schottky gate is to be formed by photolithography and dry etching.

Next, the WSi that will become the gate electrode 9 is shown in FIG. 6(C).
As shown in the figure, the SiO2 film 12 is used as a mask and the thickness is 0.3 μm.
After side etching, the implantation mask 13 is
- After being provided on the GaAS substrate 1, the acceleration voltage is 120 ke.
3i is ion-implanted at a dose of fi13x1013cts-2. As a result, an n+ layer having a higher impurity concentration than the channel layer 6 is formed as the first source region 2 and the first train region 4.

Next, S! was used as a dummy gate! After removing the Oz film 12 by etching, the gate electrode 9 and the implantation mask 1 are removed.
3 as a mask, Si is ion-implanted at an acceleration voltage of 50 keV and a dose of 8×1012c111-2, as shown in FIG. Form as a region.

Thereafter, the implantation mask 13 is removed, and the gate electrode 9 is left as shown in FIG. 6(e).
After forming a heat treatment protective film 14 on the S, l-GaAs substrate 1 and gate electrode 9, a heat treatment is performed to activate the electrical characteristics of the source region 2.3 and drain region 4.5. Let's do it.

Finally, after removing the heat-treated protective film 14, ohmic electrodes 7 and 8 are formed on the first source region 2 and the first drain region 4, as shown in FIG.
Completed GaAs IESFE device with LDD structure.

Note that the ohmic electrodes 7 and 8 are made of Au on AUGe, respectively.
It has a two-layer structure. 1 [Problems to be Solved by the Invention] In the above conventional manufacturing method, after forming the gate electrodes 1 to 9 of WSi, which is a refractory metal Schottky gate, the source regions 2 and 3, the drain region 4, 5 n+ layer and n'
After forming Fr, heat treatment is performed to activate the electrical characteristics of the impurity.

Therefore, the upper limit of the annealing temperature of the n' layer and the n' layer is limited by the Schottky gate material, and is generally 800 m
However, at this temperature, the n+ layer (
There is a limit to the reduction in sheet resistance of the first source region 2 and first drain region 4), and as a result, there is a limit to the reduction in source resistance. There was a problem in that the original high-speed performance was not fully demonstrated during engraving (mutual inductance (Jm) was suppressed).

The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a conductor device that can further improve the mutual conductance QT11.

[Means for solving problems]

FIG. 1 shows a diagram explaining the principle of the present invention. The present invention is shown in Figure 1 (
It includes the first to sixth steps of obtaining each cross-sectional structure shown in a) to (f). The first step, as shown in FIG. dummy gates 19 are sequentially formed.

As shown in FIG. 1(b), the second culm is formed by self-alignment ion implantation using the first dummy gate 19 as a mask and the sidewall of the first dummy gate 18 using the second dummy gate 19 as a mask. The first source region 20 and the first drain region, which have a higher impurity concentration and a deeper depth than the channel layer 17, are formed by sequentially etching them inward from the sidewalls of the second dummy gate 19 in an arbitrary order. 21 is formed.

As shown in FIG. 1(C), the third :r culm is formed by removing the gate electrode 19 from the second dummy gate 1, and then performing self-alignment ion implantation using the first dummy gate 18 as one mask. A second source region 22 and a second drain region 23 having a lower impurity concentration of 1σ and a shallower depth than the region 20 and the first drain region 21 are formed.

Further, in the fourth step, as shown in FIG. 1(d), heat treatment is performed directly with the heat treatment protection film 24 covered or without forming the heat treatment protection IE 324, and each area 17.
Perform electrical activation of 0-23.

In the fifth step, as shown in FIG. 1(e), a Schottky gate 25 is formed using the first dummy gate 18 by a pattern inversion method.

In the sixth step, as shown in FIG. 1(f), an ohmic electrode 26 is placed on the first source region 20 and the first drain region 21.
．． form 27. In this way, according to the present invention, an LDD structure t-S body device can be manufactured by applying a self-alignment process using a dummy gate.

[Effect]

In the present invention, after forming the first source region [20 and the first drain region 21] in the third step (FIG. 1(C)),
Heat treatment is performed in the step (FIG. 1(d)), and a Schottky gate 25 is formed in the fifth step (FIG. 1(e)).

That is, in the present invention, since the heat treatment for forming the first source region 20 and the first drain region 21 and for electrically activating the first source region 20 and the first drain region 21 is performed before forming the Schottky gate 25, the upper limit of the heat treatment temperature is the Schottky gate. There is no need to suppress the humidity to a level that does not deteriorate the gate characteristics, and even higher temperatures (
For example, 800°C to 1200°C).

〔Example〕

FIG. 2 shows an explanatory diagram of each embodiment of the present invention. First, as shown in FIG. 2(a), after forming an implantation mask 31 with a predetermined pattern on an S, I-GaAs substrate 30 as an example of a semi-insulating compound semiconductor substrate 16,
The n corresponding to the channel layer 17 was ion-implanted with 3i at 0 keV and a dose of fij 2 x 1011012C.
A mold channel layer 32 is formed. Next, S is applied to the surface of the GaASM plate 30 on the side where the channel layer 32 is formed by a known method.
After sequentially laminating the iO2 film and the All film, photolithography and dry etching were applied to form the film as shown in Fig. 2(b).
At the position where the Schottky gate should be formed, as shown in
A first dummy gate 33 made of a SiO2 film and a second dummy gate 34 made of an Ae film are formed on the first dummy gate 33.

The above corresponds to the first step.

Next, as shown in FIG. 2(b), after forming an implantation mask 35 at a predetermined position, an acceleration voltage of 100 k e V was applied.

By ion-implanting Si at a dose of fji4 x 1014 ctn-2, n++ layers 36 and 37 having a higher impurity concentration than the n'' layer are formed in the portions not covered by the implantation mask 35 and the dummy gates 34 and 35, respectively. A first source region (corresponding to 20 above) and a first drain region (corresponding to 21 above) are formed.

Next, after removing the implantation mask 35, using the second dummy gate 34 as a mask, as shown in FIG.
Side etching is performed so that the side wall of the dummy gate 33 is located about 0.3 μl inside the side wall of the second dummy gate 34 (the above is the second step).

Next, after removing the second dummy gate 34 by dry etching, the implantation mask 4 is etched as shown in FIG. 2(d).
0, and by self-alignment ion implantation using the first dummy gate 33, n +
The impurity concentration is lower than that of the + layer 36 and 37, but the impurity concentration is higher than that of the n-type channel layer 32, and the n++ layer 3
The 07 layers 38 and 39 having a depth shallower than 6°37 are
A source region 22 and a second drain region 23 are formed. This self-alignment ion implantation is performed at an acceleration voltage of 50
This step is performed by ion-implanting Si under the conditions of keV and dose ff18 x 1012 ctn-''. This step corresponds to the third step.

Next, after removing the implantation mask 40, with the first dummy gate 33 remaining, as shown in FIG.
I-GaASI board 30 and dummy goo!・A on 33
A 4N film is coated with a thickness of 1000 mm as a heat-treated protective film 41 (corresponding to the heat-treated protective film 24 of m2). After that, the 0 layer 32, the n++ layer 36, 37, n' FyJ
In order to electrically activate 38 and 39, heat treatment is performed at a temperature of 1100°C for 5 seconds (the above is the fourth culm).
.

Next, after removing the heat-treated protective film 41 with, for example, phosphoric acid,
The photoresist 42 is applied, dried, and flattened, and then dry etched until the top of the first dummy gate 33 is exposed, as shown in FIG. 2(f).
Etch 2.

Thereafter, after removing the first dummy gate 33 by etching, tungsten silicide wi,o S' 0.6, which is a Schottky gate material, is sputter-deposited as shown in FIG.
As shown in Q), wi, o S' 0 is formed on the photoresist 42 where the dummy gate 33 was originally located and the rest of the photoresist 42.
．． 6 films 43 are formed.

Next, Wl is formed on the n-type channel layer 33 by a lift-off method. Only the S'0.6 film 43 is left as a Schottky gate (corresponding to the Schottky gate 25), and the other parts of the W St□,6 film 1.0 43 are removed together with the photoresist 42 (see Figure 2 (h). )
). The fifth step is realized by the pattern inversion method using the dummy gate 33 according to the steps shown in FIGS. 2(Q) and 2(h).

Finally, AuGe is deposited to a thickness of about 1000 layers on each of the n++ layers 36 and 37 (first source region and first drain region), and then AU is formed thereon to a thickness of about 1000 layers. Ohmic electrode 44.4 as shown in Figure 2(i)
5 (corresponding to 26.27 above) (this is the sixth step). As a result, GaAsMESFE with LDD structure
T is completed. .

According to this embodiment, the heat treatment is performed after forming the n''+ layer 36.37 and the n' layer 38.39 by a self-alignment process using the dummy gates 33 and 34, so the temperature of the heat treatment can be reduced. The temperature can be raised to about 1100°C. Therefore, the sheet resistance of the n+ layer 36, 37 can be lowered compared to the conventional one, which reduces the source resistance and increases the mutual conductance (JTI+) of the FET. can.

FIG. 3 shows the gate length vs. mutual conductance characteristics based on the results of a prototype experiment conducted by the present inventors.
Compared to the FET characteristic (2), a characteristic in which the mutual conductance Qm was increased at the same gate length was obtained.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but the order of the steps shown in FIGS. In addition, in the step shown in FIG. 2(b), the first dummy gate 33 and the implantation mask 3
4 was formed directly on the surface of the GaAs substrate 30, but as shown in FIG.
It is also possible to form an insulating film such as the above, and then form the first dummy gate 33 and the implantation mask 34 thereon.

In this case, damage caused by dry etching can be reduced more than in the embodiment.

However, in this case, as shown in FIG. 2(q), as shown in FIG. 4(b), the A to N film 47 at the position where the Schottky gate should be formed is The surface of the channel layer 32 must be exposed by etching. This is because the Schottky gate must be formed directly on the channel layer 32.

In addition, although the SiO2 film and the Al film were used as the materials for the first and second dummy gates 33 and 34 in the embodiment, the materials are not limited to these.
The material may be any material as long as it is not removed by etching when the first dummy gate 33 is side-etched. However, the first dummy gate 33 is preferably made of a material that can be subjected to high-temperature heat treatment and can be used as a heat treatment barrier film for GaAs.

Furthermore, although the heat treatment was carried out using the heat treatment protective film 41, the desired effect of the present invention can also be obtained by annealing in an As pressure atmosphere without providing the heat treatment protective film 41.

〔Effect of the invention〕

As described above, according to the present invention, since the heat treatment temperature can be made higher than that of the conventional method, the sheet resistance of the first source region and the first drain region can be reduced, thereby reducing the mutual conductance qτ1 of the FET. It has the advantage of being able to manufacture GaAs MESFETs with an LDD structure that can be increased in size and at higher speeds.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is an explanatory diagram of an embodiment of the present invention, Fig. 3 is a diagram of gate length versus mutual conductance characteristics, and Fig. 6 is a diagram of conventional manufacturing. 82 is an explanatory diagram of an example of the method. In the figure, 16 is a semi-insulating compound semiconductor substrate, 17 is a channel layer, 18 is a first dummy gate, 19 is a second dummy gate, 20 is a first source region, 21 is a first drain region, 22 is a second dummy gate 23 is a second drain region, 25 is a Schottky gate, and 26 and 27 are ohmic electrodes. 3° Diagram for explaining the principle of the present invention. FIG. 1 Diagram for explaining each process in an embodiment of the present invention. Part 1) An explanatory diagram of each process of an embodiment of the present invention Fig. 2 (Part 2) Gate length (μm) Dart length vs. mutual conductance characteristic diagram Fig. 3 Detailed explanatory diagram of the present invention Fig. 4 An example of a GaAs MESFET Structural sectional view Fig. 5 An explanatory diagram of each process of an example of the conventional manufacturing method Fig. 6

Claims (2)

[Claims] (1) A first dummy gate (18) and a second dummy gate (19) are placed on the channel layer (17) formed on the semi-insulating compound semiconductor substrate (16) at the position where the Schottky gate is to be formed. a self-alignment ion implantation using the second dummy gate (19) as a mask;
) as a mask to make the side wall of the first dummy gate (18) inside the side wall of the second dummy gate (19). ) with higher impurity concentration and deeper depth than the first source region (20) and first drain region (20).
1), and after removing the second dummy gate (19), self-alignment ion implantation is performed using the first dummy gate (18) as a mask to form the first source region. (20) and a second source region (22) and a second drain region (22) having a lower impurity concentration and shallower depth than the first drain region (21).
3), and a third step of forming the first dummy gate (18) with the first dummy gate (18) remaining.
a fourth step of performing heat treatment for electrically activating the second source region (20, 22) and the first and second drain regions (21, 23), and the first dummy gate ( 18) to form a Schottky gate (25) by a pattern inversion method, and forming the first source region (25) of the semiconductor device through the fifth step.
0) and a sixth step of forming ohmic electrodes (26, 27) on each of the first drain region (21) and the first drain region (21). (2) The temperature range of the heat treatment in the fourth step is 80°C.
The method for manufacturing a semiconductor device according to claim 1, wherein the temperature is 0°C to 1200°C.