JPS6292481A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the integration and to eliminate a decrease in characteristics by heat treating and then forming a low resistance electrode material on a high melting point metal heat resistant gate electrode in a self- aligning manner. CONSTITUTION:With resist 8 and gate electrode 1 as masks Si ions are implanted to source, drain regions, the resist 8 is removed, annealed again in As atmosphere to form a high density impurity region 5. After the entire wafer is covered with a resist film 9, and the resist surface is flattened by heating. Then, it is dry etched with O2 until the resist 9 on the SiO2 film 7 is removed. The film 7 is removed by etching with diluted fluoric acid, and Au 10 is deposited by an electron beam depositing method. The resist 9 is eventually removed with organic solvent to remove the Au 10 on the resist 9, source, drain electrodes AuGe-Ni are deposited, alloyed at 400 deg.C to form source and drain electrodes 2, 3.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device including a two-layer electrode structure.

(Prior art) For example, in order to improve the performance of a field effect transistor (hereinafter referred to as ME5FET) using a barrier type field effect transistor using gallium arsenide (GaAs), an MF18 PET as shown in the schematic cross-sectional view of Fig. 2 is used. The structure of is known. In the figure, 1 is a heat-resistant gate electrode, 2 is a source electrode, 3 is a drain electrode, 4 is a GaAs active layer, 5 is a high concentration impurity region, and 6 is a semi-insulating GaAs substrate. In this structure,
For example, Internashi Explosive Solid State Circuit @ Core 77 Uyx (: II
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As shown on page 44 of 1Rcaits Conference), by ion-implanting and activating high-concentration impurities into the source and drain regions using the gate 'wL pole as a mask, the parasitic resistance of the source and drain lines is reduced. We are trying to reduce this.

Therefore, it is necessary for the gate electrode to have stable Si-Jitto characteristics even after heat treatment for activation, and currently, for example, mixtures or compounds of high melting point metals such as tungsten silicide (WSi) are used. .

Further, since the gate w electrode material is used as a wiring electrode in an integrated circuit, it is required to have low resistance in order to reduce wiring delay. Also, when F"ET is used as a low-noise or high-output amplification element, reducing the gate resistance is essential for achieving high performance. Therefore, this structure has high heat resistance and low resistance. ) [The development of 1 is necessary for manufacturing the element and improving the performance of the tube.

(Problems to be Solved by the Invention) At present, mixtures or compounds of high melting point metal rings are mainly used as gate electrode materials having high heat resistance, but the resistivity thereof is, for example, A/, Att, etc. The disadvantage is that it is relatively expensive and cannot operate at high speed.

Low resistance can be achieved by laminating A/ and Au thick on a high melting point gold thread material, but in the case of a gate electrode with this structure, A/
It was found that Au easily diffuses into GaAs through the high-melting-point all-polar thread membrane, and it is difficult to obtain good SiOtchi properties even after heat treatment. Therefore, after heat treatment, A/
Although it is preferable to laminate low-resistance single-pole materials such as Au thick, there is a problem in that when this is done by mask alignment, a margin for alignment is required and the degree of integration is reduced.

In view of the above problems, an object of the present invention is to form a low-resistance electrode material in a self-aligned manner on a heat-treated edge and a heat-resistant gate electrode structure made of a melting point metal, thereby eliminating the need for mask alignment margin. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can improve the degree of integration without causing any deterioration in characteristics.

(Means for Solving the Problems) According to the method for manufacturing a semiconductor device of the present invention, a first gate electrode is provided on a gate region on a semiconductor active layer formed on a semiconductor substrate, and an insulating film is provided on the first gate electrode. a step of forming a two-layer structure in which the conductor substrate is laminated, a step of applying a resist to the entire surface of the conductor substrate, a step of etching away the resist on the insulating film and making the upper surface of the insulating film a wire, and a step of etching the resist on the insulating film, a step of removing the exposed insulating film, a step of forming a second gate electrode material on the first gate electrode and the resist, and a step of removing the resist and the second gate electrode side on the resist. The method is characterized in that it includes a step of forming at least a two-layer gate electrode structure.

(Function) It is possible to form a resist thicker than the heat-resistant gate electrode and the thickness of the heat-resistant gate electrode on the GaAs surface other than on the heat-resistant gate electrode by self-alignment without causing any deterioration of the heat resistance. It is possible to create heat-resistant goo using the lift-off method.
It becomes possible to laminate the second gate electrode material on top of this layer with the same dimensions as the 1fjA.

(Example) Next, the drawings regarding the example of the present invention are tf! @Site-ni5・,- Explain. FIGS. 1A to 1F are schematic cross-sectional views of a semiconductor device shown in order of steps to explain an embodiment of the present invention.

First, as shown in Figure 1 (al), medium insulating (JaAs)
Prepare the substrate 6 and apply 81 ions to the soil of the substrate 6 at 50 keV.

Selective ion implantation was performed under the condition of 2 x 10'α1,
Annealing was performed at 800°C for 20 minutes in an As atmosphere, and G
aAs operation 7i114 is formed. Next, using the sputtering method, W
Si1 was deposited with a thickness of 0.2 μm on the GaAs substrate 4.
g, and then Si0,7 was deposited on WSil using the CVD method.
．． A thickness of 3 μm was deposited. Next, a resist is formed on the part that will become the gate electrode, and the SiO
. An insulator 7 is formed on the electrode.

Next, as shown in FIG. 1(b), using the resist 8 and gate voltage vkl as masks, 8i ions were heated to 150 k eV.
Ions were implanted into the source and drain regions under the conditions of , 5×IO cm-, and the edge from which the resist 8 was removed was again annealed for 20 minutes at 800 cm in an As atmosphere to form the high concentration impurity region. form 5.

Next, as shown in FIG.
After coating the entire surface of the wafer with a thickness of 5 μm, it was heated at 200°C.
The resist surface was flattened by heating.

Next, as shown in FIG. 1(d), dry etching is performed using Ol until the resist 9 on 8i0, 7 is removed.

Next, as shown in FIG. ts1 (e), 8i0,7 is removed by etching with dilute hydrofluoric acid, and Au1O is deposited to a thickness of 0.2 μm by electron beam evaporation.

At the very top, as shown in Figure 1), the Au1O on the resist 9 was removed by removing the resist 9 with an organic solvent, and AuGe-Ni was deposited on the source and drain electrodes, and a layer of 400'0 was formed. Source frost pole 2 by doing alloy
．． A drain electrode 3 is formed to complete the fabrication of F'ET.

In addition to the above fabrication of FB '1', we also fabricated 9 PET using the conventional WSj single layer gate and pole (film thickness 0.4 μm). As a result of measuring the minimum noise figure NFm1n at 12 GHz, in the conventional F'ET with the W8i$RIi gate, NFmin is 2.3 dB, and in the F'FT with the two-layer gate according to the embodiment of the present invention, NFm1nt= 1
．． An improvement of 8 dB and NFm1n was observed. This is because the bending of the gate electrode is reduced by nearly an order of magnitude compared to the conventional method.

In addition, reducing gate resistance is a major issue in integrated circuits) II
It is effective in reducing the delay time of wiring electrodes using c-pole material.
It is also extremely effective in realizing high-speed operation of integrated circuits.

(Effects of the Invention) As explained above, according to the present invention, it is possible to stack a self-aligned, low-reflection gate electrode material on a high-temperature heat-treated, heat-resistant gate electrode. The effect is that high-speed operation can be realized without reducing the degree of integration of the integrated circuit and without deteriorating the characteristics.

[Brief explanation of drawings]

Figure 1 (al~ge) is a schematic cross-sectional view of a semiconductor element shown in Figure 8+1111 to explain one embodiment of the present invention, and Figure 2 is a schematic cross-sectional view of a conventional FET having a high concentration impurity region. be. 1...Heat-resistant gate electrode: &, 2 a a...
···sauce.

Claims (1)

[Claims] a step of forming a two-layer structure in which a first gate electrode is stacked on a gate region on a semiconductor active layer formed on a semiconductor substrate and an insulating film stacked on the first gate electrode; and a step of forming a resist on the entire surface of the semiconductor substrate. a step of applying the resist on the insulating film to expose the upper surface of the insulating film; a step of removing the insulating film with the upper surface exposed; and a step of applying the second gate electrode material to the first gate electrode material. A semiconductor device comprising the steps of: forming a gate electrode on the resist; and removing the resist and a second gate electrode material on the resist. manufacturing method.