JP3035917B2 - Field effect type semiconductor device and method of manufacturing the same - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a highly reliable high-speed semiconductor device and a method for manufacturing the same.

(Prior Art) In recent years, research and development of ultra-high-speed semiconductor integrated circuits using compound semiconductors such as GaAs have been actively conducted. In particular, since the highly controlled growth method such as the molecular beam epitaxy method (MBE method) was established, the research and development of ultra-high-speed semiconductor devices and integrated circuits using high impurity density and ultra-thin epitaxial semiconductor layers have progressed rapidly. ing.

Conventionally, for example, a GaAs field effect transistor (GaAsMESF)
In ET), in order to reduce the parasitic resistance and achieve high-speed operation of the element, ion implantation was performed on a parasitic region outside the gate electrode, and heat treatment was performed to form an electrical resistance layer. In this case, the gate electrode has excellent heat resistance,
In many cases, WSi whose interface with GaAs is stable is used. Usually, the ion implantation of the parasitic region is performed after this WSi processing.
Performed in a self-aligned manner on the Si gate electrode, for example, Si
₃ N ₄ film to 800 ° C. in the protective film, heat treatment at about 20 minutes is performed. However, in practice, the WSi gate electrode and Si ₃ N ₄
It is known that since the thermal expansion coefficient of the film and that of GaAs are significantly different, a stress is generated at the end of the gate electrode, and impurity ions implanted into GaAs cause abnormal diffusion. As a result, the control of the short channel effect becomes insufficient, and it is difficult to shorten the gate length, which is advantageous for speeding up the FET. Incidentally, as a gate electrode material, for example, a two-layer structure of W and WSi may be used in order to reduce the gate resistance, but the above-described problem similarly occurs. Further, in this case, W, WSi and GaAs
Since the stress characteristics of s are different, there is also a problem that the metal film is easily peeled off.

(Problems to be Solved by the Invention) It is an object of the present invention to solve such a problem, to provide a high-speed semiconductor device which controls a short-channel effect, is excellent in reliability, and a method of manufacturing the same.

(Means for Solving the Problem) The configuration of the field-effect semiconductor device of the present invention is characterized by comprising a multilayer electrode gate electrode in which three or more heat-resistant metal layers having mutually different stress characteristics are laminated. .

The method of manufacturing a field-effect semiconductor device according to the present invention includes a step of forming three or more heat-resistant metal layers having different etching characteristics on a semiconductor layer, and a step of forming a lower metal layer by using a gas containing a halogen element. Selectively removing the upper metal layer by using the layer as a stop layer to expose the lower metal layer, ion-implanting the semiconductor layer through the lower metal layer, and subsequently performing a heat treatment. It is characterized by becoming.

Further, the structure of the field-effect semiconductor device of the present invention is such that an electrode comprising a first heat-resistant metal layer, a second heat-resistant metal layer, and a third heat-resistant multilayer metal layer having different etching characteristics on a semiconductor layer. And sequentially removing a part of the third heat-resistant multilayer metal layer using a gas containing a halogen element, using the second heat-resistant metal layer as a stop layer. Exposing the second heat-resistant metal layer in the region of the above, the step of ion-implanting the semiconductor layer through the exposed second heat-resistant metal layer, the step of forming an insulating film, Vertical processing by dry etching to form side walls; and ion implanting again into the semiconductor layer through the exposed second heat resistant metal layer;
And a step of subsequently performing a heat treatment.

Next, the present invention will be described in detail with reference to the drawings.

Embodiment 1 FIG. 1 is a structural sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 1 shows, for example, a metal organic chemical vapor deposition (MOCV) method.
FIG. 4 is a cross-sectional view of a semiconductor crystal grown by using (D method). In FIG. 1, 1 is a high-resistance GaAs substrate and 2 is an undoped
GaAs, 3 is an n-type with an impurity density of 2 × 10 ¹⁸ cm ^-3 and a thickness of 20 nm
GaAs, 4 is an ohmic electrode of Ni / Au / Ge, 5 is WSi,
6 is LaB ₆ and 7 is W. The gate electrode is formed by the metals of the formulas 5, 6, and 7. The gate metals 5, 6, and 7 are formed by a sputtering method, an electron beam gun evaporation method, and a sputtering method, respectively. By making the gate a multilayer structure,
The gate metal resistance Rg can be reduced by about one digit or more compared to the conventional WSi single layer, and the maximum available gain is greatly improved.
Further, it is possible to reduce by inserting the LaB ₆ 6 stress generated at the interface between WSi5 and W7, can control the peeling of the metal film, was formed with high reliability gate electrode.

Example 2 FIGS. 2 (a) to 2 (e) show main steps of a method for manufacturing a semiconductor device according to an example of the present invention.

As shown in FIG. 2 (a), undoped GaAs 2 was deposited on a high-resistance GaAs substrate 1 at a thickness of 0.5 μm and an impurity density of 2 × 10 ¹⁸ cm ⁻³ by using a molecular beam epitaxy method (MBE method). After successively epitaxially growing n-type GaAs3 with a thickness of 20 nm,
The WSi5 as a gate electrode material is formed by sputtering, then forming a LaB ₆ by vapor deposition, to form a W7 further by sputtering. Next, as shown in FIG. 2B, W7 is processed by dry etching using a photoresist (PR) 8 as a mask and a CF ₄ gas 9. At this time, the etching rate of the LaB ₆ 6 is set to be sufficiently smaller than that of W7.
For example, it is desirable that the power is about 100 W, the gas pressure is about 1 mTorr, and the gas flow rate is about 10 SCCM. Next, as shown in FIG. 2 (c), parasitic regions WSi5 and LaB ₆ 6 through Si ion 11 5 × 10 ¹³ cm
^-2 Inject under the condition of 100keV. After that, WSi5
And leaving the LaB _{6 6,} 800 ℃, a heat treatment is carried out for 20 minutes. Next, as shown in FIG. 2 (d), the LaB ₆ 6, for example, after removal by using Ar ion milling method to be processed by dry etching method WSi5 using CF ₄ gas. Finally, as shown in FIG. 2 (e), an ohmic electrode 4 of Ni / Au / Ge
To form

In this embodiment, a low-resistance parasitic region can be formed in the gate electrode in a self-aligned manner. This is extremely advantageous for improving the transconductance of the device. Further, since the same material as the gate metal, WSi5, can be used for the protective film for the heat treatment, the diffusion of impurity ions due to stress concentration at the end of the gate electrode, which has been a problem in the conventional method, can be prevented. As a result, even in a device having a short gate of 0.5 μm, good pinch-off characteristics, uniformity of characteristics, and reproducibility were obtained. In the present embodiment,
To perform the processing of W7 which is a prototype of a gate electrode pattern of the LaB ₆ 6 as the automatic stop layer, the uniformity of the in fine gate length into the substrate surface was also very good.

Third Embodiment FIGS. 3A to 3F show a main part manufacturing process of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1 is a cross-sectional view of a semiconductor crystal grown using, for example, a metal organic chemical vapor deposition (MOCVD) method. In FIG.
1 is a high-resistance GaAs substrate, 2 is undoped GaAs, 3 is n-type GaAs having an impurity density of 2 × 10 ¹⁸ cm ^-3 and a film thickness of 20 nm, and 4 is Ni / A
Ohmic electrode of u / Ge, 5 is WSi, 6 is LaB ₆ , 7 is W. At this time, the gate electrode is formed by the 5 and 7 metals.

As shown in FIG. 3 (a), n-type GaAs conductive layer after the epitaxial growth, the WSi5 as a gate electrode material is formed by sputtering, followed LaB ₆ 6 was formed by vapor deposition, W7 further by sputtering Form. Next, as shown in FIG. 3B, using a photoresist (PR) 8 as a mask, a CF4 gas 9
W7 is processed by a dry etch method. At this time, LaB ₆
The etching rate of 6 is set to be sufficiently smaller than that of W7. For example, power 100W, gas pressure 1mTor
r, a gas flow rate of about 10 SCCM is desirable. Next, as shown in FIG. 3C, 300 nm of SiO ₂ is deposited on the entire surface by a CVD method, and the SiO ₂ is processed by anisotropic dry etching using CF 4 gas to form a gate sidewall 10. Further, Si ions 11 in the parasitic region through WSi5 and ^{_{LaB 6 6 5 × 10 13 cm}} -2, 1
Inject under the condition of 00keV. Next, as shown in FIG. 3 (d), after removing the gate side wall by HF, a parasitic region is formed.
WSi ₅ and LaB ₆ to 6 Si ions 12 through 5 × 10 ¹² cm ^-2, 50k
Inject under eV conditions. Then, parasitic regions WSi5 and LaB ₆
Heat treatment is performed at 800 ° C. for 20 minutes while 6 is left. next,
As shown in FIG. 3 (e), the LaB ₆ 6, for example, after removal by using Ar ion milling method to be processed by dry etching side of WSi5 using CF ₄ gas. Finally, as shown in FIG. 3 (f), an ohmic electrode 4 of Ni / Au / Ge is formed.

In this embodiment, since the gate side wall SiO ₂ 10 is deposited on the metal and dry-processed, direct damage to the semiconductor layer can be extremely reduced. Thereby, the frequency dispersion of the device characteristics could be controlled. In addition, since the contact point between the gate electrode WSi layer 5 and the semiconductor layer 3 in the ion-implanted parasitic portion has a low impurity density, the short channel effect can be controlled. Further, it was confirmed that the other effects described in Example 2 could be maintained as they were.

Note that in the second and third embodiments,
The implantation of Si ions were performed through LaB ₆ 6, it may be carried out after removal of the LaB ₆ 6. Further, before the heat treatment, a protective film such as Si ₃ N ₄ may be formed to control the external diffusion of the semiconductor element. Further, in addition to the gate electrode material used in this embodiment, for example, heat-resistant metal silicide, boride, carbide, or the like such as WSiN, WAl, WN, WAlN, MoSi, and TaSi may be used. These metal materials must withstand the heat treatment temperature for the electrical activation of the implanted ions, and usually have a heat resistance of 500 ° C. or higher. Furthermore,
The present invention can be used not only for forming FETs but also for forming emitter electrode portions of bipolar transistors, for example. In addition, the present invention is similarly effective for other semiconductor materials such as InP and Si, and other devices such as a high electron mobility transistor (HEMT).

(Effects of the Invention) As described above, in the semiconductor device having the structure described in claim 1, the gate electrode has a multilayer structure, so that a gate electrode having low gate metal resistance and low stress can be obtained. According to the method of manufacturing a semiconductor device according to the second aspect of the present invention, the ion implantation for forming the contact layer is performed through the metal, and the metal can be used as it is as the recovery annealing protection film after the ion implantation. This suppresses the diffusion of impurity ions and damage due to ion implantation, and provides a manufacturing method with excellent reproducibility. According to the manufacturing method of claim 3, since the gate sidewall insulating film is formed on the metal, damage to the semiconductor layer during dry processing of the gate insulating film can be suppressed.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a principal part of a semiconductor device of the present invention, and FIGS. 2 (a) to 2 (e) and FIGS. 3 (a) to 3 (f) show the present invention. 13 is a main part manufacturing process of the method for manufacturing a semiconductor device according to the example. 1 GaAs substrate, 2 undoped GaAs, 3 n-type Ga
As, 4 ... Ohmic electrode, 5, 6, 7 ... Gate electrode, 8
…… Photoresist, 9,14 …… Etching gas, 10 ……
SiO ₂ , 11, 12... Implanted ions, 13.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 29/812

Claims (6)

(57) [Claims] 1. A heat-resistant metal layer having different stress characteristics from each other.
At least the lowermost layer and the uppermost layer are formed of a metal containing tungsten, and the intermediate layer is provided with a multilayer electrode formed of a boron compound alloy, a carbide alloy, or a metal sulfide alloy as a gate electrode. Field effect type semiconductor device. 2. The field effect semiconductor device according to claim 1, wherein the intermediate layer of said multilayer electrode is lanthanum boride. 3. The multi-layer electrode is formed of tungsten silicide (WS).
i), lanthanum hexaboride (LaB ₆ ), tungsten (W)
3. The field effect type semiconductor device according to claim 2, wherein three layers are stacked. 4. A step of forming three or more heat-resistant metal layers having different etching characteristics on a semiconductor layer, and using a gas containing a halogen element, selectively using the lower metal layer as a stop layer and selectively using the upper metal layer. A step of exposing the underlying metal layer, a step of ion-implanting the semiconductor layer through the underlying metal layer, and a subsequent heat treatment step. Production method. 5. A first heat-resistant metal layer and a second heat-resistant metal layer having different etching characteristics from each other on a semiconductor layer.
Sequentially forming electrodes made of a heat-resistant metal layer, and selectively using a gas containing a halogen element to partially cover the third heat-resistant metal layer using the second heat-resistant metal layer as a stop layer. Removing the second heat-resistant metal layer in a part of the region, implanting ions into the semiconductor layer through the exposed second heat-resistant metal layer, and forming an insulating film. Vertical processing of the insulating film by anisotropic dry etching method,
A field-effect-type semiconductor device comprising at least a step of forming a side wall, a step of implanting ions again into the semiconductor layer through the exposed second heat-resistant metal layer, and a step of subsequently performing a heat treatment. Manufacturing method. 6. The first heat-resistant metal layer is made of tungsten silicide (WSi), the second heat-resistant metal layer is made of lanthanum hexaboride (LaB ₆ ), and the third heat-resistant metal layer is 6. The method for manufacturing a field-effect semiconductor device according to claim 4, wherein said semiconductor device is made of tungsten (W).