JPH081910B2 - Field effect type semiconductor device and method of manufacturing the same - Google Patents

Description

The present invention relates to a field effect semiconductor device and a method for manufacturing the same.

[Conventional technology]

As a semiconductor device, for example, a Schottky barrier field effect transistor (hereinafter referred to as MESFET) using gallium arsenide (GaAs), a structure shown in FIG. 3 is known. In FIG. 3, 1 is a heat-resistant gate electrode, 2a
Is a source electrode, 2b is a drain electrode, 3 is an operating layer made of GaAs, 4b is a high-concentration impurity semiconductor crystal layer (hereinafter referred to as a high-concentration impurity layer), 5 is a SiO ₂ film, and 6 is a semi-insulating GaAs substrate. .

In the MESFET having this structure, the high concentration impurity layer
The presence of 4b reduces the series parasitic resistance of the source and drain, obtains high transconductance and low on-resistance, and enables high-speed operation of the FET. At present, such FETs or integrated circuits using FETs are being manufactured.

[Problems to be solved by the invention]

When manufacturing the above-mentioned GaAs MESFET, the high-concentration impurity layer 4
b is formed by selective growth using a gate electrode and a sidewall made of an insulating material formed on the side surface of the gate electrode as a mask. The side wall is provided to prevent the high-concentration impurity layer 4b and the gate electrode 1 from coming into contact with each other and preventing the breakdown voltage of the gate electrode from decreasing. However, since the side wall is provided, a high resistance region is formed under the side wall, so that the parasitic resistance of the source and drain is not sufficiently reduced.

Further, when the concentration of the high-concentration impurity layer 4b is lowered, it is possible to prevent deterioration of the gate breakdown voltage when the gate electrode and the high-concentration impurity layer are in contact with each other, and it is possible to manufacture the FET without using the side wall. However, since the sheet resistance of the high concentration impurity layer 4b increases, the parasitic resistance cannot be sufficiently reduced in this case as well.

Further, as shown in FIG. 4, in order to reduce the resistance of the region under the side wall, ion implantation is performed using only the gate electrode 1 as a mask before forming the high concentration impurity layer 4b, and the high concentration impurity layer 9 is formed on the GaAs substrate 6. There is a method of forming. However, when the ion implantation is performed in this way, the short channel effect becomes remarkable, and there is a problem that it becomes difficult to control the threshold voltage when manufacturing an FET having a short gate length.

An object of the present invention is to provide a field effect semiconductor device in which the series parasitic resistance of the source and drain is reduced without causing an increase in the short channel effect, and a manufacturing method thereof.

[Means for solving problems]

A field-effect semiconductor device according to a first aspect of the present invention is a one-conductivity-type semiconductor operating layer formed on a semi-insulating semiconductor substrate, a gate electrode formed on the semiconductor operating layer, and a side surface of the gate electrode. A one-conductivity-type low-concentration impurity layer formed on the operating layer, a sidewall made of an insulating film formed on the low-concentration impurity layer and on a side surface of the gate electrode, and a low-concentration impurity layer in contact with the sidewall. And a one-conductivity-type high-concentration impurity layer provided on the layer.

A method of manufacturing a field-effect semiconductor device according to a second aspect of the present invention comprises a step of forming a one-conductivity-type semiconductor operating layer by ion implantation of impurities into a semi-insulating semiconductor substrate, and a step of forming a gate electrode on the semiconductor operating layer. And a step of forming a one-conductivity-type low-concentration impurity layer in the source / drain regions on the semiconductor operation layer using the gate electrode as a mask, and an insulating film on the low-concentration impurity layer and on the side surface of the gate electrode. It includes a step of forming a side wall and a step of forming a one-conductivity-type high-concentration impurity layer on the low-concentration impurity layer by using the gate electrode and the side wall as a mask.

[Action]

The present invention makes it possible to significantly reduce the series parasitic resistance by forming the source / drain by using two selective growth layers including a low concentration impurity layer and a high concentration impurity layer.

Since the high-concentration impurity layer reduces the sheet resistance of the source and drain regions, and the low-concentration impurity layer is introduced below the side wall in addition to the operating layer, an increase in parasitic resistance is suppressed as compared with the conventional case. Particularly, in the enhancement type FET, the resistance of the operating layer is large, and the effect of reducing the resistance by introducing the low concentration impurity layer is large.

Further, in the present invention, since the ion implantation layer is not used for the source / drain, the short channel effect does not increase.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIGS. 1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1A, Si ions are selectively ion-implanted on a semi-insulating GaAs substrate 6 under the conditions of 50 keV and a dose amount of 2 × 10 ¹² cm ^-2 to form a CVD SiO ₂ film. 800 as a protective film
Heat treatment was performed at 20 ° C. for 20 minutes to form an operating layer 3 made of GaAs. Next, after removing the protective film, the tungsten silicide (WS ₁ ) is deposited on the GaAs operating layer 3 and the GaAs by sputtering.
After depositing a thickness of 0.5 μm on the entire surface of the substrate 6, WS ₁ was processed by a dry etching method using carbon tetrafluoride to form a gate electrode 1.

Next, as shown in FIG. 1B, after the SiO ₂ film 7 is formed on a predetermined portion of the GaAs substrate 6, the gate electrode 1 and the SiO ₂ film 7 are formed.
Using the mask as a mask, a low-concentration impurity layer 4a having an impurity concentration of 2 × 10 ¹⁷ cm ^-3 is formed in the source / drain regions by MOCVD.
It was formed by selective growth of a film thickness of 0.15 μm at 00 ° C.

Next, after removing the SiO ₂ film 7, as shown in FIG. 1C, a SiO ₂ film is deposited on the entire surface by a CVD method to a film thickness of 0.3 μm, and then CF ₄ is used with the resist film as a mask. The SiO ₂ film is processed by the anisotropic etching used and only the side surface of the gate electrode 1 is processed.
The SiO ₂ film 5 is left. Next, after removing this resist film,
2 × using the gate electrode 1, SiO ₂ film 5 and SiO ₂ film 8 as a mask
A high-concentration impurity layer containing Si of 10 ¹⁸ cm ^-3 was formed by MOCVD to a thickness of 0.3.
μm was selectively grown.

Finally, as shown in FIG. 1D, AuGe-based source and drain electrodes were formed on the high-concentration impurity layer, and the fabrication of the FET was completed.

In addition to the above-mentioned FET, conventional FETs shown in FIGS. 3 and 4 were also manufactured. In the FET of FIG. 3, the high-concentration impurity layer 4b
Has a concentration of 2 × 10 ¹⁸ cm ^-3 and a film thickness of 0.3 μm. Moreover, in the FET of FIG. 4, the high concentration impurity layer by ion implantation is 50 ke
After implantation under the condition of V, 7 × 10 ¹² cm ^-2 , SiN was formed as a protective film by heat treatment at 750 ° C. for 20 minutes.

Select each 100 of these FETs to find the mutual conductance gm
The second is the result of examining the gate length dependence of the threshold voltage V _T and
Shown in the figure. It is clear from FIG. 2 that the FET according to this embodiment has a high gm while suppressing the short channel effect as compared with the conventional FET.

Although the impurity layer is selectively grown by using the MOCVD method in the above-mentioned embodiments, it does not depart from the gist of the present invention to use other growth methods such as LPE and MBE.

〔The invention's effect〕

As described above, the present invention reduces the series parasitic resistance without increasing the short channel effect by forming the source / drain using the two types of selective growth layers of the low concentration impurity layer and the high concentration impurity layer. A field effect semiconductor device can be obtained.

[Brief description of drawings]

1 (a) to 1 (d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, and FIG. 2 is a view showing FET characteristics of the embodiment and a conventional example, 3 and 4 are sectional views of a conventional MESFET. 1 ... Gate electrode, 2a ... Source electrode, 2b ... Drain electrode, 3 ... Operating layer, 4a ... Low concentration impurity layer, 4b ... High concentration impurity layer, 5 ... SiO ₂ film, 6 ... GaAs substrate, 7,8 ...
… SiO ₂ film, 9 …… High-concentration impurity layer.

Claims (2)

[Claims] 1. A one-conductivity-type semiconductor operating layer formed on a semi-insulating semiconductor substrate, a gate electrode formed on the semiconductor operating layer, a side surface of the gate electrode and formed on the operating layer. A conductive type low-concentration impurity layer, a sidewall made of an insulating film formed on the low-concentration impurity layer and on a side surface of the gate electrode, and a sidewall provided in contact with the sidewall and on the low-concentration impurity layer. A field effect semiconductor device comprising: a conductive high concentration impurity layer. 2. A step of forming a one conductivity type semiconductor operating layer by ion implantation of impurities into a semi-insulating semiconductor substrate, a step of forming a gate electrode on the semiconductor operating layer, and the semiconductor using the gate electrode as a mask. A step of forming a one conductivity type low concentration impurity layer in the source / drain regions on the operating layer,
Forming a side wall made of an insulating film on the low concentration impurity layer and on the side surface of the gate electrode; and forming one conductivity type high concentration impurity layer on the low concentration impurity layer using the gate electrode and the side wall as a mask. A method of manufacturing a field effect semiconductor device, comprising: