JPS62245678A - Manfacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To manufacture a high speed FET by a method wherein p layers are formed on the sidewalls of n<+>source.drain layers while n<+>layers are formed deeper than an n operation layer on the p layers to reduce the contact space with the source.drain for reducing the capacity. CONSTITUTION:An n type operation layer 12, a WN film 13, an SiO2 mask 20 are laminated on a semi-insulating GaAs substrate 11 to perform side etching by RIE using CF4+O2. After the side etching process, n<+>layers 16, 17 are formed by implanting ions deeper than the n layer 12. Next, the mask 20 is removed and Si ions are implanted to form n' layers 14 and then Be ions are implanted to form p layers on the sidewalls of n<+>layers 16, 17 and below the n' layers 14. After annealing process, AuGe made ohmic electrodes 18, 19 are formed to complete a selfalignment type GaAs-FET. The p layers 15 restrain the current from flowing through the substrate 11 holding the threshold value almost unchanged up to the gate length of 0.5mum. In such a constitution, the short channel effect can be avoided by a simple process reducing the capacity to manufacture a high speed FET.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a field effect transistor using a semi-insulating compound semiconductor substrate.

(Prior art) A Schottky gate field effect transistor (In31T) using a semi-insulating GaAs substrate is made of 03As.
Because of its high electron mobility, it is attracting attention as a microwave device and as a basic device for GaAs I(:'), which enables ultrahigh-speed operation that cannot be achieved with current St.

In order to improve the performance of this MESF'ET, it is essential to reduce the series resistance S and shorten the gate length.

In order to reduce this Rs, in recent years, M E S F E T having a structure as shown in FIG. 4 1a) has come to be generally used. 3 in the figure, 41 is semi-insulating G a A 8
It is a substrate, and an fcn type operating layer 42 is formed on its surface.

A gate 43 is formed to form a semiconductor contact with the active layer 42. n+ type source.

Three drain regions 44, 45 are formed in self-alignment with the gate electrode 43 by ion implantation, and source electrodes 46, 45 are formed on the surface of each drain region 44, 45. A drain 11L and other drains 47 are formed.

When such a Gaps-MESFgT is miniaturized, the distance between the source electrode 46 and the drain electrode 47 becomes narrower, and the effect of adding the high-order 4 field between them and the effect of the source region 44 and the drain region 45 being extremely close to each other combine to cause In addition to the W current flowing through the active layer 42, which is a channel, the current flowing through the substrate side increases. Therefore, there is a shift of the threshold voltage vth to the negative side and a decrease in Kj[, which represents performance. A so-called short channel effect is caused. Therefore, Figure 4 +
There is a method of forming the opposite conductivity type 1i (P9ν region) under the n+ type source e-drain regions 44, 45 and the active layer 42 as shown in b), but a vcP type region is formed below the n+ type region. Therefore, there is a capacitance, which becomes a problem when fast-tracking F'ET. To avoid this problem, various methods have been considered to form a reverse conductive layer only on the sidewalls of the Vcn+ layer, but the process becomes complicated. It has been difficult to easily manufacture FETs suitable for integrated circuits with good reproducibility.

(Problems to be Solved by the Invention) The present invention prevents the source-drain regions from becoming extremely close to each other and the current flowing through the substrate side from increasing due to the application of a high electric field as ME3FBT is miniaturized. , which reduces the short channel effect. Furthermore, the capacitance, which is a problem in high-frequency operation of the FF1T, can also be reduced.

The purpose of the present invention is to provide a method for manufacturing FETs with such characteristics easily and with good reproducibility by adding only two ion implantation steps to the conventional Selfaline process without employing complicated processes. .

[Structure of the invention]

(Means for Solving the Problems) A field effect transistor according to the present invention has a structure in which an active layer of a first conductivity type is formed on the surface of a semi-insulating compound semiconductor substrate, and a gate electrode is formed on the surface. , a manufacturing method for providing an offset between a gate electrode and a high a-degree first conductivity type region of a source/drain, and forming a first conductivity type layer in this region and a second conductivity type layer below it. First, an active layer of the first conductivity type is formed, a metal serving as a gate electrode is deposited on the surface of the active layer, and gate processing is performed using a mask for forming the gate electrode. At this time, side etching is introduced into the gate electrode part, and the first part of the source/drain region is etched.
A conductive type high concentration layer is formed by ion implantation. After that, the mask used to process the gate electrode is removed, and the first conductivity type layer is formed using the gate electrode as a mask! A biconductivity type layer is formed by ion implantation.

According to this manufacturing method, steps such as mask insertion are not required to form the second conductivity type layer, and only two ion implantation steps are added compared to the conventional self-line type FET [1 m].

(Function) According to the method of the present invention, by adding only two ion implantation steps to the conventional process, a layer of the opposite conductivity type is formed on the sidewall or periphery of the source/drain first conductivity type high concentration layer. Because of its presence, current seeping into the substrate from the drain region can be suppressed.

And, even though an offset structure is adopted by making the first conductive layer provided above the second conductivity type region deeper than the active layer or having a higher concentration,
The source-gate series resistance can be significantly reduced.

Furthermore, by selecting the ion implantation conditions for the second conductivity type layer, it is possible to reduce the contact area between the source and the drain with the first conductivity type high concentration -.

Capacitance, which is a problem when FET operates at high speed, can be reduced.

(9N! Example) The present invention will be explained in detail below.

FIG. 1 shows an example of a GaAs-MESFBT.

Reference numeral 11 denotes a semi-insulating Ga-AS substrate with a resistivity of about 10"-10" Ωcm, on the surface of which a p-type (first conductivity type) active layer 12 is formed which becomes a channel region. For example, a Schottky gate (1i, %13) made of a WN film of about 2000A is formed.

An n-type source region 16 and a drain region 17 are formed at a higher degree and deeper than the active layer 12 by ion implantation at a location offset by Ln+-p on both sides from the gate electrode 13.
is formed. Then, an n'-type layer (first conductive layer) 14 is formed deeper than the active layer 12 or has a higher concentration, and below it is a p-type (second conductor 5 layer) layer 15, which will be described later. It is formed by ion implantation.

18*19 are source and drain ohmic electrodes, respectively.

This will be explained in detail with reference to FIGS. 2re) to (e). First, 81 ions were applied to the semi-insulating GaAs substrate 11 using 5QK.
eV.

The n-type operating layer 12 is formed by ion implantation under the condition of 3 x 10' and 7 cm. Next, put two WN films on top of this.
00OA is formed, and a mask 20 for forming the gate electrode 5 is formed using a SiOs film (see FIG. 2).
a)).

Thereafter, the WN film 13 is processed using a known dry etching technique using the Sto film 20 as a mask. At this time, s
CF420 cc/min +0110cc/mI
By processing with RIB at n @ 20 Pa and % 50 W, the side etch of L n 10-,9 is 0.2μ
Apply muff.

StO! With the mask 19 left in place, n+ type source/drain regions 16 and 17 are formed. At this time.

For example, the ion implantation conditions are 120 K, eV #5.
By selecting X 10'''/cmlK, the operating layer 12
It becomes deeper at higher concentrations (Figure 2 [b)].

After that, the 5in1 film 20 on the upper layer of the gate electrode is removed and the first
Conductive 11n'14 60KeV + 2x12cm"
SN ions are implanted under the following conditions (Fig. 2 (cl)), and then Be, which becomes the conductive gL layer, is implanted at 90 KeV + 6
Ion implantation is performed using the gate electrode 13 as a mask under the condition of IO''/c-, and the source/drain region 15 is
, 16 and the lower part of n'@14 (FIG. 2(d)).

After this, annealing was performed for 800 min to activate the implanted impurities.
Source by AuG6 alloy
Drain ohmic electrodes 18 and 19 are formed to complete the self-line type GaAs-MESFET (FIG. 2(e)).

In the MESFBT of this example, only the P-type layer 1 is formed on the walls of the source and drain regions 16 and 17111I under the 01 layer 14.
5 is formed, it acts as a potential barrier against electrons and can suppress the current flowing through the substrate.

Therefore, as shown in FIG. 3, the fluctuation of the threshold voltage vth with respect to the gate length L9 is greatly improved by two points, and there is almost no change in Vth up to a gate length of 0.5 μm.

In addition, the source series resistance Rs is 40Ω even though an offset is provided between the n+ region and the “−” and operation @1.
/w#=about 10 μm, which was not much different from the conventional type (FIG. 4(al)). This is because the 0 layer has a higher concentration than the active layer.

Using this process, we prototyped a ring oscillator and found that the delay time per gate was approximately 20q6 compared to the conventional method.
τr)d=20 ps was obtained.

This is achieved by suppressing short channel effects and reducing capacitance.

As described above, according to the present invention, the short channel effect can be prevented by an idle process, and the capacitance, which is a problem during high-speed operation of FETs, can be reduced.

The present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications.

For example, the gate electrode may be made of any material that forms a good Schottky barrier with n-type U a A & and maintains its characteristics even after heat treatment, such as WN or the like.

W * W S l 1W-A j -M o -M
o Ai 'J: (!: I can make an illustration for you.

The implanted impurities include p-type impurity S e w S in addition to St.
In the case of p-type, MIi etc. can be used in addition to Be.

Furthermore, although the embodiments have been described exclusively for n-channel cases, the present invention can also be applied to p-channel cases. In addition to MESFETs, the present invention can be similarly applied to junction FETs, and can be similarly applied when semi-insulating compound semiconductor substrates other than 011A3 are used.

〔Effect of the invention〕

According to the method of the present invention, by adding only two ion implantation steps to the conventional process, the source/drain high concentration layer can be separated from the drain region due to the presence of an opposite conductivity type layer on the sidewall or periphery. Current seeping into the substrate can be suppressed.

In the upper layer of %2nd conductivity type 1-, deeper than the active layer,
Or, because there is a first enriched layer formed at a high concentration,
Despite the offset, the source series resistance Rs
is reduced.

Further, mask alignment for forming these layers is not necessary, and by simply removing the mask used during gate processing, the layers are formed in a self-aligned manner with the gate and the first conductivity type high concentration region.

Furthermore, by selecting the ion implantation conditions for the second conductivity type layer, the contact area αl) with the first conductivity type high concentration region can be reduced. Therefore, it is possible to reduce the capacitance, which is a problem when FETs operate at high speeds.

[Brief explanation of drawings]

Fig. 1 is a diagram showing a MESFET according to an embodiment of the present invention, Fig. 2 (a) to (e) are diagrams showing its manufacturing process, and Fig. 3 is a diagram showing the gate length dependence of the threshold voltage prototyped according to this embodiment. FIG. 4 is a diagram showing the conventional MESFgT. 11: Semi-insulating GaAs substrate, 12: 0-type operating layer. 13-- Schottky gate electrode, 14... n'-type layer. 15...p type layer, 16...n+ type source region, 17
. . . n+ type drain region, t8tt9 . . . Ohmic electrode, 20 . . . S10. film. Agent Patent Attorney Ken Nori Chika Kikuo Takehana (One Keyword) L:f (Prn) Figure 3 Figure 2 Figure 4rEi

Claims (1)

[Scope of Claims] (1) A step of forming an active layer of a first conductivity type on the surface of a semi-insulating compound substrate, depositing a gate metal on the surface of the active layer, and applying a mask for forming a gate electrode. In the step of processing the gate electrode using the ion-coated metal, and during the formation of the gate electrode, side etching is introduced, and the highly concentrated source/drain regions of the first conductivity type are implanted by ion implantation while leaving the mask for gate processing. a step of forming a second conductivity type layer and a first conductivity type layer by ion implantation using the gate electrode as a mask after removing the gate processing mask, and forming an ohmic electrode on the surface of the source/drain region. A method for manufacturing a field effect transistor, comprising the steps of: (2) When forming the first conductivity type layer using the gate electrode as a mask, the first conductivity type layer is formed deeper than the first conductivity type operating layer or is formed at a higher concentration. A method of manufacturing a field effect transistor. (3) When forming the second conductivity type layer using the gate electrode as a mask, the second conductivity type layer is formed shallower than the first conductivity type high concentration region and deeper than the first conductivity type layer. A method for manufacturing a field effect transistor according to section 1.