JP2867422B2 - Field effect transistor and method for manufacturing the same - Google Patents

Description

The present invention relates to an ultra-high-speed field-effect transistor and a method for manufacturing the same.

(Prior Art) In recent years, research and development of high-speed field-effect transistors using compound semiconductors such as GaAs have been vigorously conducted.
Generally, in order to improve the performance of a field effect transistor (FET), it is important to shorten the gate length and greatly reduce the parasitic resistance. Further, from the viewpoint of practical use, it is necessary to simultaneously suppress the short channel effect and the withstand voltage degradation. From such a viewpoint, for example, in the case of a GaAs MESFET, as shown in FIG. 4, an LDD (l) which forms two parasitic regions having different impurity densities between a source electrode, a drain electrode, and a gate electrode.
(ightly-doped-drain) structure is used. In FIG. 4, 41 is a semi-insulating GaAs substrate, 42 is a second n-type parasitic region, 43 is a first n-type parasitic region, 44 is an n-type channel, 45
Is a source electrode, 46 is a gate electrode, and 47 is a drain electrode. Conventionally, the second and first n-type parasitic regions 42 and 43 are formed by implanting the same type of ions (for example, Si ions), and the ion dose is smaller than that of the former second n-type parasitic region. And the sheet resistance was set low.

(Problems to be Solved by the Invention) However, in the case of the prior art, since two parasitic regions are formed using the same kind of ions, it is not sufficient to suppress the short channel effect and the deterioration of the withstand voltage and to improve the mutual conductance. It was difficult. An object of the present invention is to solve such a problem and to provide an ultra-high-speed field-effect transistor having a high withstand voltage and a large transconductance, and a method of manufacturing the same.

(Means for Solving the Problems) The field effect transistor according to the present invention has a structure in which a first n-type parasitic region containing a group IV element is provided between a source electrode, a drain electrode, and a gate electrode. a second e-type parasitic region including a group VI element connected to the n-type parasitic region, wherein the first n-type parasitic region is formed below the gate electrode;
The second n-type parasitic region is connected to a channel region of an n-type semiconductor made of a group III element and a group V element, and is electrically connected to the source electrode and the drain electrode.

Further, the structure of the method for manufacturing a field-effect transistor of the present invention is such that a heat-resistant metal is formed on a semiconductor layer having an n-type channel and formed of a single or a plurality of semiconductors including Group III and Group V elements. Forming a gate electrode, forming an insulating film, removing the insulating film other than the side wall of the gate electrode, implanting Group VI element ions using the gate electrode and the insulating film as a mask, Removing the insulating film on the side wall of the gate electrode, implanting group IV element ions using the gate electrode as a mask, and electrically activating the implanted ions by performing a short heat treatment. Features.

(Operation) The principle of the field effect transistor of the present invention and the manufacturing method thereof is that, for example, different donor ion species (Group IV and Group VI element ions) implanted in GaAs have different electron densities after a short-time high-temperature heat treatment. It is based on the experimental results of forming a distribution. FIG. 2 shows the electron density distribution in the substrate depth direction when S ions and Si ions are implanted into a GaAs substrate and subjected to a short-time heat treatment at 900 ° C. for 5 seconds. As can be seen from this figure, when Si ions are implanted, almost
According to the distribution according to the LSS theory, the electron density of the peak is about 10 ¹⁸ cm ^-3 . On the other hand, when S ions are implanted,
Although the diffusion is slightly large and the distribution greatly deviates from the LSS theory, the electron density of the peak is about 3 × 10 ¹⁸ cm ^−3, which is about three times, and has a peak on the surface side. Such a property is
Basically, it was confirmed that it was almost the same for homologous elements in the periodic table. Therefore, in the device having the conventional structure shown in FIG. 4, the parasitic resistance is greatly increased by implanting a high dose of a group VI element (for example, S) ion capable of increasing the electron density into the second n-type parasitic region 42. The short channel effect and the deterioration of the withstand voltage can be suppressed by implanting a low-dose group IV element (for example, Si) ion with low diffusion into the first n-type parasitic region 43. In the case of manufacturing the field-effect transistor of the present invention, it is important to minimize diffusion, and therefore, it is necessary to perform heat treatment at a temperature of 650 ° C. or more for a short time of about 2 minutes or less. desirable.

Embodiment 1 Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a cross-sectional view of a main part structure of a field-effect transistor according to one embodiment of the present invention. In FIG. 1, 1 is a semi-insulating GaAs substrate, 2 is an undoped GaAs buffer layer, 3 is an N-type GaAs, 4 is an undoped A1 _0.3 Ga _0.7 As, and 5 is a second n containing a group VI element S. A type parasitic region, 6 is a first n-type parasitic region containing a group IV element Si, 7 is a source electrode made of AuGe / Ni, 8 is a gate electrode made of WSi, and 9 is a drain electrode made of AuGe / Ni. The second n-type parasitic region 5 is ion-implanted under the conditions of a dose of S ions of about 5 × 10 ¹³ cm ⁻² and an accelerating voltage of about 50 keV.
The ions are implanted under the conditions of an ion dose of about 1 × 10 ¹³ cm ⁻² and an acceleration voltage of about 30 keV. The heat treatment is performed at 900 ° C. for 5 seconds using a halogen lamp.

Representative examples of the film thickness and impurity density of each semiconductor layer in the present embodiment are as follows: Symbol thickness (A) Impurity density (× 10 ¹⁸ cm ⁻³ ) 25000 undoped 3 100 2 250 undoped.

In the fabricated FET having a gate length of 0.5 μm, the transconductance is 500 mS / mm, and the gate reverse breakdown voltage is 10
V, the threshold voltage Vt is 0.1 V, the standard deviation of Vt over the entire 2-inch substrate is 20 mV, and the difference from the Vt of the FET having a gate length of 5 μm is about 50 m.
V. As described above, a short-channel effect is sufficiently suppressed as compared with the related art, and an FET having high uniformity, high withstand voltage, and large transconductance can be realized.

In order to further reduce the parasitic resistance, a GaAs or InGaAs layer having a high donor impurity density is selectively grown on the second n-type parasitic region 5 using, for example, metal organic chemical vapor deposition (MOCVD). A source electrode and a drain electrode may be formed on this layer.

Further, the principle of the field effect transistor according to the present invention can be applied not only to the structure of this embodiment but also to a GaAs Schottky junction field effect transistor (MESFET), a high mobility electron transistor (HEMT), and the like. It is obvious. In addition, the present invention can be applied to other semiconductor materials including Group III and Group V, such as InGaAs and InP. Further, the group VI element introduced into the first n-type parasitic region may be Se, Te, and the group IV element introduced into the second n-type parasitic region may be Ge, Sn, or the like.

Next, examples of the method for manufacturing a field effect transistor according to the present invention will be described.

Embodiment 2 FIG. 3 shows a main part manufacturing process of a method for manufacturing a field effect transistor according to one embodiment of the present invention. FIG. 3 (a)
It is sectional drawing of a semiconductor crystal. In a third diagram (a), an undoped on a semi-insulating GaAs substrate 1 GaAs31, the A1 _0.3 Ga _0.7 As _32, n-type undoped GaAs 3, undoped A1 _0.3 Ga
_0.7 As4 was grown using molecular beam epitaxy (MBE).
Each grows continuously. Here, 32 is provided for suppressing the short channel effect. Next, after separating the elements by mesa etching, WSi is deposited by a sputtering method and dry-processed using a photoresist as a mask to form a gate electrode 8. Next, as shown in FIG.
The gate electrode sidewall 33 is formed by anisotropic dry processing by depositing SiO ₂ by the method, and using this as a mask, S ions 34 are applied at a dose of about 9 × 10 ¹³ cm ⁻² and an acceleration voltage of about 50 keV. Inject under conditions. Next, as shown in FIG. 3 (c), after removing the gate electrode side wall 33 with an etching solution, the Si ions 35 are exposed to a dose of about 1 × 10 ¹³ cm ⁻² and an acceleration voltage of about 30 keV. Inject with. Then use an arc lamp at 850 ° C, 30
Heat treatment for a short time of 2 seconds. Next, as shown in FIG. 3D, AuGe / Ni is deposited and alloyed by heat treatment to form a source electrode 7 and a drain electrode 9. still,
Typical examples of the film thickness and impurity density of each semiconductor layer in the present embodiment are shown below: Symbol thickness (A) Impurity density (× 10 ¹⁸ cm ⁻³ ) 31 5000 undoped 32 500 undoped 3 100 2 250 undoped is there. The performance of the field-effect transistor obtained in the present embodiment is also excellent as in the case of the first embodiment, and the short-channel effect is sufficiently suppressed, high uniformity, high breakdown voltage, and large An FET with transconductance has been realized. Considering the reproducibility of the experimental results, it is desirable that the heat treatment for activation after ion implantation be performed at 650 ° C. or higher within 2 minutes.

(Effects of the Invention) As described above, according to the present invention, an n-type impurity with small diffusion is implanted into the first n-type parasitic region near the gate electrode, and the second n-type impurity near the source and drain electrodes is formed. An n-type impurity capable of increasing the electron density can be injected into the parasitic region. Therefore, the short channel effect is sufficiently suppressed, and high speed, high uniformity, high withstand voltage, and large transconductance are obtained. There is an effect that a high-performance field-effect transistor can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic structural sectional view of an embodiment of a field effect transistor of the present invention, and FIG. 2 is a group IV and VI of the present invention.
FIGS. 3A to 3D are diagrams showing the distribution of electron density in the depth direction by ion implantation of group III elements, and FIGS. 3A to 3D are schematic structures showing main manufacturing steps in an embodiment of the method for manufacturing a field-effect transistor of the present invention. FIG. 4 is a schematic sectional view of a conventional field-effect transistor. 1, 41 ... substrate, 2 ... undoped GaAs, 3 ... n-type Ga
As, 4 ... Undoped A1GaAs, 5, 42 ... Second n-type parasitic region, 6, 43 ... First n-type parasitic region, 7, 45 ... Source electrode, 8, 46 ... Gate electrode, 9, 47 drain electrode, 31 ... undoped GaAs, 32 ... undoped A1GaAs,
33: SiO ₂ side wall, 34: S ion, 35: Si ion, 44
.... n-type GaAs channel

Claims (2)

(57) [Claims] A first n-type parasitic region and a second n-type parasitic region connected to the first n-type parasitic region between the source and drain electrodes and the gate electrode; The first
Is connected to a channel region formed under the gate electrode and made of an n-type semiconductor having group III and group V elements as constituent elements, and the second n-type parasitic region is connected to the source electrode and the source electrode. A field-effect transistor having a structure electrically connected to a drain electrode, wherein the first n-type parasitic region includes a group IV element as an n-type impurity;
A field effect transistor comprising a group VI element as an n-type impurity in the second n-type parasitic region. 2. A step of forming a gate electrode made of a heat-resistant metal on a semiconductor layer having an n-type channel and comprising a single or a plurality of semiconductors containing Group III and Group V elements as constituent elements. Forming an insulating film, removing the insulating film other than the side wall of the gate electrode, and implanting Group VI element ions into the semiconductor layer using the gate electrode provided with the insulating film on the side wall portion as a mask, Removing the insulating film on the side wall of the gate electrode, implanting group IV element ions into the semiconductor layer using the gate electrode as a mask, and electrically activating the implanted ions by performing a short heat treatment. And a method for manufacturing a field-effect transistor.