JPH03280552A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To improve the inverse breakdown voltage of a GaAs MES FET, and prevent the decrease of FET characteristics of HEMT, by ion-implanting a dopant of a second conductivity type in the vicinity of the surface of a semiconductor layer of a first conductivity type, activating implanted ions by heat treatment, and decreasing the concentration of first conductivity type carrier. CONSTITUTION:By using resist 2 as a mask, Si<+> ions are implanted in a semiinsulative GaAs substrate 1, thereby forming a thin ion-implanted layer 3 of high concentration. After the resist 2 is eliminated and an SiN film 4 is formed on the whole wafer surface, resist 5 is formed. After an SiO2 film 7 is deposited on the whole wafer surface, the resist 5 is eliminated, thereby forming a gate aperture 7' at the position corresponding with the part position 5' of the SiO2 film 7. The SiO2 film 7 used as a mask, and the SiN film 4 is etched by using RIE, thereby forming a gate aperture 4' at the position corresponding with the part position 5' of the SiN film 4. By using the SiO2 film 7 as a mask Zn<+> ions are implanted, thereby decreasing the carrier concentration in the vicinity of the surface of a channel region 8. After that, the channel region 8 and regions 6a, 6b are activated by short time heat treatment.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a method for manufacturing a spot field effect transistor.

(b) Conventional technology Many compound semiconductor devices, including GaAs, have excellent characteristics such as high-speed operation and low power consumption, and a variety of research into ultra-high speed and ultra-high wave integrated circuits is underway. It is done in the form of

In the case of a GaAs integrated circuit, in order to improve its performance, it is essential that the MESFETs that constitute the integrated circuit have high performance. One of the effective means of improving the performance of GaAs MESFETs is to make the active layer thinner and highly doped, and this can be expected to suppress the transconductance (g) in the direction of -E and the short channel effect.

In addition, ion implantation is widely used to form the active layer in consideration of cost, controllability, and uniformity.In recent years, high concentration of the active layer has been realized by low-energy, high-dose implantation, It has been reported that an extremely high performance M E S F E T of , = 630 mS/' turn was obtained.
an, E]ectronDevices Lette
rs vol, 9 No. 8 1988 P, 417
-P, 418).

In addition, in recent years, high electron mobility transistors (HEMTs) manufactured using the MBE method, etc., have been developed to reduce the contact resistance between the source electrode and the drain electrode, or the resistance between the source and gate. A heavily doped n-type GaAs cap layer is provided on top. However, regarding the cap layer where the gate electrode is provided, considering the gate breakdown voltage, it is not possible to directly provide the gate electrode on the cap layer, so recess etching is performed to obtain good breakdown voltage characteristics. A gate electrode is provided on the AZGaAs layer under the cap layer.

(c) Problems to be Solved The carrier profile of the highly concentrated thin active layer formed by the above-mentioned low-energy, high-dose implantation has a shape close to that of glass distribution. Therefore, there is a problem that the carrier concentration near the surface of the active layer increases and the reverse breakdown voltage becomes low.

Furthermore, in HEMTs that require the above-mentioned recess etching, there is a problem that the FET characteristics of the HEMT are degraded due to in-plane variations in the surface of the A1GaAs layer that occur during the recess etching.

(d) Means for Solving the Problems The present invention comprises a step of ion-implanting a second conductivity type dopant into the vicinity of the surface of a first conductivity type semiconductor layer, and a heat treatment to activate the implanted ions to the vicinity of the surface. A method for manufacturing a field effect transistor, comprising the steps of: reducing a first conductivity type carrier concentration of the semiconductor layer; and forming a gate electrode on the semiconductor layer.

(e) Function A semiconductor layer of the first conductivity type is formed by ion-implanting n-type dopane) (ZnJ), and p-type dopane) (ZnJ) is ion-implanted near the surface of this semiconductor layer. The carrier profile in this case is shown in Figure 2.This carrier profile is assumed to be an LSS curve, and Si and Zn are 100% activated, and Zn +77jJ compensates for a total of 81 carriers. In addition, the conditions for implanting Sl are acceleration energy 2
3 keV, dose 8X IQ "am-", Zn implantation conditions are acceleration energy 15 keV, dose 9
×IQ”cm−2.

As can be understood from the figure, by ion-implanting a p-type dopant, the n-type carrier concentration near the surface is reduced.

Even when the first conductivity type is p type and the second conductivity type is n type, the p type carrier concentration near the surface is reduced by ion-implanting the n type dopant, as described above.

(f) Examples of the method of the present invention
The case where the present invention is applied will be explained using FIGS. 1(a) to (h).

First, using a resist (2) as a mask on a semi-insulating GaAs substrate (1), Sl''' ions were heated at 25 keV and 8
IQ "crn-" is implanted (A) to form a thin layer of highly concentrated ions (3) (see Figure 1 (a)).
)),.

After removing the resist (2) and forming 300 SiN films (4) on the entire surface of the wafer using the ECR plasma CVD method, a resist (5) is formed. At this time, the width of the portion (5°) where the gate electrode was to be formed was 0.6 μm.

Using this resist (5) as a mask, Si3 ions were
Implant B at 0 keV, 3 x 10 “cm”
), a source region (6b) and a drain region (6b) are formed (FIG. 6(b)). At this time, the portion (8) becomes the channel region (active layer).

SiO2 film (
After depositing 300 layers of 7), the resist (5) is removed to form a gate opening (7°) at a position 1 corresponding to the portion (5°) of the Sin film (7). 5iO=
Using RIE as a mask, the SiN film (4) is etched to form a gate opening (4°) at a position corresponding to the portion (5°) of the SiN film (4).

Then, using the Sin film (7) as a mask, Zn- ions were implanted at 15 K e V and 9X10 Cm-' to lower the carrier concentration near the surface of the channel region (8). Channel area (8) with a short annealing (heat treatment) by a halogen lamp for seconds
and activate regions (6a) and (6b) ((d) in the same figure)
.

A WSi film (9) is deposited on the entire surface of the wafer up to the depth, and a resist (1O) is formed on the WS1 film (9) (FIG. 4(d)).

An Au film (11) is deposited on the entire surface of the wafer, and a resist (10) is deposited on the entire surface of the wafer.
) is removed, and then W is removed using the Au film (11) as a mask.
Etch the Si film (9) to expose the substrate surface (
Figure (f)).

A resist (12) is formed, and this resist (12) and A
SiN film (4) and 5i0 using u film (11) as a mask
2 film (7) is etched (FIG. 2(g)).

A u , / T i , / P d film on the entire surface (13)
The gate electrode (14) is completed by vapor-depositing and removing the resist (12), and the source electrode (
15) and drain electrode (16) are completed (see figure (h)
)).

The sheet resistance Rs between the source and drain electrodes of the GaAs MESFET completed as described above is the same as that of the GaAs MESFET manufactured using the same manufacturing process as described above except that Zn'' ions are not implanted.
It is equivalent to that of MESFET (conventional device).

In addition, as mentioned above, the completed G a As M E S
The maximum value of mutual conductance gゎ□ of FET is 4
00m5/mm, reverse withstand voltage is 8.8v, - direction,
The g*max of the conventional device is 410 m5/mm, and the reverse breakdown voltage is 3.8V. In other words, by implanting Zn ions, the reverse breakdown voltage can be significantly improved without changing Rs and g++tsat.

In the above embodiment, Zn'' ion implantation was performed after A implantation and B implantation, but it may be performed before A implantation or between A implantation and B implantation.

Next, the case where the method of the present invention is applied to HEMT will be explained using FIG. 2.

First, a molecular beam epitaxy (MBE) technique or an organometallic epitaxy (M
Non-doped GaAs layer (22
) was grown to a thickness of 1 μm, and the non-doped GaAs
On the layer (22), non-doped A l , G a knee,
The As layer (23) is grown to a thickness of 0 to 60 nm, and then the non-doped A l , Ga 1-, As layer (23
) on the Si-doped A l , Ga , , As layers (S
i concentration: 0.5-2, OX 10 "cm-")
(24 nm was grown to a thickness of 250-450 nm, and the Si-doped AIl.

Ga,,Si-doped GaAs on the A S layer (24)
layer (high concentration n-type GaAs cap layer) (Sl concentration: 2.
Grow 5 x 10 "cm-,") (25) to a thickness of 600 cm. Here, the composition X of the AlGaAs layer is approximately 0.3. Thereafter, an ohmic metal made of Au, Ge, Ni, etc. is vapor-deposited on the heteroepitaxial substrate thus formed, and the metal is left in the source electrode formation part and the drain electrode formation part by a lift-off method, and alloyed. The ohmic region is made of Si-doped GaA.
s layer (25), S1 doped A' ++ G a +
-*A 8 layers (24), non-doped A 12 , G
a, -, As layer (23), and non-doped Ga, A
A source electrode (26) and a drain electrode (27) are formed by penetrating the s-layer (22).

A resist having an aperture is formed between the source electrode (26) and the drain electrode (27), and using this resist as a mask, Zn" ions are applied at 25 K e V and 2.8XIQ".
cm-” doped Ga, As layer (2
5) Lower the concentration near the surface. After that, 7゜0
The injection layer is activated by short-time annealing using a halogen lamp at 50°C for 5 seconds. After removing the resist, a t-gate electrode (28) is formed on the Si-doped GaAs layer (25). This gate electrode (28) is T i /P t/'
, Au is selectively deposited between the source electrode (26) and the drain electrode (27) by a lift-off method.

The reverse breakdown voltage of the HEMT completed as described above is 5.2V, while the reverse breakdown voltage of the HEMT manufactured using the same manufacturing process as above except that Zn'' ions are not implanted is 0.2V.
It becomes v. In other words, the IEMT can be fabricated without performing recess etching of the Si door GaAs layer (25), and in-plane variations due to recess etching do not occur.

In addition, although GaAs base was used in each of the above-mentioned examples, In
A P substrate or the like may be used, and implanted ions other than Si' ions and Zn' ions may be used.
In the case of a field effect transistor using an active layer of type
An n-type dopant may be mainly added as ions.

(g) Effects of the Invention As is clear from the above description, the present invention provides a method for ion-implanting a dopant of the second conductivity type to
Since the conductivity type carrier concentration can be reduced, Ga
The reverse withstand voltage is improved in the As-fEs FET, and in-plane variations due to recess etching are eliminated in the HEMT, making it possible to prevent the FET characteristics of the HEMT from deteriorating.

[Brief explanation of drawings]

Figures 1 (a) to (h) are process explanatory diagrams for explaining the method of the present invention, Figure 2 is a diagram showing the injection profile, and Figure 3 is a diagram showing the injection profile.
The figure is a schematic cross-sectional view of HEMT. (1) -=- semi-insulating GaAs substrate, (2) (5) (1
0) (22)...Resist, (3)...Ion implantation layer, (4)...SiN film, (7)...5iO=film,
(8)...Channel area, (9)---WS i
M, (11) = A u film, (13)” A u /'
Ti/′Pd film, (14)...gate electrode, (15)
... Source electrode, (16) ... Drain electrode, (2
1) Semi-insulating GaAs substrate, (25) Si-doped GaAs1, (2B) Gate as a pole.

Claims (1)

[Claims] 1. A step of ion-implanting a second conductivity type dopant near the surface of the first conductivity type semiconductor layer, and a step of activating the implanted ions by heat treatment to reduce the first conductivity type carrier concentration near the surface. A method for manufacturing a field effect transistor, comprising the steps of: forming a gate electrode on the semiconductor layer.