JP2000307100A - Field effect semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a field effect semiconductor device which contains a HENT and is excellent in high-frequency characteristics and high-speed operating characteristics by reducing the device in damage by ion implantation for controlling Vth and keeping it high in channel mobility. SOLUTION: A field effect semiconductor device is equipped with an InGaAs channel layer 13 formed on a semi-insulating GaAs substrate 11, an N-AlGaAs carrier feed layers 14A and 14B which are larger in energy band gap than the channel layer 13 and where impurities are introdued into all their surfaces, an I-GaAs insertion layer 15 which is interposed between the N-AlGaAs carried feed layers 14A and 14B and higher than them in impurity activation rate, and a Vth-control ion-implantation region 21 which includes the insertion layer 15 and is formed only in a transistor required for changing a threshold voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a threshold voltage (V _th )
High electron mobility transistor in which is controlled by introducing impurity ions.
The present invention relates to a field effect semiconductor device including an electron transfer (HEMT).

[0002]

2. Description of the Related Art Generally, HEMTs are frequently used as elements having good high-frequency characteristics and high-speed operability. When a high-speed field-effect semiconductor device composed of HEMTs is realized, the threshold voltage _Vth must be reduced. Different types of H
EMT is required.

In order to separately produce a plurality of types of threshold voltages V _th ,
For example, MESFET (metalsemiconductor)
to field effect transist
or) is achieved by changing the dose of ion implantation for forming a channel, and in the case of a HEMT having a modulation doping structure, it is achieved by changing the depth of the gate recess.

However, even in HEMT, MES
As with FET, if it is possible to control the V _th by ion implantation, it is possible to simplify the process of making the HEMT having different V _th on the same substrate.

However, in the HEMT, the energy band gap in the carrier supply layer is wider than that in the channel layer and the impurity is doped at a high concentration. It is difficult to perform the implantation to introduce the dopant in view of crystal damage and the like.

In order to avoid the above-mentioned difficulties, undoped AlGaAs is used without using a modulation doping structure.
In a heterojunction structure FET using a barrier layer or the like, attempts have been made to control _Vth by ion implantation.

In other words, a technique has been proposed in which an InGaAs layer having a higher dopant activation efficiency than AlGaAs is interposed in the AlGaAs layer and _Vth is changed by low-temperature activation annealing (in other words, a "special technique"). Kaihei 2-27394
No. 3).

However, according to the proposed technique, since the barrier layer is not doped, it has the following two problems. That is, in the heterojunction structure FET, the channel is doped, so that the carrier mobility is already low even without ion implantation into the channel. In the heterojunction structure FET, the electrode contact resistance is reduced. In order to form the ohmic region, it is necessary to introduce a high-dose impurity, so that the impurity is likely to diffuse laterally from the ohmic region, and it is difficult to fabricate a short gate device.

[0009]

According to the present invention, a HEMT having good high-frequency characteristics and high-speed operability is provided by reducing damage due to ion implantation for V _th control and maintaining high channel mobility. And a field-effect semiconductor device including the same.

[0010]

According to the present invention, in a HEMT having a modulation doping structure, a semiconductor layer having a high impurity activation efficiency is interposed in a carrier supply layer, so that a small amount of dopant can be used. Basically, it is possible to control V _th with low damage.

Incidentally, a HEMT having a modulation doping structure
Since ion implantation is not necessary for forming an ohmic region, extremely high performance can be maintained as long as ion implantation for controlling V _th can be performed with low damage.

FIG. 1 is an explanatory view for explaining the principle of the present invention, in which (A) is a cutaway side view of a main part of a HEMT, and (B).
FIG. 4 is a diagram showing a relationship between V _th and carrier mobility.

In FIG. 1A, reference numeral 1 denotes semi-insulating GaAs.
s substrate, 2 is an i-AlGaAs buffer layer, 3 is InG
aAs channel layer (first semiconductor layer), 4A and 4B are n-AlGaAs carrier supply layers (second semiconductor layer),
5 is an i-GaAs insertion layer (third semiconductor layer), 6 is n-
An AlGaAs cap layer, 7 is a gate electrode, 8 is a source electrode, 9 is a drain electrode, and 10 is a _Vth control ion implantation region.

The HEMT according to the present invention is different from the conventional HEMT in that a carrier supply layer is formed above the channel layer 3.
Although not different from EMT, the carrier supply layer is composed of two layers, that is, the carrier supply layers 4A and 4B, between which the energy band gap is narrower than that of the carrier supply layers 4A and 4B. An insertion layer 5 made of is interposed.

[0015] The insertion layer 5, since the activation efficiency of the dopant introduced in order to change the V _th is high, that is inserted layer 5 as compared to the absence, to control the V _th with a small amount of dopant Yes, and if less dopant is introduced, less damage to the crystal.

The insertion layer 5 in the illustrated HEMT is a GaAs layer having a thickness of 4 nm, and the ion implantation amount for controlling V _th is 1 × 10 ¹² to 4 × 10 ¹² [cm ^{− 2} ], and how the change in _Vth and the carrier mobility changed was examined. The result shown in FIG. 1B was obtained.

FIG. 1B is a graph showing the relationship between the change amount of V _th and the carrier mobility. The horizontal axis represents the change amount of V _th , and FIG.
The vertical axis represents the carrier mobility.

In the figure, the characteristic line indicated by a circle is shown in FIG.
(A) is the data on the HEMT described above, and the characteristic line indicated by ● is the data added for reference, and is the measurement result on the HEMT without the GaAs insertion layer 5 according to the present invention. is there.

According to FIG. 1B, V _{th is set} to 0.5 [V].
When shifting, the carrier mobility is reduced to about half in the conventional HEMT, whereas the HEMT according to the present invention is used.
It can be seen that the carrier mobility can be reduced to 10% or less.

As means for changing V _th , HEMT is used.
A method of changing V _th deeply (to the depletion side) by introducing a dopant having the same conductivity type as the carrier in the above (the former), and a method of introducing a dopant having a different conductivity type to make V _th shallow ( On the enhancement side)
There is a method of changing (the latter), and the present invention is effective in both cases.

In any case, if a dopant is introduced to change V _th , it is inevitable that the characteristics will be degraded. Therefore, a HEMT having a deep V _th and a HEMT having a shallow V _th within one chip.
HEMT with a shallow V _th
The former may be used for applications where higher characteristics are required, and the latter may be used for applications where higher characteristics are required for HEMTs having a deeper _Vth .

The GaAs insertion layer 5 according to the present invention, ie,
If the thickness of the third semiconductor layer is too thin, the effect of improving the activation efficiency of the introduced impurities cannot be sufficiently obtained.
It is necessary to have a layer thickness of 2 [nm] or more, which has been confirmed by experiments.

FIG. 2 is a diagram showing the relationship between the thickness of the third semiconductor layer (GaAs) and the amount of shift of the threshold voltage V _th , and the horizontal axis represents the thickness [nm] of the third semiconductor layer (GaAs). , And the vertical axis represents the threshold voltage change [V].

As is apparent from the figure, when the thickness of the third semiconductor layer is less than 2 [nm], the threshold voltage hardly changes.

From the above description, in the field effect semiconductor device according to the present invention, (1) a first semiconductor layer (for example, a channel layer formed on a substrate (for example, a semi-insulating GaAs substrate 11)). In
A GaAs channel layer 13) and an energy band formed on the first semiconductor layer as compared to the first semiconductor layer.
A second semiconductor layer having a large gap and doped with impurities on the entire surface (for example, the n-AlGaAs carrier supply layer 14).
A and 14B) and a third semiconductor layer (for example, an i-GaAs insertion layer 15) interposed in the second semiconductor layer and made of a material having a higher impurity activation rate than the second semiconductor layer.
And a threshold voltage control impurity introduction region (for example, a V _th control ion implantation region 2) formed only in a transistor portion including the third semiconductor layer and requiring a threshold voltage to be changed.
1) and or

(2) In the above (1), the transistor portions having different threshold voltages (for example, the gate electrode 17A)
Or a HEMT represented by a gate electrode 17B).

(3) In the above (1) or (2),
The transistor portion that needs to have a higher threshold voltage is a threshold voltage control impurity introduction region in which an impurity of the same conductivity type as that of the carrier is introduced, or

(4) In the above (1) or (2),
The transistor portion that requires a shallow threshold voltage is a threshold voltage control impurity introduction region in which an impurity of the conductivity type opposite to that of the carrier is introduced, or

(5) In any one of the above (1) to (4), the third semiconductor layer (for example, the i-GaAs insertion layer 1)
The layer thickness of 5) is not less than 2 [nm].

By adopting the above-mentioned means, when V _th is changed by introducing impurities into the carrier supply layer composed of the second semiconductor layer and the third semiconductor layer having a high impurity activation efficiency, the amount of impurities is small. even, since higher in impurity activation efficiency to the third semiconductor layer, a sufficient amount of activated impurities is generated to change the V _th, therefore, cost required for changing the V _th Therefore, it is possible to suppress a decrease in carrier mobility due to the ion implantation damage.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is a cutaway side view of a main part showing a field effect semiconductor device for explaining an embodiment of the present invention.

In the figure, 11 is a semi-insulating GaAs substrate, 12 is an i-AlGaAs buffer layer, and 13 is InG.
aAs channel layer (first semiconductor layer), 14A is nA
lGaAs carrier supply layer (second semiconductor layer), 14B
Is an i-AlGaAs carrier supply layer (second semiconductor layer), 15 is an i-GaAs insertion layer (third semiconductor layer),
16 is an n-GaAs cap layer, 17A and 17B are gate electrodes, 18A and 18B are source electrodes, 19A and 19B are drain electrodes, 20A, 20B and 20C are element isolation regions, and 21 is a V _th control ion implantation region. ing.

The outline of the process for manufacturing the field-effect semiconductor device shown in FIG. 3 is as follows.

(1) MOVPE (metalorga)
By applying a nic vapor phase epitaxy method, a buffer layer 12
Channel layer 13, carrier supply layer 14A, insertion layer 15,
The carrier supply layer 14B and the cap layer 16 are grown.

The main data on the grown semiconductor layers is as follows. About buffer layer 12 Material: i-AlGaAs Thickness: 300 [nm] About channel layer 13 Material: i-InGaAs In composition: 0.2 Thickness: 15 [nm] About carrier supply layer 14A Material: n-AlGaAs Al composition : 0.3 Impurity concentration: 2 × 10 ¹⁸ [cm ⁻³ ] Thickness: 7.5 [nm] About insertion layer 15 Material: i-GaAs Thickness: 4 [nm] Carrier supply layer 14B Material: n-AlGaAs Al composition: 0.30 Impurity concentration: 2 × 10 ¹⁸ [cm ⁻³ ] Thickness: 7.5 [nm] About the cap layer 16 Material: n-GaAs Impurity concentration: 2 × 10 ¹⁸ [cm ⁻³ ] Thickness : 50 [nm]

(2) By applying a resist process in the lithography technique, a resist film having an opening corresponding to the HEMT which needs to change V _th is formed.

(3) By applying the ion implantation method, the ion acceleration energy is set to 60 [keV], the dose is set to 8 × 10 ¹¹ [cm ^-2 ], and the resist film formed in the step (2) is formed. Is implanted using Si as a mask, and V _th
A control ion implantation region 11 is formed.

(4) After removing the resist film, the temperature is set to 830 ° C., the time is set to 15 seconds, and the impurity activation heat treatment is performed.

(5) A resist film having an opening in a portion where an element isolation region is to be formed is formed by applying a resist process in lithography technology.

(6) By applying the ion implantation method, oxygen ions are implanted using the resist film formed in the step (5) as a mask, and the element isolation regions 20A, 20B,
20C is formed.

(7) After removing the resist film, a resist film having an opening at a portion where an ohmic electrode is to be formed is formed by applying a resist process in lithography technology.

(8) By applying a vapor deposition method, A
After depositing uGe / Au, lift-off is performed to peel off the resist film formed in step (7), and the source electrode 18A,
A source electrode 18B, a drain electrode 19A, and a drain electrode 19B are formed.

(9) A resist film having an opening in a portion where a gate electrode is to be formed is formed by applying a resist process in lithography technology.

(10) The etching gas is SiCl ₄
By applying a dry etching method using a system gas, the n-GaAs cap layer 16 exposed in the opening of the resist film formed in the step (9) is etched to form an opening, and the opening is formed. The underlying i-AlGaAs carrier supply layer 14B is exposed.

(11) By applying an evaporation method while leaving the resist film formed in the step (9), after depositing Al, lift-off is performed to peel off the resist film, and the gate electrode 17A and the gate electrode 17A are removed. The gate electrode 17B is formed.

Through the above steps, HEMTs having V _th different by 0.5 [V] can be formed on the same substrate, and the implantation amount of Si ions for changing V _th can be increased. , Carrier mobility degradation due to crystal damage is small.

In the present invention, without being limited to the above-described embodiment, many other modifications can be realized without departing from the scope of the claims.

For example, the dopant introduced for changing V _th is not limited to Si, and S, C, Mg, Be, etc. can be selectively used as necessary. The method is not limited to the method, and a gas phase diffusion method, a solid phase diffusion method, or the like can be appropriately selected.

Further, the insertion layer as the third semiconductor layer includes:
In addition to GaAs, AlGaAs can be used. In this case, those having a relatively small x value, that is, an Al composition, have a large impurity activation rate.

Furthermore, the thickness of each semiconductor layer, the impurity concentration, the impurity addition condition, the metal material, the element manufacturing process, and the like can be appropriately selected.

[0051]

In the field effect semiconductor device according to the present invention, the first semiconductor layer which is a channel layer and the energy band band formed on the first semiconductor layer are smaller than those of the first semiconductor layer. A second semiconductor layer having a large gap and an impurity introduced into the entire surface, and a third semiconductor layer of a material having a higher impurity activation rate than the second semiconductor layer interposed in the second semiconductor layer; A threshold voltage control impurity introduction region formed only in a transistor portion including the third semiconductor layer and requiring a threshold voltage to be changed.

By adopting the above means, when V _th is changed by introducing impurities into the carrier supply layer composed of the second semiconductor layer and the third semiconductor layer having high impurity activation efficiency, the amount of impurities is small. even, since higher in impurity activation efficiency to the third semiconductor layer, a sufficient amount of activated impurities is generated to change the V _th, therefore, cost required for changing the V _th Therefore, it is possible to suppress a decrease in carrier mobility due to the ion implantation damage.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram for explaining the principle of the present invention.

FIG. 2 is a diagram showing a relationship between a layer thickness of a third semiconductor layer (GaAs) and a threshold voltage V _th shift amount.

FIG. 3 is a fragmentary side view showing a field-effect semiconductor device for describing an embodiment of the present invention;

[Explanation of symbols]

Reference Signs List 11 semi-insulating GaAs substrate 12 i-AlGaAs buffer layer 13 InGaAs channel layer (first semiconductor layer) 14An n-AlGaAs carrier supply layer (second semiconductor layer) 14B n-AlGaAs carrier supply layer (second semiconductor layer) 15) i-GaAs insertion layer (third semiconductor layer) 16 n-GaAs cap layer 17A and 17B Gate electrode 18A and 18B Source electrode 19A and 19B Drain electrode 20A, 20B, 20C Device isolation region 21 _Vth control ion implantation region

Claims (5)

[Claims] A first semiconductor layer serving as a channel layer formed on a substrate; and an energy band gap larger than the first semiconductor layer formed on the first semiconductor layer and having a larger energy band gap. A second semiconductor layer in which impurities are introduced into the entire surface, a third semiconductor layer made of a material interposed in the second semiconductor layer and having a higher impurity activation rate than the second semiconductor layer, A field effect semiconductor device comprising: a threshold voltage control impurity introduction region formed only in a transistor portion including the third semiconductor layer and requiring a threshold voltage to be changed. 2. The field effect semiconductor device according to claim 1, further comprising transistor portions having different threshold voltages. 3. The transistor part in which the threshold voltage needs to be deepened is a threshold voltage control impurity introduction region into which an impurity of the same conductivity type as that of the carrier is introduced. Item 3. The field-effect semiconductor device according to Item 2. 4. A transistor portion requiring a shallow threshold voltage is a threshold voltage control impurity introduction region into which an impurity of a conductivity type opposite to that of a carrier is introduced. Item 3. The field-effect semiconductor device according to Item 2. 5. The semiconductor device according to claim 1, wherein the thickness of the third semiconductor layer is 2 nm or more.
The field-effect semiconductor device according to claim 1.