JPS6143443A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the wiring yield and the density of integration by a method wherein the first semiconductor layer is formed on a substrate and then a part corresponding to separated region is implanted with ion while the lowest level is raised higher than Fermi level. CONSTITUTION:An undoped GaAs layer 2 is grown on a semiinsulating substrate 1 comprising GaAs by means of liquid epitaxial process etc. Next a photoresist film 3 is deposited on the layer 2 and then the layer 2 is implanted with beryllium ion utilizing the layer 3 as a mask to be changed into a P type GaAs layer 4. Later the film 3 is removed and then an SiO2 film is formed on overall surface before performing specified capannealing. Then the SiO2 film is removed to form an N type AlGaAs layer 5 on overall surface by means of molecular beam epitaxial process and then an N type GaAs layer 6 is successively grown on the layer 5. Later ohmic metals as source.drain e.g. an alloy of AuGe/ Ni/Au are evaporated and etched to form source.drain electrodes 7, 8. At this time, elements may be separated by means of increasing the concentration of layer 4 to raise the lowest level higher than Fermi level.

Description

DETAILED DESCRIPTION OF THE INVENTION - [Technical Field] The present invention relates to a technique that is effective when applied to isolation between elements of a semiconductor device having a heterojunction, particularly a field effect transistor.

[Background Art] Compound semiconductors, such as gallium arsenide (GaAs
) can use semi-insulating GaAs as a substrate, and
Various materials have been developed because of their high electron mobility.

In order to further increase this electron mobility, a HEMT C (high electron mobility transistor) using a Peter junction was disclosed in Japanese Patent Laid-Open No. 56-94780 or No. 57-11 of the same town.
It is disclosed in Japanese Patent No. 8676.

This HEMT element is, for example, an undoped G a A
This is an FET in which an N-type AuGaAs layer is formed on an s layer, and a two-dimensional electron gas generated at a heterojunction formed at the interface between these layers is controlled by a metal electrode of the N-type AuGaAs layer. By the way, the isolation between these HEMT elements is
This is generally done by mesa etching. For this reason, there was a problem in that the heterojunction was exposed on the surface and the reliability of the integrated circuit deteriorated. Furthermore, due to mesa etching, steps are formed on the wafer, making wiring difficult and reducing wiring yield. Furthermore, the above-mentioned Japanese Patent Application Laid-Open No. 57-118676 proposes, for example, performing device isolation by using acceptors or donors implanted into the N-type AuGaAs layer.

However, element isolation by ion implantation into the N-type Al2GaAs layer has a drawback in controllability.

[Objective of the Invention] An object of the present invention is to provide a semiconductor device that improves reliability and wiring yield by performing element isolation without introducing mesa etching, enables high integration, and allows easy control of element isolation. The present invention provides a method for manufacturing.

The above and other objects and novel features of the present invention are as follows:
The description herein and the accompanying drawings will become clear.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

In a semiconductor device in which a heterojunction is formed at the interface between a first semiconductor layer and a second semiconductor layer on a semi-insulating substrate, first, after forming the first semiconductor layer, a selective layer is applied to the element isolation region. Perform ion implantation. After annealing, a second semiconductor layer is formed on the entire surface. By changing the impurity concentration of the first semiconductor layer, the width of the depletion layer of the heterojunction can be adjusted. Therefore, it is easy to make the lowest level of the carrier accumulation layer higher than the Fermi level by narrowing the width of the potential groove, and its controllability is also long. In this way, since element isolation can be performed without using mesa etching, reliability and wiring yield can be improved, and a method of manufacturing a semiconductor device with good controllability can be achieved.

[Example] An example of the method for manufacturing a semiconductor device of the present invention will be described below with reference to FIGS. 1 to 5. 1 to 3 are cross-sectional views showing the manufacturing process.

FIGS. 4 and 5 are diagrams showing energy bands of a heterojunction.

In FIG. 1, an undoped GaAs layer 2 (first semiconductor layer) is grown on a semi-insulating substrate 1 by liquid phase epitaxial method or molecular beam epitaxial method. GaAs is used for the semi-insulating substrate 1.

Next, in FIG. 2, a photoresist film 3 is deposited on the undoped GaAs layer 2 in a portion where the element region is to be formed, and beryllium ions are implanted using the photoresist film 3 as a mask. The undoped GaAsW2 in the isolation region implanted with beryllium becomes a P-type GaAs layer 4. Although the photoresist film 3 was used as a mask, it goes without saying that the SiC2 film can also be used as a mask. Thereafter, the photoresist film 3 is removed, a SiO□ film is formed on the entire surface, and required cap annealing is performed.

After annealing, the 5i02 film is removed. An N-type AQGaAs layer 5 (second semiconductor layer) is formed on the entire surface by molecular beam epitaxial method, and an N-type GaAs layer 5 (second semiconductor layer) is formed on the upper layer.
The s-layer 6 is grown continuously (FIG. 3).

After this, the ohmic metal of the source and drain.

For example, the source/drain electrodes 7 and 8 are formed by depositing an AuGe/Ni/Au alloy and then etching it. Further, the gate electrode 9 is formed of, for example, tungsten silicide or titanium tungsten.

In such a HEMTI device, the energy band diagram of the heterojunction can appear as shown in FIGS. 4 and 5. That is, the P-type GaAs layer 4 and the N-type AQG
The energy band diagram of the isolation region formed at the interface with the aAs layer 5 shows that the extension of the depletion layer is small, as shown by the symbol A in FIG.
In the energy band diagram of the element region formed at the interface with the aAs layer 5, the depletion layer is widened as indicated by the symbol B in FIG.・In the figure, the dashed line indicates the Fermi level9
The dotted line indicates the lowest level that can exist within the potential groove.

As can be seen from FIG. 4, near the heterojunction of the isolation region formed by the P-type AQGaAs layer 4 and the N-type AQGaAs layer 5, the band bends sharply and the width of the potential groove becomes narrow. Therefore, the lowest level indicated by the one-dot line increases. By making the concentration of P-type GaAsJfj4 sufficiently high, it is extremely easy to make the lowest level a higher energy level than the Fermi level. Therefore, there is no two-dimensional electron gas in the separation region, resulting in high resistance.
This achieves isolation between elements.

Furthermore, in the vicinity of the heterojunction formed by the undoped GaAs layer 2 and the N-type AQGaAs layer 5 in the element region, the lowest level can exist at a level lower than the Fermi level, as shown in FIG. .

Therefore, an accumulation layer of electrons, which are carriers, is formed and contributes to electrical conduction.

[Effects] As explained above, the first semiconductor layer is formed on the semi-insulating substrate, and ions are implanted into the portion corresponding to the isolation region. Therefore, the width of the potential groove at the heterojunction between the second semiconductor layer and the first semiconductor layer formed on the first semiconductor layer changes, and the lowest level cannot be made higher than the Fermi level. can. Therefore, element isolation by mesa etching as in the conventional method is not required, and the effects of improved reliability, wiring yield, and degree of integration can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the first semiconductor layer and the second semiconductor layer are each a combination of undoped and N type, but the combination of N- type and N4'' type, undoped and P
A combination of P-type and P-type is also possible.

[Field of Application] The present invention is directed to FETs having heterojunctions, particularly GaAsM
It can be applied to integrated circuits using ESFET.

[Brief explanation of the drawing]

1 to 3 are process cross-sectional views showing one embodiment of the method for manufacturing a semiconductor device of the present invention. Figures 4 and 5 are each for 1 minute! FIG. 3 is a band diagram for explaining an energy band near a heterojunction between a 1liV4 region and an element region. DESCRIPTION OF SYMBOLS 1... Semi-insulating substrate (GaAs), 2... First semiconductor layer (undoped GaAs layer), 4---P type Ga
As layer, 5... second semiconductor layer (N-type AQGaA
s layer). 6... N-type AQGaAs layer, 7... Source electrode, 8
...Drain electrode, 9...Gate electrode, third
figure

Claims (1)

[Claims] 1. A first semiconductor layer is formed on a semi-insulating substrate, and then ions are selectively implanted into the first semiconductor layer corresponding to the isolation region other than the element region, followed by annealing. A second semiconductor layer forming a heterojunction with the first semiconductor layer is formed on the entire surface, so that a carrier accumulation layer of the heterojunction between the first semiconductor layer and the second semiconductor layer is formed in the isolation region other than the element region. 1. A method for manufacturing a semiconductor device, characterized by preventing the formation of.