JPH07106525A - Field-effect transistor and compound semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a field-effect transistor and an integrated circuit appropriate in ultrahigh speed operations, capable of reducing parasitic resistance of a diode and a diode area. CONSTITUTION:In a compound semiconductor integrated circuit, a high concentration n type GaAs layer 6 is provided in a source and a drain of a field-effect transistor, and an undoped GaAs layer 7 and a second gate electrode 10 are provided thereon.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor integrated circuit using a field effect transistor (FET) having an ultrahigh speed, and an FET particularly suitable for enhancing the high speed.
And a compound semiconductor integrated circuit having a diode.

[0002]

2. Description of the Related Art A conventional compound semiconductor integrated circuit using FETs is disclosed in, for example, IE Journal
Solid State Circuits (IEEE JOURNAL OF SOLI
D-STATE CIRCUITS, VOL. 27, NO. 10, pp. 1342-134
5). The compound semiconductor integrated circuit is composed of a diode, a FET and a resistance element.

As shown in FIG. 3, in this conventional example, an FET is used.
By using a two-dimensional electron gas field effect transistor (2DEG FET) having an InGaAs channel 33 as
It has realized an ultrahigh-speed integrated circuit intended for use in a 10 Gbps optical transmission system. The diode used here has the same structure as the FET, and a Schottky diode using two terminals between the gate and source (or both source and drain) of the FET was used. In FIG. 3, 31 is a semi-insulating GaAs substrate and 32 is Al.
Undoped buffer layer including GaAs hetero buffer, 33 undoped InGaAs channel layer, 34 N-type AlGaAs electron supply layer, 35 n-type GaAs cap layer, 38 lift-off gate electrode made of Ti / Al, 39 AuGe / Ni / Au is an alloy ohmic electrode.

Using the same structure as the FET in the diode is a method generally used in the present compound semiconductor FET integrated circuit.

[0005]

As shown in FIG. 4, many diodes are used for level shifting in a source follower circuit. According to our study, the band of such a source follower is limited by the capacitance added to each node of the source follower and the parasitic resistance of the diode, and it becomes clear that the band of the IC itself is deteriorated. It was

When the compound semiconductor FET is used as a diode, the source resistance Rs and drain resistance Rd of the FET become parasitic resistance of the diode. The source resistance of the FET is generally about 35 to 70 Ω per 10 μm gate width. Although there is a demand to reduce the source resistance in order to improve the performance of the FET, it has been difficult to reduce the parasitic resistance to less than that by the conventional technique.

On the other hand, there is a method of widening the gate width as a method of reducing the parasitic resistance of the diode, but in this case, the parasitic capacitance increases due to the increase of the diode area, and therefore the band cannot be improved.

The method using the FET as a diode as in the conventional example has a problem that it is difficult to further improve the band of the IC, and a higher speed IC cannot be realized.

It is an object of the present invention to propose a field effect transistor structure capable of reducing the parasitic resistance of a diode and reducing the diode area, and to provide a compound semiconductor integrated circuit most suitable for ultra-high speed operation.

[0010]

To achieve the above object, a high-concentration impurity layer is formed on a source and a drain of an FET, an undoped semiconductor layer is formed on the high-concentration impurity layer, and the undoped semiconductor layer is formed. A second gate electrode, which will be the anode of the diode, was formed on top of the.

[0011]

By using the high-concentration impurity layer as the cathode of the Schottky diode, the series resistance in the semiconductor layer of the parasitic resistance of the diode can be made extremely small, and in particular by increasing the film thickness of the high-concentration impurity layer, the series resistance can be increased. The resistance can be reduced to one digit or less as compared with the conventional one.

By forming the undoped semiconductor layer on the high-concentration impurity layer, a good Schottky junction with a small tunnel current component can be formed between the second gate electrode and the semiconductor layer. According to the experiments by the inventors, a good diode having an ideality factor n = 1.1 can be obtained.

Further, the area of the diode can be reduced by forming the diode on the high concentration impurity layer of the drain or the source of the FET.

[0014]

Embodiment 1 Embodiment 1 of the present invention will be described below with reference to FIGS. 1, 2 and 4. Figure 1 shows HIGFET (Heterostructure
It is a cross-sectional structural diagram of a type of FET called Insulated-Gate FET) and a diode. FIG. 2 shows the HIGFET of FIG.
FIG. 4 is a layout diagram of a source follower circuit using the above, and FIG. 4 is a circuit diagram of the source follower circuit.

First, the manufacturing process of the FET will be described. In FIG. 1, an undoped GaAs buffer layer 2, a p-type GaAs layer 3, an n-type InGaAs active layer 4, and an undoped AlGaAs layer 5 are successively grown on a semi-insulating GaAs substrate 1 by MBE (electron beam epitaxial) method. Here, the thickness and impurity concentration of each layer are as shown in Table 1. The composition ratio y of the n-type InyGa1-yAs active layer 4 was 0.2, and the composition ratio x of the undoped AlxGa1-xAs layer 5 was 0.3.

[0016]

[Table 1]

The layers shown in Table 1 may be formed by MOCVD (Metal Organic Chemical Vapor Deposition) method. In that case, it is preferable to use carbon as an impurity of the p-type GaAs layer 3.

After element isolation by wet etching, 600 nm thick WSi (tungsten silicide) is deposited and processed to form a heat resistant gate electrode 8.
After that, in order to reduce the resistance between the source and the gate,
Si ions may be implanted using the heat resistant gate electrode 8 as a mask. In this case, the ion implantation conditions are an acceleration energy of 50 keV and a dose amount of 1E14 / cm ^2, which is activated by heat treatment.

Next, after depositing and processing a SiON film, using this as a mask, the semiconductor surface of the source and drain parts of the FET is ground to a depth of 70 nm and exposed p-type GaA.
A high concentration n-type GaAs layer 6 and undoped GaA are formed on the s layer 3 by MOCVD (metal organic chemical vapor deposition).
The s layer 7 is continuously grown. The crystal growth at this time is Si
The ON film is used as a mask to selectively grow on the source and drain portions. The high-concentration n-type GaAs layer 6 is made of Si or Se.
E18 / cm ³ at a concentration of doped thickness 320nm Ga
The undoped GaAs layer 7 is made of As and has a thickness of 50 n.
m of GaAs. The temperature during growth is usually 680 ° C., and trimethylgallium and arsine are used as source gases.

Next, an ohmic electrode 9 made of AuGe / W / Ni / Au is formed on the undoped GaAs layer 7 by the lift-off method, and alloyed at 400.degree. As a result, the alloy region 19 extends to a depth of about 140 nm in the semiconductor layer, so that the ohmic electrode 9 and the high-concentration n-type GaAs layer 6 are formed.
Good electrical connection with. Next, Mo / Pt / A
The second gate electrode 10 made of u is formed of undoped GaAs.
It is formed on the layer 7 by a lift-off method.

After that, a low resistance metal 11 composed of Mo / Au / Mo is formed on the heat resistant gate electrodes 8 and wiring is performed on these electrodes to complete the integrated circuit.

FIG. 2 shows a layout example when the field effect transistor according to this embodiment is applied to a source follower circuit. The cross-sectional view taken along the broken line AA 'in the figure corresponds to FIG. By arranging in this way, the source follower circuit shown in FIG. 4 can be realized.

According to the first embodiment, the parasitic resistance of the diode can be reduced to about 15Ω per 10 μm gate width.
This is 5 when the diode with the same structure as the FET is used.
Compared with about 0Ω, the parasitic resistance becomes about 30%. That is, according to this embodiment, the gate width is 30
%, The same parasitic resistance can be obtained, and the element area can be significantly reduced. In addition, by making the electrodes of the FET and the diode common, the diode area is further reduced to about 1 /
It becomes about 2, and the parasitic capacitance due to the wiring between the FET and the diode becomes zero. By these, parasitic capacitance can be reduced and the band of the source follower can be improved as compared with the conventional case.

In the first embodiment, the second gate electrode 1
Although 0 is set to Mo / Pt / Au, the gate metal may be Ti / Pt / Au which is usually used, WSi which is a heat-resistant gate metal, or the like.

In the first embodiment, the second gate electrode may be Mo / Au / Mo and may be formed simultaneously with the low resistance metal 11. In this case, the process of manufacturing the integrated circuit can be shortened.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a cross-sectional structural diagram of a HIGFET and a diode.

First, the manufacturing process of the FET will be described. Figure 5
At the semi-insulating InP substrate 41, an undoped InAlAs buffer layer 42, a p-type InGaAs layer 43, and an n-type InGaA are formed on the semi-insulating InP substrate 41 by the MBE (electron beam epitaxial) method.
The s active layer 44 and the undoped InAlAs layer 45 are continuously and sequentially grown. Here, the thickness and impurity concentration of each layer are as shown in Table 2. Here, p-type InyGa1-y
As layer 43 and n-type InyGa1-yAs active layer 44
The composition ratio y of 0.5 is 0.53, and undoped InzAl1-
zAs buffer layer 42 and undoped InzAl1-
The composition ratio z of the zAs layer 45 was 0.52, and the zAs layers 45 were lattice-matched to the semi-insulating InP substrate 41.

[0028]

[Table 2]

The layers shown in Table 2 may be formed by MOCVD (Metal Organic Chemical Vapor Deposition) method. In that case, it is preferable to use carbon as an impurity of the p-type InGaAs layer 43.

Next, after element isolation is performed by wet etching, WSi (tungsten silicide) having a thickness of 600 nm is deposited and processed to form a heat resistant gate electrode 8.

Next, after depositing and processing a SiON film, using this as a mask, the semiconductor surface of the source and drain parts of the FET is ground to a depth of 60 nm and exposed p-type InG.
MOCVD (metal organic chemical vapor deposition) on the aAs layer 43
High concentration n-type InGaAs layer 46 and undoped I
The nAlAs layer 47 is continuously grown. The crystal growth at this time is selectively grown on the source and drain portions using the SiON film as a mask. The high-concentration n-type InGaAs layer 46 is S
The undoped InAlAs layer 47 is made of InyGa1-yAs (y = 0.53) with a thickness of 320 nm doped with i or Se at a concentration of 4E18 / cm ³ , and the thickness of the undoped InAlAs layer 47 is 50 nm.
InzAl1-zAs (z = 0.52).

Next, a SiON film is deposited and undoped In
A window is partially opened on the AlAs layer 47, the undoped InAlAs layer 47 is removed by an etching process using this as a mask, and a non-alloy ohmic electrode 49 is formed on the exposed high concentration n-type InGaAs layer 46. For the non-alloy ohmic electrode 49, for example, Ti / Pt / Au is used. Next, the second gate electrode 10 made of Mo / Pt / Au is formed on the undoped InAlAs layer 47 by the lift-off method.

After that, a low resistance metal 11 composed of Mo / Au / Mo is formed on the heat resistant gate electrodes 8 and wiring is performed on these electrodes to complete the integrated circuit.

In the second embodiment, the second gate electrode 1
0 may be Ti / Pt / Au and may be formed simultaneously with the non-alloy ohmic electrode 49. In this case, the process of manufacturing the integrated circuit can be shortened.

According to the second embodiment, the contact resistance between the non-alloy ohmic electrode 49 which is the cathode electrode of the diode and the high-concentration n-type InGaAs layer 46 can be reduced, and the parasitic resistance of the diode can be further increased as compared with the first embodiment. It can be reduced.
Therefore, the area of the diode can be reduced, and the band when used in the source follower circuit can be remarkably improved.

Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 6 is a cross-sectional structure diagram of the FET and the diode.
The difference from the first embodiment is that the FET and the diode are separated and the cathode electrode 59 of the diode is provided on the undoped GaAs layer 7.

According to this embodiment, the high-concentration n-type GaAs layer 6 can be formed in the source-drain of the FET and the cathode portion of the diode in the same process. A diode with low resistance can be formed on the same substrate.

[0038]

According to the present invention, it is possible to provide a field effect transistor and an integrated circuit which can reduce the parasitic resistance of a diode and can reduce the diode area, and which is optimum for ultra-high speed operation.

[Brief description of drawings]

FIG. 1 is a sectional view of a field effect transistor and a diode according to a first embodiment of the present invention.

FIG. 2 is a layout diagram of the source follower circuit according to the first embodiment of the present invention viewed from above.

FIG. 3 is a cross-sectional view of a conventional field effect transistor and diode.

FIG. 4 is a circuit diagram illustrating a source follower circuit.

FIG. 5 is a sectional view of a field effect transistor and a diode according to a second embodiment of the present invention.

FIG. 6 is a sectional view of a field effect transistor and a diode according to a third embodiment of the present invention.

[Explanation of symbols]

1 ... Semi-insulating GaAs substrate, 2 ... Undoped GaAs buffer layer, 3 ... P-type GaAs layer, 4 ... N-type InGaAs
Active layer, 5 ... Undoped AlGaAs layer, 6 ... High concentration n
Type GaAs layer, 7 ... undoped GaAs layer, 8 ... heat resistant gate electrode, 9 ... ohmic electrode, 10 ... second gate electrode, 11 ... low resistance metal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor ▲ Taka ▼ Hiroyuki Sawa 1-280, Higashi Koikeku, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Keiichi Kitamura 1-280, Higashi Koikeku, Kokubunji, Tokyo Stocks Central Research Laboratory of Hitachi, Ltd.

Claims (6)

[Claims] 1. An active layer formed on the surface of a compound semiconductor substrate, a first gate electrode formed at a position where an electric field can be applied to the active layer, and high-concentration impurity layers formed on both sides of the active layer. A field effect transistor comprising a source electrode and a drain electrode formed on the high-concentration impurity layer, wherein an undoped semiconductor layer and a second gate electrode are provided on the high-concentration impurity layer. Field effect transistor. 2. An n-type GaAs layer having an impurity concentration of 1E18 / cm ³ or more is used as the high-concentration semiconductor layer, and an undoped Ga is used as the undoped semiconductor layer.
A field effect transistor using an As layer. ^3. The n-type InGaAs having an impurity concentration of 1E18 / cm ³ or more as the high-concentration semiconductor layer according to claim 1.
Layer, and using undoped In as the undoped semiconductor layer
Field effect transistor using AlAs layer. 4. An integrated circuit including a source follower circuit composed of a field effect transistor and a level shift diode, comprising the field effect transistor according to claim 1, 2, or 3, wherein the second gate electrode is the source follower circuit. A compound semiconductor integrated circuit used as an anode electrode of a level shift diode of a circuit. 5. An active layer formed on the surface of a compound semiconductor substrate, a first gate electrode formed at a position where an electric field can be applied to the active layer, and high-concentration impurity layers formed on both sides of the active layer. In a field effect transistor including a source electrode and a drain electrode formed on the high-concentration impurity layer, an undoped semiconductor layer is provided between the high-concentration impurity layer and the source and drain electrodes. Impurity concentration of 1E18 / as semiconductor layer
A field effect transistor using an n-type GaAs layer of cm ³ or more and an undoped GaAs layer as the undoped semiconductor layer. 6. The method for manufacturing a field effect transistor according to claim 1, 2, 3 or 5, wherein a selective growth method is used for forming the high concentration impurity layer and the undoped semiconductor layer.