JP2645993B2 - Field effect type semiconductor device and method of manufacturing the same - Google Patents
Field effect type semiconductor device and method of manufacturing the sameInfo
- Publication number
- JP2645993B2 JP2645993B2 JP61137179A JP13717986A JP2645993B2 JP 2645993 B2 JP2645993 B2 JP 2645993B2 JP 61137179 A JP61137179 A JP 61137179A JP 13717986 A JP13717986 A JP 13717986A JP 2645993 B2 JP2645993 B2 JP 2645993B2
- Authority
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- Japan
- Prior art keywords
- layer
- gaas
- semiconductor device
- electrode
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 230000005669 field effect Effects 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 31
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 18
- 229910045601 alloy Inorganic materials 0.000 claims description 10
- 239000000956 alloy Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 6
- 239000007769 metal material Substances 0.000 claims description 5
- 240000002329 Inga feuillei Species 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/802—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 〔概要〕 InGaAsのノンアロイオーミックコンタクトを用いるこ
とにより、ゲート電極、ソース電極およびドレイン電極
を一度のプロセスで形成することを基本とする電界効果
型半導体装置及びその製造方法であり、高速，低消費電
力化を可能にする。DETAILED DESCRIPTION OF THE INVENTION [Outline] A field-effect semiconductor device based on forming a gate electrode, a source electrode and a drain electrode in a single process by using a non-alloy ohmic contact of InGaAs, and a method of manufacturing the same. Therefore, high speed and low power consumption can be achieved.
本発明はセルフアライン型GaAs電界効果型半導体装置
（FET）及びその製造方法に係り、特にその寄生抵抗を
低減し、高速，低消費電力化を可能にする電界効果型半
導体装置およびその製造方法に関する。The present invention relates to a self-aligned GaAs field-effect semiconductor device (FET) and a method of manufacturing the same, and more particularly, to a field-effect semiconductor device capable of reducing its parasitic resistance and achieving high speed and low power consumption, and a method of manufacturing the same. .
〔従来の技術〕 最近、化合物半導体装置の開発が盛んになってきてお
り、特に、GaAsMESFET（金属−半導体電界効果型トラン
ジスタ）は、Siの次のトランジスタとして注目されてい
る。[Related Art] In recent years, compound semiconductor devices have been actively developed, and in particular, GaAs MESFETs (metal-semiconductor field effect transistors) have attracted attention as the next transistor after Si.
第２図に従来のGaAsMESFETの要部断面構成を示してい
る。第２図において、21が半絶縁性のSI-GaAs基板であ
り、その上に活性層のn-GaAs層24が形成され、さらにソ
ース，ドレイン領域の高濃度なn+‐GaAs層22,23が形成
され、それぞれソース電極S,ドレイン電極D,およびゲー
ト電極Ｇが形成されている。しかしこの構造では、ゲー
ト電極Ｇに対して、n+‐GaAs層22,23がセルフアライン
で形成されていないので、ゲート電極Ｇとn+‐GaAs層2
2,23間に寄生的抵抗が生じ、ソース抵抗が高くなるとい
う問題がある。また、ゲートとソース，ドレイン間に活
性層24の比較的低抵抗のn-GaAs層が出ているので、表面
空乏層の影響で、しきい値Vthの均一性が悪くなるとい
う欠点が生じる。FIG. 2 shows a cross-sectional configuration of a main part of a conventional GaAs MESFET. In FIG. 2, reference numeral 21 denotes a semi-insulating SI-GaAs substrate, on which an n-GaAs layer 24 as an active layer is formed, and high-concentration n + -GaAs layers 22, 23 in source and drain regions. Are formed, and a source electrode S, a drain electrode D, and a gate electrode G are respectively formed. However, in this structure, since the n + -GaAs layers 22 and 23 are not formed in a self-aligned manner with respect to the gate electrode G, the gate electrode G and the n + -GaAs layer 2 are not formed.
There is a problem that a parasitic resistance is generated between 2 and 23, and the source resistance is increased. Further, since a relatively low-resistance n-GaAs layer of the active layer 24 is exposed between the gate, the source, and the drain, there is a disadvantage that the uniformity of the threshold value Vth is deteriorated due to the influence of the surface depletion layer.
そこで、この欠点を改善する従来の方法として、第３
図に示すように、ゲートに高耐熱金属のWSi（タングス
テンシリサイド）Ｇ′を用い、それをマスクにして、ソ
ース，ドレイン領域32,33用のn+層をイオン注入法で形
成し、その後、アニールを行い、ソース，ドレイン電極
領域を形成する方法がある。このセルフアライン型GaAs
MESFETは、ゲートとソースの間がn+の高濃度層になって
いるので、抵抗が低減するとともに、表面空乏層の影響
を回避して、しきい値の変動を防止することができる。
それにより、このセルフアライン型GaAsMESFETは寄生抵
抗，容量が小さくでき、高速、低消費電力化に有利であ
る。Therefore, as a conventional method for remedying this drawback, the third method
As shown in the figure, high-heat-resistant metal WSi (tungsten silicide) G 'is used for the gate, and using it as a mask, n + layers for the source and drain regions 32 and 33 are formed by ion implantation. There is a method of performing annealing to form source and drain electrode regions. This self-aligned GaAs
Since the MESFET has a high concentration layer of n + between the gate and the source, the resistance can be reduced, and the influence of the surface depletion layer can be avoided to prevent the threshold from fluctuating.
As a result, the self-aligned GaAs MESFET can reduce parasitic resistance and capacitance, which is advantageous for high speed and low power consumption.
しかしながら、上記改良されたセルフアライン型GaAs
MESFETは、セルフアライン化のために用いるゲート電極
のWSiの抵抗が高いことから、ゲートの抵抗が高くなる
という問題がある。However, the improved self-aligned GaAs
The MESFET has a problem that the resistance of the gate increases because the resistance of WSi of the gate electrode used for self-alignment is high.
本発明の目的はゲート抵抗を低減するとともに、プロ
セスが容易なセルフアライン型GaAsMESFETからなる電界
効果型半導体装置及びその製造方法を提供することにあ
る。SUMMARY OF THE INVENTION An object of the present invention is to provide a field-effect semiconductor device comprising a self-aligned GaAs MESFET in which the gate resistance is reduced and the process is easy, and a method of manufacturing the same.
本発明は上記問題点を解決するために、InGaAsのノン
アロイオーミックコンタクトを用いることにより、ゲー
ト電極，ソース電極およびドレイン電極を一度のプロセ
スで形成することを基本とするでセルフアライン型GaAs
MESFETを提供するものである。The present invention solves the above-mentioned problems by using a non-alloy ohmic contact of InGaAs to form a gate electrode, a source electrode and a drain electrode in a single process.
MESFET is provided.
従って、本発明の構成は以下に示す通りである。即
ち、GaAsを活性層（２）とした電界効果型半導体装置に
おいて、 該活性層（２）上にGaAsと格子整合する一導伝型の高
濃度InGaAs層（３）からなるソースおよびドレインのコ
ンタクト領域を有し、該各々のコンタクト領域を構成す
るInGaAs層（３）上およびGaAs活性層（２）上に同一金
属材料からなる電極が形成されてなることを特徴とする
電界効果型半導体装置としての構成を有する。Accordingly, the configuration of the present invention is as described below. That is, in a field effect type semiconductor device using GaAs as an active layer (2), a source and drain contact composed of a high conductivity type InGaAs layer (3) lattice-matched with GaAs on the active layer (2). A field-effect-type semiconductor device, characterized in that electrodes formed of the same metal material are formed on the InGaAs layer (3) and the GaAs active layer (2) constituting the respective contact regions. It has a configuration of
或いはまた、基板（１）上に活性層のGaAs層（２）を
形成する工程と、 該GaAs層（２）上に一導伝型の高濃度InGaAs層（３）
を形成する工程と、 該InGaAs層（３）のゲート領域部分を除去する工程
と、 その後、該ゲート領域および該InGaAs層（３）上に同
一金属材料を付着し、ソース電極（Ｓ）、ドレイン電極
（Ｄ）およびゲート電極（Ｇ）を同時にノンアロイで形
成する工程とを有することを特徴とする電界効果型半導
体装置の製造方法としての構成を有する。Alternatively, a step of forming a GaAs layer (2) as an active layer on the substrate (1), and a high conductivity type InGaAs layer (3) on the GaAs layer (2)
And removing the gate region of the InGaAs layer (3). Then, the same metal material is deposited on the gate region and the InGaAs layer (3), and the source electrode (S) and the drain Forming a non-alloy electrode (D) and a gate electrode (G) simultaneously at the same time as a method for manufacturing a field-effect semiconductor device.
InGaAsは金属電極とノンアロイで極めて良好なオーミ
ックコンタクトを形成することができる。そこで、本発
明においては、これに着目して、ソース及びドレインの
電極部にInGaAsを用いることにより、ソース，ドレイン
の金属電極にゲート電極の形成と同一金属を用い、同一
プロセスで形成することを可能にした。ノンアロイであ
ることから、ゲート電極形成後の熱処理が必要ないた
め、しきい値の変動がなく、また、ソース，ドレイン，
ゲートの各電極間の距離を正確に規定することができ、
製造歩留りを向上すると共に、素子の高速，低消費電力
化を可能にすることができる。InGaAs can form a very good ohmic contact with a metal electrode by using a non-alloy. In view of this, the present invention pays attention to this fact, and uses InGaAs for the source and drain electrode portions to use the same metal as the gate electrode for the source and drain metal electrodes and to form them in the same process. Made it possible. Since it is a non-alloy, there is no need for heat treatment after the gate electrode is formed, so there is no fluctuation in the threshold value.
The distance between each electrode of the gate can be precisely defined,
It is possible to improve the manufacturing yield and to achieve high-speed and low-power consumption of the element.
第１図に本発明の実施例としての電界効果型半導体装
置の製造工程の断面図を示しており、以下これを用い
て、本発明をさらに詳細に説明する。FIG. 1 is a cross-sectional view of a manufacturing process of a field-effect semiconductor device as an embodiment of the present invention, and the present invention will be described below in more detail with reference to FIG.
第１図（Ａ）参照 まず、GaAs半絶縁性（SI-GaAs）基板１上に、次の層
を順次形成する。Referring to FIG. 1A, first, the following layers are sequentially formed on a GaAs semi-insulating (SI-GaAs) substrate 1.
２…n-GaAs層 厚さ500Å キャリア濃度１×1018／cm3 ３…n-AlGaAs層 厚さ５Å キャリア濃度１×1018／cm3 AlXGal-XAsと表わすときのｘ＝0.3 ４…n+‐InGaAs層 厚さ2000Å キャリア濃度１×1019／cm3 InyGa1-yAsとしたときのｙ＝0.5 第１図（Ｂ）参照 その後、ゲート電極部をレジストパターン５をマスク
に用いて、CCl2F2で選択エッチングして窓開けする。エ
ッチングはn-AlGaAs層３で停止する。2 ... n-GaAs layer thickness 500Å Carrier concentration 1 × 10 18 / cm 3 3 ... n-AlGaAs layer thickness 5Å Carrier concentration 1 × 10 18 / cm 3 x = 0.34 when expressed as Al X Gal X As n + -InGaAs layer thickness 2000Å carrier concentration 1 × 10 19 / cm 3 in y Ga 1-y as and the y = 0.5 the first view of (B) see Thereafter, the gate electrode portion resist pattern 5 as a mask Then, a window is opened by selective etching using CCl 2 F 2 . The etching stops at the n-AlGaAs layer 3.
第１図（Ｃ）参照 次に、１回のマスク合わせでCr/Auにより、ソース電
極S,ドレイン電極Ｄのオーミックコンタクトおよびゲー
ト電極Ｇを一度に形成する。Next, referring to FIG. 1 (C), ohmic contacts of the source electrode S and the drain electrode D and the gate electrode G are formed at one time by Cr / Au by one mask alignment.
それには、例えば、Cr（クローム）をＥガン蒸着（電
子銃蒸着）で500Åの厚さに付着し、次に抵抗加熱式の
通常の蒸着でAuを3000Åの厚さに付着し、パターニング
して各電極を形成すれば良い。この場合、従来のAuGe/A
uのように、蒸着後アロイの熱処理を行わなくても極め
て低抵抗のオーミックコンタクトを形成することができ
るため、ゲート電極Ｇは熱処理を受けることがなく、し
きい値Vthの変動を生じることができない。To do this, for example, Cr (chrome) is deposited to a thickness of 500 mm by E-gun evaporation (electron gun evaporation), and then Au is deposited to a thickness of 3000 mm by normal resistance heating type evaporation and patterned. What is necessary is just to form each electrode. In this case, the conventional AuGe / A
As shown in u, since an ohmic contact with extremely low resistance can be formed without performing heat treatment of the alloy after vapor deposition, the gate electrode G is not subjected to heat treatment and the threshold voltage Vth may fluctuate. Can not.
n+‐InGaAs層４に対して、Cr/Auはノンアロイで極め
て低抵抗のオーミックコンタクトを形成でき、１×10-7
〜１×10-8Ωcm2という低いコンタクト抵抗を形成でき
る。against n + -InGaAs layer 4, Cr / Au may form an ohmic contact of very low resistance non-alloy, 1 × 10 -7
A contact resistance as low as 1 × 10 −8 Ωcm 2 can be formed.
以上のように１回のマスク合わせで、ゲート，ソース
およびドレイン電極相互がセルフアライン的に形成され
たFETを作製することができ、プロセスも容易化でき
る。また、ゲート電極Ｇとソース，ドレイン電極を構成
するn+‐InGaAs層４との間隔は高精度のステッパにより
0.1μｍ程度に近接して形成可能である。As described above, the FET in which the gate, source and drain electrodes are formed in a self-aligned manner can be manufactured by one mask alignment, and the process can be simplified. The distance between the gate electrode G and the n + -InGaAs layer 4 constituting the source and drain electrodes is determined by a high-precision stepper.
It can be formed close to 0.1 μm.
なお、上記実施例では、ソース，ドレイン電極および
ゲート電極の金属として、Cr/Auを示したが、本発明は
これに限らず、他の金属材料を用いることが可能であ
り、例えばTiPtAu、Au、Al等を用いることができ、従来
セルフアライン型とするために用いているWSiより抵抗
が（100分の１程度）小さな材料をゲートに用いること
が可能となる。In the above embodiment, Cr / Au is shown as the metal of the source, drain and gate electrodes. However, the present invention is not limited to this, and other metal materials can be used. For example, TiPtAu, Au , Al or the like can be used, and a material having a resistance (about 1/100) smaller than that of WSi conventionally used for a self-aligned type can be used for the gate.
以上のように、本発明によれば、InGaAsをオーミック
コンタクト形成用半導体層に用いることにより、蒸着後
アロイの熱処理を行わなくても極めて低抵抗のオーミッ
クコンタクトを形成することができるため、１回のマス
ク合わせで、ゲート，ソースおよびドレイン電極相互が
セルフアライン的に形成されたFETを作製することがで
き、プロセスも容易化できる。また、ゲート電極はアロ
イの熱処理を受けないため、しきい値Vthの変動が生じ
ることがない。また、従来のセルファライン型のGaAsME
SFETより低抵抗なゲート電極材料の採用を可能とする。As described above, according to the present invention, by using InGaAs for the semiconductor layer for forming an ohmic contact, an ohmic contact with extremely low resistance can be formed without performing heat treatment on the alloy after vapor deposition. By the mask alignment described above, a FET in which the gate, source and drain electrodes are formed in a self-aligned manner can be manufactured, and the process can be simplified. Further, since the gate electrode is not subjected to the heat treatment of the alloy, the threshold value Vth does not fluctuate. In addition, conventional self-aligned GaAsME
Enables the use of gate electrode material with lower resistance than SFET.
第１図（Ａ）〜（Ｃ）は本発明の実施例としての電界効
果型半導体装置の製造工程の断面図、 第２図は従来のGaAsMESFETの要部素子断面構造図（従来
例１）、 第３図は従来のタングステンシリサイドゲートを有する
GaAsMESFETの要部素子断面構造図（従来例２）である。 １……GaAs半絶縁性（SI-GaAs）基板 ２……n-GaAs層 ３……n-AlGaAs層 ４……n+‐InGaAs層 ５……レジストパターン 21,31……SI-GaAs基板 22,32……n+‐GaAs層（ソース領域） 23,33……n+‐GaAs層（ドレイン領域） 24……n-GaAs層（活性層） 34……活性層 Ｓ……ソース電極 Ｄ……ドレイン電極 Ｇ……ゲート電極 Ｇ′……（WSi:タングステンシリサイド）ゲート電極1 (A) to 1 (C) are cross-sectional views of a manufacturing process of a field-effect semiconductor device as an embodiment of the present invention. FIG. 2 is a cross-sectional structural view of a main part of a conventional GaAs MESFET (conventional example 1). FIG. 3 has a conventional tungsten silicide gate
FIG. 3 is a sectional view of a main part of a GaAs MESFET (conventional example 2). DESCRIPTION OF SYMBOLS 1 ... GaAs semi-insulating (SI-GaAs) substrate 2 ... n-GaAs layer 3 ... n-AlGaAs layer 4 ... n + -InGaAs layer 5 ... resist pattern 21,31 ... SI-GaAs substrate 22 , 32 ... n + -GaAs layer (source region) 23,33 ... n + -GaAs layer (drain region) 24 ... n-GaAs layer (active layer) 34 ... active layer S ... source electrode D ... ... Drain electrode G ... Gate electrode G '... (WSi: tungsten silicide) gate electrode
Claims (2)
において、 該活性層上にGaAsと格子整合する一導伝型の高濃度InGa
As層からなるソースおよびドレインのコンタクト領域を
有し、該各々のコンタクト領域を構成するInGaAs層上お
よびGaAs活性層上に同一金属材料からなる電極が形成さ
れてなることを特徴とする電界効果型半導体装置。1. A field effect type semiconductor device using GaAs as an active layer, wherein a first conductive high-concentration InGa that lattice-matches with GaAs is formed on the active layer.
A field-effect type having source and drain contact regions made of an As layer, and electrodes formed of the same metal material formed on the InGaAs layer and the GaAs active layer constituting the respective contact regions. Semiconductor device.
と、 該GaAs層上に一導伝型の高濃度InGaAs層を形成する工程
と、 該InGaAs層のゲート領域部分を除去する工程と、 その後、該ゲート領域および該InGaAs層上に同一金属材
料を付着し、ソース電極、ドレイン電極およびゲート電
極を同時にノンアロイで形成する工程とを有することを
特徴とする電界効果型半導体装置の製造方法。A step of forming a GaAs layer as an active layer on the substrate; a step of forming a high conductivity type InGaAs layer on the GaAs layer; and a step of removing a gate region portion of the InGaAs layer. And thereafter, a step of depositing the same metal material on the gate region and the InGaAs layer, and simultaneously forming a source electrode, a drain electrode, and a gate electrode in a non-alloy manner. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61137179A JP2645993B2 (en) | 1986-06-12 | 1986-06-12 | Field effect type semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61137179A JP2645993B2 (en) | 1986-06-12 | 1986-06-12 | Field effect type semiconductor device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62293679A JPS62293679A (en) | 1987-12-21 |
| JP2645993B2 true JP2645993B2 (en) | 1997-08-25 |
Family
ID=15192658
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61137179A Expired - Lifetime JP2645993B2 (en) | 1986-06-12 | 1986-06-12 | Field effect type semiconductor device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2645993B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01179461A (en) * | 1988-01-07 | 1989-07-17 | Fujitsu Ltd | Field-effect transistor |
| US5331410A (en) * | 1991-04-26 | 1994-07-19 | Sumitomo Electric Industries, Ltd. | Field effect transistor having a sandwiched channel layer |
| JPH05198598A (en) * | 1992-01-22 | 1993-08-06 | Mitsubishi Electric Corp | Compound semiconductor device and manufacture thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3005733A1 (en) * | 1980-02-15 | 1981-08-20 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PRODUCING A SEMICONDUCTOR ARRANGEMENT AND SEMICONDUCTOR ASSEMBLY PRODUCED BY THIS METHOD |
| JPS59123272A (en) * | 1982-12-28 | 1984-07-17 | Fujitsu Ltd | Compound semiconductor device |
-
1986
- 1986-06-12 JP JP61137179A patent/JP2645993B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62293679A (en) | 1987-12-21 |
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