JPS59113671A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To reduce the region for surface depletion layer minimizing the parasitic resistance such as source resistance, drain resistance etc. by a method wherein N<+> type ion implantation, a source electrode and a drain electrode are self-matched using a tapered insulating film as a mask. CONSTITUTION:An N type region 5 to be an active layer is formed on a semiinsulating substrate 1 by means of implanting ion such as Si etc. at the dose corresponding to the specified threshold value voltage of MESFET using a photoresist 3 as a mask. An insulating film 11 is etched to be tapered using another photoresist 12 as a mask. Furthermore an N<+> type region 4 is formed by means of implanting ion at higher dose. The insulating film 11 on the element forming part is partly etched using a photoresist mask 13 to expose an N<+> type region 4. AuGe/Ni etc. are vacuum evaporated to form a source electrode 7 and a drain electrode 8 while the resist 13 is removed and lifted off and then annealed at an optimum temperature to come into ohmic contact. Next another resist 15 is removed to form a photoresist on the insulating film 15 then a metal is formed and the photoresist is removed by means of lift off process to form a gate electrode 9.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a compound semiconductor field effect transistor.

Structure of a conventional example and its problems Figure 1 (al~(fI is a conventional gallium arsenide Schottky barrier gate field effect transistor (hereinafter referred to as GaAs
M: This is a diagram showing the manufacturing process of ESFET. First, as shown in FIG. 1(a), an insulating film 2 of Si3N4, 5i02, etc. is formed on a semi-insulating GaAS substrate 1,
Using the photoresist 3 as a mask, a window for ohmic implantation is opened by etching to reduce ohmic contact resistance. Next, as shown in FIG. 5B, ions such as Si are implanted at a high dose to form type 1 region 4.Next, as shown in FIG.
As shown in C1, a window for forming the active layer is opened using a similar photoresist method, and ions are implanted at a dose depending on the desired threshold voltage of the FET to form a N layer that will become the active layer.
A mold region 6 is formed. Next, as shown in FIG. 3(d), resist 3. After removing the insulating film 2, a new layer of Si3 is deposited on the entire surface of the substrate.
An insulating film 6 of N4 or the like is deposited, and annealing is performed at SO'C to 850'C to activate the ion implantation region.

Next, as shown in FIG. 7(e), a lift-off method is used to remove the source electrode 7. A drain electrode 8 is formed and annealed at a suitable temperature to obtain ohmic contact. Next, as shown in FIG. 3(f), a gate electrode 9 is formed using a similar lift-off method, and the process is completed.

Figure 2 shows the conventional GaAs MESFE thus formed.
A structural cross-sectional view of T is shown. In the conventional manufacturing method, the N4 region 4 and the source electrode 7. Since the drain electrode 8 is not self-aligned, the N-type regions between the gate electrode 9 and the source electrode 7 and between the gate electrode 9 and the drain electrode 8 become long, and therefore the surface depletion layer 10 formed there also becomes long. It will be formed over a wide area. As a result, parasitic resistances such as source resistance and drain resistance increase, resulting in deterioration of high frequency noise characteristics and reduction in transfer conductance. This becomes a big problem, especially when the N-type region 5 serving as the active layer becomes thin, as in an enhancement type FET.

In view of these conventional problems, the present invention provides a method for manufacturing a MESFET that almost eliminates the influence of the surface depletion layer and has low parasitic resistances such as source resistance and drain resistance.

Structure of the Invention The present invention has an ohmic furnace type region, a source electrode, and a drain electrode configured to be self-aligned with respect to the gate electrode, thereby forming a gap between the gate electrode and the source electrode and a gap between the sheet electrode and the drain electrode. Mli:5FET has a short length to minimize the area where the surface depletion layer is formed, and has low parasitic resistance such as source resistance and drain resistance.
This makes it possible to manufacture

Embodiment FIGS. 3(a) to 3(j) show M in an embodiment of the present invention.
It shows the manufacturing process of ESFET.

As shown in FIG. 3 Fa+, ions such as Si are applied to the semi-insulating substrate 1 using the photoresist 3 as a mask.
The N-type region 5, which will become an active layer, is formed by implanting at a dose depending on the desired threshold voltage of the ET.

Next, after removing the photoresist with A-7T, etc., the same figure (b) is shown.
As shown in FIG.
Deposit on an aAs substrate 1. Next, as shown in FIG. 3C, using the photoresist 12 as a mask, the insulating film 11 is etched using a CF4 isotropic dry etching device or the like, so that it is etched into a pattern.

In this case, all of the insulating film not covered with the photoresist 12 is left unetched in order to be used as an annealing protective film after ion implantation.

Next, as shown in the same figure (dl), ions are implanted at a high dose to form the N'' type region 4. In this case, the ions pass through the thin part of the insulating film 11, but the part covered with the photoresist 3 Assume that it does not pass.

Next, after removing the photoresist, annealing is performed at 800° C. to 850° C. as shown in FIG. As shown in the figure (fl), a certain amount of the insulating film 11 in the element formation area is etched using a photomask 13 to expose the W-shaped head region 4. Next, as shown in the figure (g), the source Electrode 7. AuGe/Ni or the like is vacuum-deposited as the drain electrode 8, and the resist 13 is removed, lifted off, and annealed at an appropriate temperature to obtain ohmic contact.In this case, on the insulating film 11 on the region 6, The electrode metal separates and deposits.Next, the same figure (
As shown in h), an insulating film 14 of 5iO7 or the like is vertically deposited using a sputtering method or the like. This insulating film 14 and insulating film 1
It is assumed that the material is different from 1 and can be selectively etched. In this case as well, the insulating film 14 is placed on the insulating film 11.
is separated and deposited.

Next, as shown in the same figure (1), the insulating film 1 of the element forming part
1 is selectively removed by dry etching the OF4 using the photoresist 15 as a mask.

In this case, the insulating film 14 is connected to the taper of the insulating film 11 and the source electrode 7. It is offset inward from the drain electrode 8. This offset amount X can be adjusted by adjusting the taper angle. Next, the regimen 15 is removed, a photoresist (not shown) is formed on the insulating film 15, metal is formed on the entire surface, and the photoresist is removed using a lift-off method, as shown in FIG. 3(j). As shown in FIG. 3, a gate electrode 9 is formed and the process is completed. Due to the offset amount X of the insulating film 14, the gate electrode 9 is closer to the source electrode 7. There is no short circuit with the drain electrode 8.

The above method according to the present example is based on the N'' region 4 and the source electrode 7 with respect to the gate electrode 9. The drain electrode 8 is self-aligned, so the distance between the gate electrode 9 and the source electrode 7' and the distance between the gate electrode 9 and the drain electrode 8 can be shortened, and the influence of the surface depletion layer formed in the region of this distance is extremely small. Parasitic resistances such as source resistance and drain resistance are reduced, and high frequency noise characteristics and transfer conductance are improved.

The above describes the process for annealing the insulating film 11 after ion implantation.
We will explain the process of using the film as a protective film (cap), but when using the capless annealing method in which the As pressure is released and annealed in an AsH1 atmosphere, the process shown in Fig. 3 f
In (1), etching is performed until the GaAg substrate 1 is exposed without leaving the insulating film 11, then ions are implanted into the resistive region 4, and after removing the photoresist, capless annealing is performed. In addition, as the insulating film 11, Si
3N4.

Although 5i02 has been described as the insulating film 14, the insulating film 1
Of course, it is only necessary that 1 be a combination in which the insulating film 14 can be selectively etched.

Figures 4(a) and 4(b) show MESFETs (gate length 1/!) manufactured using the conventional manufacturing process shown in Figure 1.
, m, gate width 2oμm, gate electrode, source electrode spacing.

The static characteristics of the gate electrode and drain electrode spacing (both 1 μm) (
The MESFET (gate length 1 μm, gate width 2
0 μm) (FIG. 2(b)). The ion implantation conditions for the N-type region 4 and this 1-type region of the active layer are respectively an acceleration voltage of 120 KeV, a dose of 3 x 1o12ctn-2, and an acceleration voltage of 170K.
eV, and the dose was set to 5×10 Cff. The source resistance Rs and transfer conductance gm of the two MESFETs (source, drain voltage 2V, source.

When the gate voltage ρV) is measured, the conventional example is shown in Fig. 4(a).
The one is RS = 54Ω + g ”””, 8”l)s
In the actual gun example of the present invention shown in FIG. 4(b), Rs=11Ω,
gn+=2. s;esmv, the source resistance decreased and the transfer conductance increased.

Effects of the Invention As is clear from the above explanation, the method for manufacturing a field effect transistor of the present invention involves implanting type 1 ions using a tapered insulating film as a mask, and self-aligning the source electrode and drain electrode with the gate electrode. As a result, the area where the surface depletion layer of the FET is formed can be made small, and the influence of the surface depletion layer can therefore be minimized, and the source resistance,
A field effect transistor with extremely low parasitic resistance of the drain resistance can be obtained.

[Brief explanation of the drawing]

Figures 1 (2L) to (2L) - (The opening is a sectional view showing the manufacturing process of a conventional field effect transistor, Figure 2 is a sectional view showing the structure of a conventional field effect transistor, and Figure 3 fa1 to (j) are sectional views showing the manufacturing process of a conventional field effect transistor. A cross-sectional view showing the manufacturing process of a field effect transistor in a case of leprosy, FIGS. 4(a) and 4(b) show the static characteristics of field effect transistors manufactured by the conventional manufacturing process and the manufacturing process of the present invention, respectively. It is a diagram. 1... Semi-insulating GaAs substrate, 3...
Photoresist film, 4...N+ type layer, 5...
... N-type layer, 7... Source electrode, 8...
...Drain electrode, 9...Gate metal, 11.
...Insulating film, 14...Insulating film. Name of agent: Patent attorney Toshio Nakao and 1 other person
1 @ b Figure 3 Figure 1 Figure 2rlA Figure 3 Figure 3 Figure 4 Making source dot Llli

Claims (1)

[Claims] a first step of forming a first insulating film on an N-type active layer formed on a semi-insulating substrate; a second step of etching the first insulating film so as to have a taper; a third step of ion-implanting N-type impurities into the semi-insulating substrate using the tapered first insulating film as a mask to form an ion-implanted layer; and after annealing the ion-implanted layer, the tapered Using the first insulating film with as a mask,
a fourth step of forming a source electrode and a drain electrode; a sixth step of forming a second insulating film using the tapered first insulating film as a mask; and a sixth step of forming a second insulating film using the tapered first insulating film as a mask. a sixth step of selectively etching the film;
The second insulating film is