JPH01256174A - Formation of gate electrode - Google Patents

Abstract

PURPOSE:To eliminate overlapped parts in formation of gate electrodes, by forming a gate pattern with an ordinary mesa shape before forming a reversed gate pattern, undercutting the side walls of the reversed gate pattern on the side of the gate electrode into an inverted mesa shape and forming the gate electrodes thinner than the reversed gate pattern. CONSTITUTION:A gate pattern 22 of ordinary mesa type is formed in gate regions on a semiconductor substrate 1 and doped layers 4S and 4D are formed in the gate regions on the substrate 1 by using the gate patterns 22 as a mask. An inorganic film 5 is formed on the gate patterns 22 as well as on the doped layers 4S and 4D and then the gate patterns 22 are removed, whereby the inorganic film 5 on the doped layers 4S and 4D are left as reversed gate patterns 5' of inverted mesa type which are undercut on the side of the gate regions. By using these reversed gate patterns 5' as a mask, gate electrodes 6S, 6D thinner, than the patterns 5' are formed. Thus, a gate electrode material 7 on the reversed gate patterns 5' can be isolated from the gate electrodes 6S, 6D on the active layer 3 without any overlapped part.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for forming a self-aligned gate electrode, which is used, for example, in manufacturing a Schottky gate field effect transistor (FET) using a compound semiconductor. be done.

[Conventional technology]

FETs are widely used as an essential element of semiconductor integrated circuits, and research into their miniaturization and high-speed performance is being actively pursued. A self-aligned (self-aligned) type gate electrode satisfies these requirements, and FvI
It is widely applied to ESFETs and the like, and one of its formation methods is called a replacement gate process. In this method, a gate pattern (dummy gate) is formed in the gate region using an insulating film, metal, or multilayer resist, and an inverted gate pattern is formed using this gate pattern as a mask. After annealing, a gate electrode is formed. The schematic structure near the gate of the resulting FET is as shown in FIG. 2, for example.

As shown in the figure, an active layer 5 is provided in the gate region of the semiconductor substrate 51.
2 is formed, and source and drain regions 533.53D doped with impurities at a high concentration are formed on both sides thereof. A gate electrode 55 and source and drain electrodes 56S are formed on the semiconductor substrate 51 through the opening of the insulating film 54.

56D is formed. However, according to this FET, the end of the gate electrode 55 extends to the top of the insulating film 54, and therefore the source and drain regions 53S, 53
There is a capacitance between D and the overlapping portion of the gate electrode, which deteriorates high-speed performance and high-frequency characteristics.

Therefore, the technology to remove this overlap part was developed by Extemporan Abstracts on the Seventeenth Conference on Solid State Devices and Materials (Extend
ed Abstracts of the 17thC
onference on 5olid 5tate
Devlces and Harterials) 19
85, PP, 413-416. An outline of this is shown in FIG. As shown in FIG. 5A, a first layer gate metal 55 made of molybdenum (Mo 2 ) and a second layer gate metal 57 made of gold (Au 2 ) are deposited on an insulating film 54 that is an inverted gate pattern. do. Next, only the Au layer 57 at the gate portion is left by ion milling, as shown in FIG. 5(b), and reactive ion etching (RIE)
The Mo layer 54 is removed. In this way, no overlapping portion appears on the gate electrode.

[Problem to be solved by the invention]

However, the manufacturing process of the above-mentioned conventional technology is extremely complicated. That is, a process of forming a plurality of metal layers, an ion milling process, and an RIE process are newly required, which not only lowers the yield but also increases the cost of the product.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for forming a gate electrode, which is simple, has a high yield, and can prevent overlapping portions from forming in the gate electrode.

[Means to solve the problem]

A method for forming a gate electrode according to the present invention is a method for forming a gate electrode in which a self-aligned gate electrode is formed on a semiconductor substrate. A first step of forming an impurity doped layer on both sides of the gate region of the semiconductor substrate using the gate pattern as a mask, and forming an inorganic film on the gate pattern and the impurity doped layer using, for example, ECR plasma CVD method. to form.

a third step, a fourth step in which the gate pattern is removed and the inorganic film on the impurity doped layer is made into an inverted mesa-type inverted gate pattern with an undercut on the gate region side; A fifth step of forming a gate electrode thinner than the inverted gate pattern. Here, the above first step may be a step of forming a gate pattern by exposing a low resolution resist, or a step of forming a gate pattern by exposing the resist in a defocused state. Alternatively, the gate pattern may be formed by patterning the resist and then causing the pattern to sag by heat treatment.

[Effect]

According to the present invention, the gate pattern made of resist is formed into a normal mesa shape before forming the inverted gate pattern,
Therefore, the sidewall of the inverted gate pattern on the gate electrode side has an inverted mesa shape (inverted tapered shape). Therefore, by forming a gate electrode thinner than the inverted gate pattern, the gate electrode material on the inverted gate pattern can be separated from the gate electrode on the active layer.

〔Example〕

Hereinafter, the present invention will be described in detail based on FIG. 1 of the accompanying drawings. In addition, in the description of the drawings, the same elements are given the same reference numerals, and redundant description will be omitted.

FIG. 1 is a cross-sectional view of an element showing steps in an example.

First, an ion implantation layer to become the active layer 3 is formed on the upper surface of the semiconductor substrate 1 made of, for example, gallium arsenide (GaAs) through a resist pattern 21 (FIG. 1(a)). Then, ion implantation layers to become the source and drain regions 4S and 4D are formed through another resist pattern 22 (FIG. 2(b)). Here, the resist pattern 22 has an inclined side surface as shown in FIG. 2A, and is a mesa-shaped gate pattern.

Such a forward mesa shape of the gate pattern (resist pattern 22) can be formed, for example, by using a low-resolution resist material, but even when a high-resolution resist material is used, it is difficult to defocus the exposure in the photolithography process. It can be achieved if you do it in good condition. Furthermore, even when the resist pattern is heated to a predetermined temperature after being formed, a normal mesa gate pattern as shown in the figure can be formed.

Next, as shown in FIG. 1(C), for example, silicon nitride (Si
An insulating film 5 made of 3N4) is formed.

This insulating film 5 is deposited using the ECR plasma CVD method. Thereafter, when the resist pattern 22 is removed using acetone or the like, an inverted gate pattern 5 made of the insulating film 5 is formed.
' is obtained (Fig. 1(d)). Here, the inverted gate pattern 5' has an inverted mesa shape (reverse tapered shape) on the gate region side, corresponding to the shape of the forward mesa type gate pattern (resist pattern 22). In this state, annealing is performed in an atmosphere containing As, for example, to activate the active layer 3 and the source and drain regions 4S and 4D. Then, source and drain electrodes 63.6D are formed by a lift-off method.

Next, the first resist film 23 is used as a three-layer mask.
, a second-layer inorganic film 24 and a third-layer resist film 25 are sequentially deposited, and the uppermost resist film 25 is patterned by photolithography (see FIG. 1(e)).
)). Thereafter, the inorganic film 24 exposed from the opening of the pattern of the resist film 25 is etched by RIE.
When the resist film 23 exposed from the opening of the pattern of the inorganic film 24 is etched by IE method or the like, the structure shown in FIG. 1(f) is obtained. Here, the opening of the inorganic film 24 is larger than the opening of the inverted gate pattern 5', and the resist film 23 is undercut from the opening of the inorganic film 24. Such an undercut of the resist film 23 can be easily realized by controlling the overetching time.

Next, gate electrode material 7 is deposited by vacuum evaporation or the like (
Figure 1(g)). Here, the deposited thickness of the gate electrode material 7 is made thinner than the thickness of the inverted gate pattern 5'. After that, the resist film 23 is removed with acetone or the like and unnecessary gate electrode material 7 is lifted off, as shown in the figure (h).
) structure is obtained. In this lift-off process, the resist film 23 is undercut with respect to the inorganic film 24, so that so-called "burr" does not occur at the end of the gate electrode material 7 on the inverted gate pattern 5'. What is important here is that the inverted gate pattern 5' has an inverted mesa shape, and the thickness of the gate electrode material 7 is thinner than that of the inverted gate pattern 5'.
The gate electrode material 7 (gate electrode) on the active layer 3 and the gate electrode material 7 on the inverted gate pattern 5' are separated. Therefore, since the gate electrode (flat gate electrode) without the above-mentioned overlapping portion can be realized in a self-aligned manner, capacitance will not occur in the overlapping portion.

Next, specific examples and examples carried out by the present inventors will be briefly described.

First, as a comparative example, high resolution resist (AZ-140
A gate pattern (dummy gate) was formed using 0), and an inverted gate pattern was formed using the ECR plasma CVD method. Then, a gate electrode was formed by lift-off using a three-layer resist pattern, and a gate electrode with a gate length of 0.7 μm was formed.
It was set as aAs-MESFET.

Next, as an example, a slightly lower resolution resist (OFP
R-800) was used to create a gate pattern with sloped sidewalls (
A dummy gate) was formed, and an inverted gate pattern was formed by ECR plasma CVD under the same conditions as in the comparative example.

Then, a gate electrode was formed by lift-off using the same three-layer resist pattern as in the comparative example, and the gate length was 0.7.
It was made into a μm GaAs-MESFET. Here, the gate electrode material on the inverted gate pattern was not electrically connected to the gate electrode on the active layer.

For both the comparative example and the example, the gate-source capacitance C
When measured, the capacity in the example was small at a ratio of 0.2 S p F / m11. Therefore, the high-frequency cutoff wave number fT of a transistor is determined as tT-g,/(2πφCgS), where g is the mutual conductance. According to the example, the high-speed and high-frequency properties are considerably higher than that of the comparative example. I found that it improved.

The present invention is not limited to the above embodiments, and various modifications are possible.

The reverse mesa shape (reverse taper shape) inverted gate pattern is
The present invention can also be realized by, for example, the following process without using a forward mesa-shaped gate pattern (dummy gate) as in the embodiment. First, a gate pattern (dummy gate) is formed using a high-resolution resist. The sidewalls of this gate pattern are not sloped. Next, 513N4 is deposited by ECR plasma CVD method. At this time, 513
The N4 deposition conditions are gradually changed to form 813N4, which is coarser at the bottom and denser toward the top.

Such density control can be performed by changing the ECR plasma conditions (microwave power, gas composition).

Next, after removing the gate pattern, the inverted gate pattern is lightly etched. Then, the inverted gate pattern consisting of 513N4 is undercut, so the first
An inverted mesa pattern similar to that shown in Figure (d) can be used.

The material of the gate pattern, the material of the inverted gate pattern formed by the ECR plasma CVD method, etc. are not limited to those of the embodiment, and various modifications are possible. In addition, the semiconductor substrate is also Ga
It is not limited to As, but can be applied to all ■-V group systems.

〔Effect of the invention〕

As described above, according to the method for forming a gate electrode of the present invention, the gate pattern made of resist is formed into a forward mesa shape before forming an inverted gate pattern, and therefore the sidewall of the inverted gate pattern on the gate electrode side is formed into an inverted mesa shape. becomes. Therefore, by forming a gate electrode thinner than the inverted gate pattern, the gate electrode material on the inverted gate pattern can be separated from the gate electrode on the active layer. Therefore, a self-aligned flat gate electrode with no overlapping portions can be realized with a high yield through a simple process.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of each process to explain an embodiment of the gate electrode forming method of the present invention, FIG. 2 is a cross-sectional view of a conventional MESFET, and FIG. 3 is a process of forming a conventional flat gate electrode. FIG. 1... Semiconductor substrate, 22... Resist pattern, 3
... Active layer, 5... Insulating film, 5'... Inverted gate pattern, 7... Gate electrode material. Process of Example (1/3) Process of Example (2/3) Figure 1 Process of sub-row (3/3) Figure 1 Cross-sectional view of conventional monofemale FET Figure 2

Claims (1)

[Claims] 1. In a method for forming a gate electrode in which a self-aligned gate electrode is formed on a semiconductor substrate, a mesa-shaped gate pattern with inclined sidewalls is formed using a resist in a gate region of the semiconductor substrate. a first step of forming an impurity doped layer on both sides of the gate region of the semiconductor substrate using the gate pattern as a mask;
a third step of depositing an inorganic film on the gate pattern and the impurity doped layer; and removing the gate pattern and undercutting the inorganic film on the impurity doped layer on the gate region side. and a fifth step of forming a gate electrode thinner than the inverted gate pattern using the inverted gate pattern as a mask. How to form. 2. The method for forming a gate electrode according to claim 1, wherein the first step is a step of forming the gate pattern by exposing a low resolution resist. 3. The method for forming a gate electrode according to claim 1, wherein the first step is a step of forming the gate pattern by exposing the resist in a defocused state. 4. The method of forming a gate electrode according to claim 1, wherein the first step is a step of patterning the resist and then forming the gate pattern into a mesa shape by heat treatment.