JP2657950B2 - Method of forming gate electrode - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a self-aligned gate electrode, for example, used for manufacturing a Schottky gate field effect transistor (FET) using a compound semiconductor. Is done.

[Conventional technology]

FETs are widely used as indispensable elements of semiconductor integrated circuits, and research on miniaturization and high speed has been actively pursued. The self-aligned (self-aligned) gate electrode satisfies such requirements and is widely applied to MESFETs and the like. One of the formation methods is a so-called replacement gate process. In this method, a gate pattern (dummy gate) is formed in a gate region with an insulating film, a metal or a multilayer resist, and an inverted gate pattern is formed using the gate pattern as a mask, and a gate electrode is formed after annealing. The schematic structure near the gate of the obtained FET is, for example, as shown in FIG.

As shown, an active layer 52 is provided in the gate region of the semiconductor substrate 51.
Are formed, and source and drain regions 53S, 53D heavily doped with impurities are formed on both sides thereof. On the semiconductor substrate 51, a gate electrode 55 and source and drain electrodes 56S and 56D are formed through an opening in the insulating film 54. However, according to this FET, the gate electrode 55
End portion extends to above the insulating film 54, and therefore has a capacitance between the source and drain regions 53S, 53D and the overlapping portion of the gate electrode, and the high-speed and high-frequency characteristics are reduced. .

Therefore, the technology to remove this overlap part,
Extended Abstracts Of The Seventeens Conference On Solid State Devices And Atrials (Extended
Abstracts of the 17th Conference on Solid State D
evices and Marterials) 1985, PP. 413-416. An outline of this is shown in FIG. As shown in FIG.
A first-layer gate metal 55 made of molybdenum (Mo) and a second-layer gate metal 57 made of gold (Au) are deposited on the insulating film 54 that is the inverted gate pattern. Next, the Au layer 57 at the gate portion is formed by ion milling as shown in FIG.
Mo layer 54 by reactive ion etching (RIE)
Is removed. In this case, no overlapping portion appears on the gate electrode.

[Problems to be solved by the invention]

However, in the above-described conventional techniques, the manufacturing process is extremely complicated. That is, a process for forming a plurality of metal layers, an ion milling process, and an RIE process are newly required, so that not only the yield is reduced but also the cost of the product is increased.

Therefore, an object of the present invention is to provide a method for forming a gate electrode which can prevent the overlap portion from being generated in the gate electrode with a simple process and a high yield.

[Means for solving the problem]

A method for forming a gate electrode according to the present invention is a method for forming a self-aligned gate electrode on a semiconductor substrate, wherein a forward mesa-type gate pattern having a sloped side wall in a gate region of the semiconductor substrate is formed using a resist. A first step of forming, a second step of forming an impurity-doped layer on both sides of the gate region of the semiconductor substrate using the gate pattern as a mask, and an inorganic film formed on the gate pattern and the impurity-doped layer by, for example, an ECR plasma CVD method. A fourth step of forming the inverted gate pattern by removing the gate pattern to form an inverted mesa inverted gate pattern in which the inorganic film on the impurity-doped layer is undercut on the gate region side; Forming a gate electrode thinner than the inverted gate pattern as a mask. Here, the first step may be a step of forming a gate pattern by exposing a low-resolution resist, or a step of forming a gate pattern by exposing the resist in a defocused state. Alternatively, a step of forming a gate pattern by patterning a resist, followed by patterning by heat treatment may be performed.

[Action]

According to the present invention, the gate pattern made of the resist is formed into a normal mesa shape before forming the inverted gate pattern, and therefore, the side wall on the gate electrode side of the inverted gate pattern has an inverted mesa shape (an inverted tapered shape). Therefore, by forming a gate electrode thinner than the inverted gate pattern,
The gate electrode material on the inverted gate pattern can be separated from the gate electrode on the active layer.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIG. 1 of the accompanying drawings. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description.

FIG. 1 is a cross-sectional view of the device showing the steps of the embodiment. First, a semiconductor substrate 1 made of, for example, gallium arsenide (GaAs)
An ion implantation layer to be the active layer 3 is formed by ion implantation through the resist pattern 21 on the upper surface of the first layer.
(A), an ion-implanted layer to be the source and drain regions 4S, 4D is formed via another resist pattern 22 (FIG. (B)). Where the resist pattern
22 has a sloped side surface as shown in FIG. 2A, and has a forward mesa gate pattern. Such a regular mesa shape of the gate pattern (resist pattern 22) can be formed by using, for example, a low-resolution resist material. However, even when a high-resolution resist material is used, the exposure in the photolithography process is defocused. It can be realized if done in a state. Further, even when the resist pattern is formed and then heated to a predetermined temperature, a forward mesa gate pattern as shown in the figure can be obtained.

Next, as shown in FIG. 1C, for example, silicon nitride (Si
₃ N ₄₎ forming an insulating film 5 made of. This insulating film 5 is made of ECR
It is deposited using a plasma CVD method. Thereafter, when the resist pattern 22 is removed with acetone or the like, an inverted gate pattern 5 'made of the insulating film 5 is obtained (FIG. 1 (d)). Here, the inverted gate pattern 5 'has an inverted mesa shape (an inverted tapered shape) on the gate region side corresponding to the shape of the forward mesa type gate pattern (resist pattern 22). In this state, annealing is performed in an atmosphere containing, for example, As to form the active layer 3, the source and drain regions 4
Activate S, 4D. And source and drain electrodes
6S and 6D are formed by a lift-off method.

Next, as a three-layer mask, the first resist film 2
3, the second inorganic film 24 and the third resist film 2
5 are sequentially deposited, and the uppermost resist film 25 is patterned by photolithography (FIG. 1 (e)). Thereafter, the inorganic film 24 exposed from the opening of the pattern of the resist film 25 is etched by RIE, and the RIE is performed.
When the resist film 23 exposed from the opening of the pattern of the inorganic film 24 is etched by a method or the like, the structure shown in FIG. 1F is obtained. Here, the opening of the inorganic film 24 is larger than the opening of the inverted gate pattern 5 ', and the resist film 23 is undercut from the opening of the inorganic film 24. Such undercut of the resist film 23 can be easily realized by controlling the over-etching time.

Next, a gate electrode material 7 is deposited by a vacuum evaporation method or the like (FIG. 1 (g)). Here, the deposited thickness of the gate electrode material 7 is made smaller than the thickness of the inverted gate pattern 5 '. Thereafter, when the resist film 23 is removed with acetone or the like to lift off the unnecessary gate electrode material 7, the structure shown in FIG. During this lift-off process,
Since the resist film 23 is undercut with respect to the inorganic film 24, so-called burrs do not occur at the end of the gate electrode material 7 on the inverted gate pattern 5 '. What is important here is that the inverted gate pattern 5 'has an inverted mesa shape, and the thickness of the gate electrode material 7 is smaller than that of the inverted gate pattern 5'. Gate electrode material 7 (gate electrode)
That is, the gate electrode material 7 on the inverted gate pattern 5 'is separated. Therefore, the gate electrode (flat gate electrode) having no overlap portion described above can be realized in a self-aligned manner, so that the capacitance at the overlap portion does not occur.

Next, specific examples and specific examples performed by the present inventors will be briefly described.

First, as a comparative example, a high-resolution resist (AZ-1400)
A gate pattern (dummy gate) is formed using
An inverted gate pattern was formed by the R plasma CVD method. Then, a gate electrode was formed by lift-off using a three-layer resist pattern to obtain a GaAs-MESFET having a gate length of 0.7 μm.

Next, as an example, a slightly lower resolution resist (OFPR
-800) to form a gate pattern (dummy gate) with inclined sidewalls, and ECR plasma C under the same conditions as in the comparative example.
An inverted gate pattern was formed by the VD method. Then, a gate electrode was formed by lift-off using the same three-layer resist pattern as in the comparative example, and a GaAs-M gate with a gate length of 0.7 μm was formed.
ESFET. Here, the gate electrode material on the inverted gate pattern was not electrically connected to the gate electrode on the active layer.

Gate-source capacitance for both the comparative example and the example
When C _gs was measured, the capacitance was small at a rate of 0.2 pF / mm in the example. Accordingly, the high band cut-off frequency f _T of the transistor, so determined transconductance as _{f T = g m / (2π} · C gs) is taken as g _m, according to the embodiment, rather than the comparative examples Fast Characteristics and high frequency characteristics were found to be improved.

The present invention is not limited to the above embodiments, and various modifications are possible.

The inverted gate pattern having the inverted mesa shape (inverted tapered shape) can be realized by, for example, the following process without using the forward mesa shaped gate pattern (dummy gate) as in the embodiment. First, a gate pattern (dummy gate) is formed using a high-resolution resist. The side wall of this gate pattern is not inclined. Next, Si ₃ N ₄ is deposited by ECR plasma CVD. At this time, Si ₃ N is gradually changed ₄ deposition conditions, rough bottom, and dense Si ₃ N ₄ toward the upper side. Such control of the density can be performed by changing the conditions (microwave power, gas composition) of the ECR plasma. Next, after the gate pattern is removed, the inverted gate pattern is lightly etched. Then, Si ₃ N ₄
Since the inverted gate pattern consisting of is undercut, an inverted mesa pattern similar to that shown in FIG. 1D can be obtained.

The material of the gate pattern, the material of the inverted gate pattern by the ECR plasma CVD method, and the like are not limited to those of the embodiment, and various modifications are possible. Further, the semiconductor substrate is not limited to GaAs or the like, and can be applied to all III-V group-based materials.

〔The invention's effect〕

As described above, according to the gate electrode forming method of the present invention, the gate pattern made of the resist is formed into a normal mesa shape before forming the inverted gate pattern, and therefore, the side wall on the gate electrode side of the inverted gate pattern becomes an inverted mesa shape. . Therefore, by forming a gate electrode thinner than the inverted gate pattern, the gate electrode material on the inverted gate pattern is
It can be separated from the gate electrode on the active layer. Therefore, a self-aligned flat gate electrode in which an overlap portion is not generated can be realized with a high yield by a simple process.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view for explaining one embodiment of a method for forming a gate electrode according to the present invention, FIG. 2 is a cross-sectional view of a conventional MESFET,
FIG. 3 is a cross-sectional view illustrating a step of forming a conventional flat gate electrode. 1 ... semiconductor substrate, 22 ... resist pattern, 3 ... active layer, 5 ... insulating film, 5 '... inverted gate pattern, 7
...... Gate electrode material.

Claims (4)

(57) [Claims] 1. A method for forming a self-aligned gate electrode on a semiconductor substrate, comprising: forming, in a gate region of the semiconductor substrate, a forward mesa gate pattern having a sloped side wall with a resist; Forming an impurity-doped layer on both sides of the gate region of the semiconductor substrate using the gate pattern as a mask;
A third step of depositing an inorganic film on the gate pattern and the impurity-doped layer; and removing the gate pattern to undercut the inorganic film on the impurity-doped layer on the gate region side. A fourth step of forming an inverted mesa-type inverted gate pattern, and a fifth step of forming a gate electrode thinner than the inverted gate pattern using the inverted gate pattern as a mask. Formation method. 2. The method according to claim 1, wherein said first step is a step of forming said gate pattern by exposing a low-resolution resist. 3. The method according to claim 1, wherein the first step is a step of forming the gate pattern by exposing the resist in a defocused state. 4. The method of forming a gate electrode according to claim 1, wherein said first step is a step of forming said gate pattern into a regular mesa shape by heat treatment after patterning said resist.