KR100266560B1 - Fabrication method of thin-film transistor - Google Patents

Abstract

PURPOSE: A method for fabricating a thin film transistor is to improve the characteristics of the thin film transistor by selectively forming an insulating layer between a doping layer and a gate. CONSTITUTION: A buffer layer(2) and an active layer(3) are formed in this order on a silicon substrate(1). Then, an insulating layer(8) is formed on the active layer, and then removed by using a mask to leave only a part of the insulating layer to be provided with a gate. A doping layer(4) is selectively grown on the active layer. A source(5) and a drain(6) are formed on the doping layer. A photoresist is formed on the source and the drain. Then, the insulating layer to be provided with the gate is removed by a lithography process. A gate electrode(7) is formed by depositing a metal on the insulating layer and the photoresist. Next, the photoresist and the metal are removed by a lift-off process, thereby manufacturing a thin film transistor.

Description

Thin film transistor manufacturing method

1 is a conventional thin film transistor structure diagram.

2a to c is a conventional thin film transistor manufacturing process diagram.

3 is a structure diagram of a thin film transistor of the present invention.

4a to d is a manufacturing process diagram of the thin film transistor of the present invention.

* Explanation of symbols for main parts of the drawings

1 silicon substrate 2 buffer layer

3: active layer 4: doping layer

5: source 6: drain

7 gate electrode 8 insulating film

9: photoresist

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of gallium arsenide (GaAs) mespets (MESFETs), and in particular, eliminates problems such as chemical reactions, recess etch forms, and etching depths generated during the recess etching process. In addition, the present invention relates to a method for manufacturing a thin film transistor that can more conveniently manufacture a T-type gate.

1 is a structure diagram of a conventional thin film transistor, in which a buffer layer 2, an active layer 3, and a doping layer 4 are successively formed on a silicon substrate 1 to form a pattern in a mesa shape. A source 5 and a drain 6 are formed on the doped layer 4, and a gate electrode 7 is formed on the etched active layer 3.

Referring to Figure 2 attached to a conventional thin film transistor manufacturing method configured as described above is as follows.

2a to c are conventional thin film transistor manufacturing process diagrams, as shown in FIG. 2a, a buffer layer 2, an active layer 3, and a doping layer 4 are successively stacked on a silicon substrate 1, followed by Mesa. Etching is performed, and as shown in FIG. 2B, metal is deposited on the doped layer 4, and then, a lithography process is performed to form a source 5 and a drain 6 pattern. As shown in FIG. 2C, after the recess etching with chemical etchant, a gate electrode 7 is formed on the exposed active layer 3, and then a lift-off process is performed. To prepare a thin film transistor.

However, the conventional thin film transistor manufacturing method described above uses a recess etching process, and the chemical reaction, the recess etching form, and the etching depth which occur at this time are pointed out as many problems.

In other words, because the surface oxidation and chemical state caused by etching through the chemical reaction (recess etching) are different, the recess etching is not always performed under the same conditions. Due to the bonding conditions, the process conditions can be shaken, resulting in poor Cdg, Cgs and breakdown voltages.

In addition, the depth of the etching etching performed to match the IDss varies greatly depending on the chemical state, and there is a problem in the balanced etching of the wafer, and there is a problem that there is a limitation of chemical etching as the gate length becomes smaller than 0.25 μm. .

In order to solve this problem, the present invention can selectively form an insulating film between the doping layer and the gate to improve the characteristics of the thin film transistor, to control the IDss by adjusting the thickness of the active layer, and to form a gate on the flat active layer Complementing the disadvantages caused by the recess etching, and devised a thin film transistor manufacturing method to reduce the resistance by depositing the gate, described in detail with reference to the accompanying drawings as follows.

FIG. 3 is a schematic diagram of a thin film transistor of the present invention, in which a buffer layer 2 and an active layer 3 are continuously formed in a mesa shape on a silicon substrate 1, and a doped layer 4 patterned on the active layer 3 is formed. ), An insulating film 8 is formed, a source 5 and a drain 6 are formed on the doped layer 4, and a gate electrode 7 is formed on the insulating film 8 to form a thin film transistor.

When described in detail with reference to Figure 4 attached to the present invention the thin film transistor manufacturing method configured as described above are as follows.

4A to 4D illustrate a process chart for manufacturing a thin film transistor according to the present invention. As shown in FIG. 4A, a buffer layer 2 and an active layer 3 are sequentially stacked on a silicon substrate 1, and then an insulating film 8 is formed on the active layer 3. After deposition), only the part where the gate is to be formed is left using a mask, and the remaining part is etched and removed. Here, when the thickness of the active layer 3 is deposited, the current IDss flowing to the active layer 3 can be controlled.

Thereafter, as shown in FIG. 4B, a doping layer (n + GaAs) 4 is selectively grown on the active layer 3 from which the insulating film 8 is removed, and then the device is insulated in a mesa shape to insulate the device. Then, as shown in FIG. 4C, a source 5 and a drain 6 are formed on the doped layer 4, and then a photoresist 9 is deposited thereon, and then an insulating film is defined where the gate is to be formed. (8) is removed by the lithography process.

Thereafter, as shown in FIG. 4D, the lithography process is performed again to be larger than the original gate length, and then metal is deposited on the insulating film 8 and the photoresist 9 to form the gate electrode 7.

Thereafter, the photoresist 9 and the metal thereon are removed by a lift-off process to manufacture a completed thin film transistor as shown in FIG.

As described above, the present invention selectively grows the doping layer to sufficiently increase the distance between the gate and the doping layer, and forms an insulating film therebetween to increase the breakdown voltage, and to control the thickness of the active layer. IDss can be precisely matched to improve overall uniformity in large-area wafer processing and reduce the complexity of gate fabrication.

Claims (2)

After the buffer layer (2), the active layer (3) is laminated on the silicon substrate (1) to form an insulating film (8) on the active layer (3), and optionally the doping layer (4) on the active layer (3) Growing and mesa etching to form a source (5) and a drain (6), depositing the photoresist (9) and removing the insulating film (8) in the gate forming portion by a lithography process, and forming a gate And forming a gate electrode (7) after the portion is formed in a larger lithography process. The method according to claim 1, wherein the current (IDss) can be controlled by adjusting the deposition thickness of the active layer (3).