JPS60165764A - Manufacture of compound semiconductor device - Google Patents
Manufacture of compound semiconductor deviceInfo
- Publication number
- JPS60165764A JPS60165764A JP2109984A JP2109984A JPS60165764A JP S60165764 A JPS60165764 A JP S60165764A JP 2109984 A JP2109984 A JP 2109984A JP 2109984 A JP2109984 A JP 2109984A JP S60165764 A JPS60165764 A JP S60165764A
- Authority
- JP
- Japan
- Prior art keywords
- film
- compound semiconductor
- layer
- gate electrode
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 150000001875 compounds Chemical class 0.000 title claims description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000001312 dry etching Methods 0.000 claims abstract description 5
- 239000003870 refractory metal Substances 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 claims description 2
- 150000003377 silicon compounds Chemical class 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 25
- 230000000694 effects Effects 0.000 abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 2
- 208000012868 Overgrowth Diseases 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- PXBRQCKWGAHEHS-UHFFFAOYSA-N dichlorodifluoromethane Chemical compound FC(F)(Cl)Cl PXBRQCKWGAHEHS-UHFFFAOYSA-N 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 239000011669 selenium Substances 0.000 description 1
- -1 silicide metals Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
本発明は、化合物半導体からなるヘテロ接合を用いるシ
ョットキー接合型の化合物半導体装置の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a Schottky junction type compound semiconductor device using a heterojunction made of a compound semiconductor.
（従来技術）
最近、化合物半導体装置、特にＧａＡＳシｍツ）キー型
電界効果トランジスタ（ＧａＡｓ ＭＢ２ ＦＥＴ又は
ＧａＡｓ ＳＢ ＦＥＴ）やＧａＡ ＩＡｓ等のへテロ
接合を用いるショットキー接合型の化合物半導体装置（
以下、ＧａＡｓ ＦＥＴという。）が、その高速性のた
めにシリコンデバイスに代るものとして熱心に検討され
ている。このためにはデバイスのチャネル長はサブミク
ロンの領域まで短くする必要があシ、この短チヤネル化
に伴ないそのしきい値電圧が低下を来すといういわゆる
短チヤネル効果の発生並びに寄生抵抗の増大という問題
がある。(Prior Art) Recently, compound semiconductor devices, especially GaAS semiconductors, Schottky junction type compound semiconductor devices using heterojunctions such as key field effect transistors (GaAs MB2 FETs or GaAs SB FETs) and GaA IAs (GaAs IAs) have recently been developed.
Hereinafter, it will be referred to as GaAs FET. ) are being actively considered as an alternative to silicon devices due to their high speed. To achieve this, it is necessary to shorten the channel length of the device to the submicron range, and as the channel length becomes shorter, the threshold voltage decreases, which is the so-called short channel effect, and parasitic resistance increases. There is a problem.
一方、これらの微細化によシ製造工程における目合せ露
光技術が厳しくなりなかなか要求を満足しきれないとい
う問題がある。On the other hand, due to the miniaturization of these devices, alignment exposure technology in the manufacturing process has become stricter, and there is a problem in that it is difficult to satisfy the requirements.
（発明の目的）
本発明の目的は、上記問題点を解消することにより、短
チヤネル兼効果の発生を抑制しかつ寄生抵抗を減少させ
た化合物半導体装置を厳しい目合せ露光技術によらずに
セルファライン法で製造できるところの化合物半導体装
置の製造方法を提供することにある。(Objective of the Invention) An object of the present invention is to solve the above-mentioned problems, thereby producing a compound semiconductor device that suppresses the occurrence of the short channel effect and reduces parasitic resistance without using strict alignment exposure technology. An object of the present invention is to provide a method for manufacturing a compound semiconductor device that can be manufactured by a line method.
（発明の構成）
本発明の化合物半導体装置の製造方法は、化合さ／
初生導体からなるヘテロ接合を用いるシロットキ接合型
の化合物半導体装置の製造方法において、半絶縁性基板
上に形成された化合物半導体からなるヘテロ接合基板上
にリフラクトリ金属又はそれらのシリサイド金属からな
るゲート電極を形成する工程と、引続き化学蒸着法等に
よりシリコン化金物からなる絶縁膜を被着し異方性エツ
チング法により前記絶縁膜を前記ゲート電極の側壁部分
のみを残して除去する工程と、引続き有機金属気相成長
法によシー導電型の高濃度化合物半導体層を所定の厚さ
に形成する工程と、引続きホトレジスト膜を前記ゲート
電極の厚さと前記高濃度化合物半導体層の厚さの和以上
の厚に塗布し所定の温度でベーキングを施す工程と、引
続き反応性ドライエツチング法等により前記ゲート電極
上の前記ホトレジスト膜及び前記高濃度化合物半導体層
を除去する工程とを含むことから構成される。(Structure of the Invention) A method for manufacturing a compound semiconductor device of the present invention is a method for manufacturing a compound semiconductor device of a Sirotki junction type using a heterojunction made of a compound/primary conductor. A step of forming a gate electrode made of a refractory metal or its silicide metal on a heterojunction substrate consisting of a step of removing the gate electrode leaving only the side wall portion thereof; a step of forming a high concentration compound semiconductor layer of the conductivity type to a predetermined thickness by metal organic vapor phase epitaxy; The photoresist film on the gate electrode and the photoresist film on the gate electrode are coated to a thickness greater than or equal to the sum of the thickness of the gate electrode and the thickness of the high concentration compound semiconductor layer and baked at a predetermined temperature, followed by a reactive dry etching method or the like. and removing the high concentration compound semiconductor layer.
（実施例）
以下、本発明の実施例について図面を参照して説明する
。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｇ）は、本発明を説明するための工程
順におけるＧａＡｓ ＦＥＴの断面図である。FIGS. 1(a) to 1(g) are cross-sectional views of a GaAs FET in order of steps for explaining the present invention.
（１）第１図（ａ）に示す様に、半絶縁性ＧａＡｓ基板
１上に形成された、アンドープＧａＡｓ層２とＮ型Ｇａ
１−）（ＡｌｘＡｓ層３からなるヘテロ接合基板上に、
従来一般に用いられているり７トオフ法又は反応性イオ
ンエツチング法等によシタンタル、タングステン又はそ
れらのシリサイド金属等のいわゆる高耐熱性のりフラク
トリ金属な被着加工してＧａＡｓ ＦＥＴのゲート電極
４を形成する。(1) As shown in FIG. 1(a), an undoped GaAs layer 2 and an N-type GaAs layer 2 are formed on a semi-insulating GaAs substrate 1.
1-) (On a heterojunction substrate consisting of an AlxAs layer 3,
The gate electrode 4 of the GaAs FET is formed by depositing a so-called high heat-resistant glue-fractory metal such as tantalum, tungsten, or their silicide metals by the commonly used glue-off method or reactive ion etching method. .
（２）引続き、第１図（ｂ）に示すように、プラズマ化
学蒸着法等によシリコン化金物
、？。(2) Subsequently, as shown in FIG. 1(b), siliconized metal is formed by plasma chemical vapor deposition or the like. .
高濃度Ｎ型ＧａＡｓ層６からゲート電極４端距離を所定
間隔とするために、所定の厚さくほぼ、シリコン窒化膜
厚と、ゲート電極４端一高濃度Ｎ型ＧａＡｓ層６間の距
離は同じである。）成長し、次いで方向性をもたせたフ
レオン系の反応性イオンエツチング例えば（ＣＦ４＋Ｈ
２）混合ガスにより異方性エツチングを施し、ゲート電
極４側壁にのみシリコン窒化膜５を、成長時の膜厚分を
高精度に残し他は除去する。これにより後に続く高濃度
Ｎ型ＧａＡｓ層６とゲート電極４端の間隔を精度良く、
シかも電気的に絶縁して保つことができる。In order to maintain a predetermined distance from the high concentration N-type GaAs layer 6 to the gate electrode 4 end, the thickness of the silicon nitride film and the distance between the gate electrode 4 end and the high concentration N-type GaAs layer 6 are approximately the same. It is. ) growth and then directional Freon-based reactive ion etching, e.g. (CF4+H
2) Anisotropic etching is performed using a mixed gas to leave the silicon nitride film 5 only on the side walls of the gate electrode 4 in the same film thickness as it was grown with high precision, and remove the rest. As a result, the distance between the subsequent high-concentration N-type GaAs layer 6 and the end of the gate electrode 4 can be adjusted with high precision.
Both can be kept electrically insulated.
（３）引続き、第１図（ｅ）Ｋ示すように、トリメチル
ガリウムとアルシン系、又は塩化アルキルガリウム−ア
ルシン系等を用いる有機金属気相成長法に５−
より、Ｎ型不純物としてはシリコン、セレン等の不純物
を添加した高濃度（キャリア濃度として５×１０１７１
／Ｃｍ３〜）Ｎ型ＧａＡｓ層６をゲート電極４の厚さ以
下に成長する。(3) Subsequently, as shown in FIG. 1(e)K, the N-type impurity is silicon, High concentration with impurities such as selenium added (5×10171 as carrier concentration)
/Cm3~) N-type GaAs layer 6 is grown to a thickness equal to or less than that of gate electrode 4.
（４）引続き、第１図（ｄ）に示すように、ホトレジス
トを、ゲート電極４の厚さをＡ、高濃度Ｎ Ｗ ＧａＡ
ｓ層６の厚さをＢとしたとき、（Ａ十Ｂ）の厚さ以上ス
ピンナー等によシ塗布しホトレジスト膜７を形成し、ホ
トレジストの軟化点温度（約１５０〜２５０°Ｃ）程度
の不活性雰囲気のオーブン中にてベーキングを施す。か
くして、第１図（ｄ）に示す如く、ゲート電極４上のレ
ジストは薄くゲート電極４より離れた領域では厚くレジ
ストがダした状態のホトレジスト膜７が出来上がる。(4) Subsequently, as shown in FIG. 1(d), a photoresist is applied to the gate electrode 4 with a thickness of A and a high concentration of N W GaA.
When the thickness of the s-layer 6 is B, the photoresist film 7 is formed by coating with a spinner or the like to a thickness of (A + B) or more, and the photoresist film 7 is formed at a softening point temperature of the photoresist (approximately 150 to 250°C). Bake in an oven with an inert atmosphere. In this way, as shown in FIG. 1(d), a photoresist film 7 is completed in which the resist on the gate electrode 4 is thin and the resist is thick in areas distant from the gate electrode 4.
（５）引続き、第１図（ｅ）に示すように、この状態で
フレオンに酸素を５〜ｌＯ％混合した反応性ドライエツ
チング法又は斜め照射によるイオンミリング法によりゲ
ート電極４上の薄くなったホトレジスト膜７のみを選択
的にエツチングして、ゲート電極４上の高濃度ＧａＡｓ
層・６が露出した時点で、さ６一
らに４塩化炭素又はジクロルジフルオロカーボン等の反
応性ドライエツチング法により、ゲート電極４上の不要
な高濃度ＧａＡｓ層６をゲート電極４側壁に形成したシ
リコン窒化膜５表面が露出するまでエツチングを行なう
。(5) Subsequently, as shown in FIG. 1(e), in this state, the thickness of the gate electrode 4 was thinned by a reactive dry etching method using Freon mixed with 5 to 10% oxygen or an ion milling method using oblique irradiation. Only the photoresist film 7 is selectively etched to remove the high concentration GaAs on the gate electrode 4.
Once the layer 6 was exposed, an unnecessary high concentration GaAs layer 6 on the gate electrode 4 was formed on the side wall of the gate electrode 4 by a reactive dry etching method using carbon tetrachloride or dichlorodifluorocarbon. Etching is performed until the surface of silicon nitride film 5 is exposed.
（６）引続き、第１図（ｆ）に示すように、ゲート電極
４上の不要な高濃度ＧａＡｓ層６の除去に用いたホトレ
ジストを有機溶剤により除去してから、一般のＧａＡｓ
ＦＥＴ製造工程で用いられているリフトオフ法等によ
シ所定領域にＡｕＧｅ ／Ｎ ｉ等のオーミック電極８
をソース及びドレインに被着後、約４００〜４５０℃で
熱処理を施してオーミックコンタクト層を膜層９を所定
の厚さ成長してゲート電極４等の表面保護を行なってか
らフォトリソグラフィーによりソース、ドレイン領域の
窓明けを非酸素エツチング液等により行なってから通常
半導体製造工程で用いられる蒸着法により所定厚のＴｉ
Ｐ辷Ａｕ層１０を被着して、ソース及びドレイン電極を
形成する。(6) Subsequently, as shown in FIG. 1(f), after removing the photoresist used to remove the unnecessary high concentration GaAs layer 6 on the gate electrode 4 with an organic solvent,
Ohmic electrodes 8 such as AuGe/Ni are formed in predetermined areas by the lift-off method used in the FET manufacturing process.
After depositing on the source and drain, heat treatment is performed at about 400 to 450°C to grow an ohmic contact layer 9 to a predetermined thickness to protect the surface of the gate electrode 4, etc., and then photolithography is performed to coat the source and drain. After opening a window in the drain region using a non-oxygen etching solution or the like, a predetermined thickness of Ti is deposited using a vapor deposition method commonly used in semiconductor manufacturing processes.
A P-thick Au layer 10 is deposited to form source and drain electrodes.
本実施例によれば、ソース及びドレイン電極は、ゲート
電極４に密接して形成された高濃度ＧａＡｓ層を介して
取出されているので、ＧａＡｓ ＦＥＴの寄生抵抗を最
大限に小さく、しかもＧａＡｓ ＦＥＴのゲの悪影響を
抑えて性能を向上させることができる。According to this embodiment, the source and drain electrodes are taken out through the high concentration GaAs layer formed in close contact with the gate electrode 4, so that the parasitic resistance of the GaAs FET can be minimized and the GaAs FET can be It is possible to improve performance by suppressing the negative effects of overgrowth.
また、製造工程においては、厳しい目合せ露光技術を駆
使することなしにセルファライン法により製造できるた
め製造工程が簡略になり、製品が高歩留りで生産できる
ことになる。In addition, in the manufacturing process, the manufacturing process can be simplified because it can be manufactured by the self-line method without using strict alignment exposure technology, and the product can be produced with a high yield.
（発明の効果）
以上、詳細説明したとおり、本発明によれば、上記の構
成により、短チヤネル効果の発生を抑制し、かつ寄生抵
抗を減少させた化合物半導体装置を、厳しい目合せ露光
技術によ・らずにセルファライン法で製造できる化合物
半導体装置の製造方法が得られる。(Effects of the Invention) As described in detail above, according to the present invention, the above structure allows a compound semiconductor device that suppresses the occurrence of short channel effects and reduces parasitic resistance to be suitable for strict alignment exposure technology. A method for manufacturing a compound semiconductor device that can be manufactured by the self-line method without any modification is obtained.
第１図（ａ）〜（ｇ）は本発明の一実施例を説明するた
めの工程順におけるＧａＡｓ ＦＥＴの断面図である。
１・・・・・・半絶縁性ＧａＡｓ基板、２・・・・・ア
ンドープＧａＡｓ層、３・・・・・Ｎ型Ｇａ１−ｘＡｌ
ｘＡｓ層、４・・・・・・ゲート電極、５・・・・・・
シリコン窒化膜、６・・・・・・高濃度Ｎ’ｆＪ Ｇａ
Ａｓ層、７・・・・・・ホトレジスト膜、８・・・・・
ＡｕＧｅ／Ｎｉ層、９・・・・・・シリコン酸化膜層、
１０・・・・・・ＴｉＰｔＡｕ層。
９−
（７）FIGS. 1(a) to 1(g) are cross-sectional views of a GaAs FET in order of steps for explaining an embodiment of the present invention. 1...Semi-insulating GaAs substrate, 2...Undoped GaAs layer, 3...N-type Ga1-xAl
xAs layer, 4...gate electrode, 5...
Silicon nitride film, 6... High concentration N'fJ Ga
As layer, 7... Photoresist film, 8...
AuGe/Ni layer, 9... silicon oxide film layer,
10...TiPtAu layer. 9- (7)
Claims (1)
接合型の化合物半導体装置の製造方法において、半絶縁
性基板上に形成された化合物半導体からなるヘテロ接合
基板上にリフラクトリ金属又はそれらのシリサイド金属
からなるゲート電極を形成する工程と、引続き化学蒸着
法等によシシリコン化合物からなる絶縁膜を被着し異方
性エツチング法により前記絶縁膜を前記ゲート電極の側
壁部分のみを残して除去する工程と、引続き有機金属気
相成長法により一導電型の高濃度化合物半導体層を所定
の厚さに形成する工程と、引続きホトレジスト膜を前記
ゲート電極の厚さと前記高濃度化合物半導体層の厚さの
和以上の厚に塗布し所定の温度でベーキングを施す工程
と、引続き反応性ドライエツチング法等によシ前記ゲー
ト電極上の前記ホトレジスト膜及び前記高濃度化合物半
導体層を除去する工程とを含むことを特徴とする化合物
半導体装置の製造方法。In a method for manufacturing a Schottky junction type compound semiconductor device using a heterojunction made of a compound semiconductor, a gate electrode made of a refractory metal or a silicide metal thereof is placed on a heterojunction substrate made of a compound semiconductor formed on a semi-insulating substrate. followed by a step of depositing an insulating film made of a silicon compound by chemical vapor deposition or the like and removing the insulating film by anisotropic etching leaving only the side wall portion of the gate electrode; A step of forming a high concentration compound semiconductor layer of one conductivity type to a predetermined thickness by metal vapor phase epitaxy, and subsequently forming a photoresist film to a thickness greater than or equal to the sum of the thickness of the gate electrode and the thickness of the high concentration compound semiconductor layer. and baking at a predetermined temperature, followed by a step of removing the photoresist film and the high concentration compound semiconductor layer on the gate electrode by a reactive dry etching method or the like. A method for manufacturing a compound semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2109984A JPS60165764A (en) | 1984-02-08 | 1984-02-08 | Manufacture of compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2109984A JPS60165764A (en) | 1984-02-08 | 1984-02-08 | Manufacture of compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60165764A true JPS60165764A (en) | 1985-08-28 |
Family
ID=12045420
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2109984A Pending JPS60165764A (en) | 1984-02-08 | 1984-02-08 | Manufacture of compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60165764A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62156876A (en) * | 1985-12-28 | 1987-07-11 | Matsushita Electronics Corp | Semiconductor device |
| JPS62177974A (en) * | 1986-01-31 | 1987-08-04 | Nec Corp | Manufacture of semiconductor device |
| JPS62200771A (en) * | 1986-02-28 | 1987-09-04 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPS63281473A (en) * | 1987-05-13 | 1988-11-17 | Nec Corp | Field-effect semiconductor device and manufacture thereof |
| JPS642370A (en) * | 1987-06-24 | 1989-01-06 | Nec Corp | Field-effect type semiconductor device and manufacture thereof |
-
1984
- 1984-02-08 JP JP2109984A patent/JPS60165764A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62156876A (en) * | 1985-12-28 | 1987-07-11 | Matsushita Electronics Corp | Semiconductor device |
| JPS62177974A (en) * | 1986-01-31 | 1987-08-04 | Nec Corp | Manufacture of semiconductor device |
| JPS62200771A (en) * | 1986-02-28 | 1987-09-04 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPS63281473A (en) * | 1987-05-13 | 1988-11-17 | Nec Corp | Field-effect semiconductor device and manufacture thereof |
| JPS642370A (en) * | 1987-06-24 | 1989-01-06 | Nec Corp | Field-effect type semiconductor device and manufacture thereof |
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