JPS62156876A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62156876A JPS62156876A JP29358685A JP29358685A JPS62156876A JP S62156876 A JPS62156876 A JP S62156876A JP 29358685 A JP29358685 A JP 29358685A JP 29358685 A JP29358685 A JP 29358685A JP S62156876 A JPS62156876 A JP S62156876A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- gate metal
- metal
- resistance
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、半導体装置に関するものである。[Detailed description of the invention] (Industrial application field) The present invention relates to a semiconductor device.
（従来の技術）
近年、半導体装置の金属膜の幅を充分狭く形成すること
が必要となっている。特に衛星放送の開始などに伴い、
１０ＧＨｚ以上の高周波を制御する装置として注目され
ているＧａＡｓＦＥＴを低雑音、高利得とするためには
、ゲート金属長を、０．３μｍ以下に短く形成すること
が必須条件である。(Prior Art) In recent years, it has become necessary to form a metal film of a semiconductor device with a sufficiently narrow width. Especially with the start of satellite broadcasting,
In order to make a GaAsFET, which is attracting attention as a device for controlling high frequencies of 10 GHz or more, low noise and high gain, it is essential to form the gate metal length as short as 0.3 μm or less.
以下１図面を参照しながら、上述したような従来の半導
体装置について説明する。A conventional semiconductor device as described above will be described below with reference to one drawing.
第２図は、従来の半導体装置の第１の例としてＭＥＳ
ＦＥＴの断面を示したものである。１は半導体基板の活
性層、２は半導体基板の低抵抗層、３は半導体基板の高
抵抗層、４はゲート金属、５は絶縁膜、６はソースまた
はドレイン金属である。Figure 2 shows an MES as a first example of a conventional semiconductor device.
It shows a cross section of an FET. 1 is an active layer of the semiconductor substrate, 2 is a low resistance layer of the semiconductor substrate, 3 is a high resistance layer of the semiconductor substrate, 4 is a gate metal, 5 is an insulating film, and 6 is a source or drain metal.
第３図は、従来の半導体装置の第２の例としてのＭＥＳ
ＦＥＴの断面を示したものである。第２図と同一符号
のものは同一のものを表わしている。FIG. 3 shows an MES as a second example of a conventional semiconductor device.
It shows a cross section of an FET. Components with the same reference numerals as in FIG. 2 represent the same components.
（発明が解決しようとする問題点）
しかしながら、上記のような従来構成では、ＦＥＴの特
性を左右するゲート金属長Ｑを０．３μｍ以下に短くす
ることはきわめてむずかしく、従って、高利得化するこ
とはきわめて困難であった。また。(Problems to be Solved by the Invention) However, in the conventional configuration as described above, it is extremely difficult to shorten the gate metal length Q, which influences the characteristics of the FET, to 0.3 μm or less, and therefore it is difficult to increase the gain. was extremely difficult. Also.
第２図の例では、ゲートとソース、ドレインとの間隔を
、製造上の問題から１μｍ以下にすることはきわめて困
雉であり、第３図のものでは、半導体基板の低抵抗層２
を形成するために、イオン注入のアニール温度８００°
Ｃにも耐える窩耐熱性金属しか、ゲート金属に使えない
という欠点を有していた。In the example shown in FIG. 2, it is extremely difficult to reduce the distance between the gate, source, and drain to 1 μm or less due to manufacturing problems, and in the example shown in FIG.
To form the ion implantation annealing temperature of 800°
The drawback is that only heat-resistant metals that can withstand C can be used as gate metals.
本発明は上記欠点に鑑み、ＦＥＴのゲート金属長を短く
するとともにソース・ゲート間抵抗を下げ、またゲート
に使用する金属を自由に選択できるようにして、より高
利得、低雑音の半導体装置を提供するものである。In view of the above drawbacks, the present invention shortens the gate metal length of the FET, lowers the resistance between the source and gate, and allows the metal used for the gate to be freely selected, thereby creating a semiconductor device with higher gain and lower noise. This is what we provide.
（問題点を解決するための手段）
上記問題点を解決するために１本発明の半導体装置は、
ＦＥＴのゲート金属、またはダイオードのショットキ
ー金属が半導体表面に形成した溝に、絶縁膜を介して埋
めこまれ、かつゲート金属またはショットキー金属の上
部が、埋めこまれた下部より太い構造となっている。(Means for Solving the Problems) In order to solve the above problems, a semiconductor device of the present invention includes:
The gate metal of an FET or the Schottky metal of a diode is embedded in a groove formed on the semiconductor surface via an insulating film, and the upper part of the gate metal or Schottky metal is thicker than the buried lower part. ing.
（作 用） 上記構成によれば、ゲートとソース間の間隔が。(for production) According to the above configuration, the distance between the gate and the source is.
溝の側壁とゲート間に挟まれた絶縁膜の厚さｔと等しく
なるため、非常に短くでき、ソース・ゲート間抵抗を下
げることができる。またゲート長は溝の幅と絶縁膜の厚
さによって制御でき、非常に短く形成することが可能と
なり、 ＦＥＴが低雑音、高利得になる。Since the thickness is equal to the thickness t of the insulating film sandwiched between the side wall of the trench and the gate, it can be made very short and the resistance between the source and gate can be lowered. Furthermore, the gate length can be controlled by the width of the groove and the thickness of the insulating film, making it possible to form it very short, resulting in FETs with low noise and high gain.
（実施例） 以下、実施例について、図面を参照しながら説明する。(Example) Examples will be described below with reference to the drawings.
第１図は１本発明の一実施例における半導体装置のＭＥ
Ｓ ＦＥＴの断面を示したものである。第１図において
、１は半導体基板の活性層、２は半導体基板の低抵抗層
、３は半導体基板の高抵抗層、４はゲート金属、５は絶
縁膜、６はソースまたはドレイン金属、ｅはゲート金属
長、ｔは溝の側壁とゲート金属４間に介在させた絶縁膜
５の膜厚である。FIG. 1 shows ME of a semiconductor device in one embodiment of the present invention.
It shows a cross section of S FET. In FIG. 1, 1 is the active layer of the semiconductor substrate, 2 is the low resistance layer of the semiconductor substrate, 3 is the high resistance layer of the semiconductor substrate, 4 is the gate metal, 5 is the insulating film, 6 is the source or drain metal, and e is the The gate metal length t is the thickness of the insulating film 5 interposed between the side wall of the trench and the gate metal 4.
以上のように構成された本実施例について、以下その動
作を説明する。The operation of this embodiment configured as above will be described below.
通常、ＦＩＥＴはゲートから信号が入力され、ドレイン
から出力される６利得及び雑音特性は、ゲート金属長、
ソース・ゲート間抵抗、ゲート金属の種類、グー１〜金
属抵抗に左右される。本実施例では、ゲート金属長αは
、絶縁膜５の厚さｔと溝の幅によって容易に制御され１
例えばｔｌｏ、４μｍ。Normally, in a FIET, a signal is input from the gate and output from the drain.6 Gain and noise characteristics are determined by the gate metal length,
It depends on the source-gate resistance, the type of gate metal, and the metal resistance. In this embodiment, the gate metal length α is easily controlled by the thickness t of the insulating film 5 and the width of the trench.
For example, tlo, 4 μm.
溝の幅を１ 、０ｐｍに設定すると、ゲート金属長Ｑは
０．２μｍとなり、きわめて短く設定することができる
。ソース・ゲート間隔もこの絶縁膜の厚さｔによってき
わめて短くすることができ、１μｍ以下にすることが容
易である。つまり、ソース・ゲート間抵抗を著しく下げ
ることができる。また、半導体基板の低抵抗層２もＦＥ
Ｔ作製前に予め形成しておけば良く、ゲート金属に耐熱
性金属を使用しなくて済み、ゲート金属を自由に選択す
ることが可能となる。さらに、ゲート金属の上部を太く
することができるので、グー１〜金属抵抗も従来のもの
に比べて１７２以下におさえることが可能である。If the groove width is set to 1.0 pm, the gate metal length Q will be 0.2 μm, which can be set extremely short. The source-gate interval can also be made extremely short by the thickness t of this insulating film, and can easily be made 1 μm or less. In other words, the source-gate resistance can be significantly reduced. Furthermore, the low resistance layer 2 of the semiconductor substrate is also made of FE.
It is sufficient to form the gate metal in advance before manufacturing the T, and there is no need to use a heat-resistant metal for the gate metal, making it possible to freely select the gate metal. Furthermore, since the upper part of the gate metal can be made thicker, it is possible to suppress the metal resistance to 172 or less compared to the conventional one.
以上のように、本実施例によれば、著しく高利得、低雑
音のＦＥＴを有する半導体装置を実現することができる
。As described above, according to this embodiment, a semiconductor device having an FET with extremely high gain and low noise can be realized.
なお、実施例では、シングル・ゲートＦＥＴについて説
明したが、デュアル・ゲートＦＥＴ、あるいはダイオー
ドでもよい。In the embodiment, a single gate FET has been described, but a dual gate FET or a diode may be used.
（発明の効果）
以上のように、本発明は、ＦＥＴのゲート金属またはダ
イオードのショットキー金属が半導体表面に形成された
溝に、絶縁体を介して埋めこまれ、ゲート金属またはシ
ョク１へキー金属の上部が、埋めこまれた下部より太く
構成されることにより、ゲート金属長を０．３μｍ以下
に、ソース・ゲート間抵抗を従来の２７３以下に、ゲー
ト金属抵抗を１／２以下に下げることが可能になる。ま
た、ゲート金属の種類を自由に選択することが可能で、
著しく高利得、低雑音の半導体装置を実現することがで
き。(Effects of the Invention) As described above, in the present invention, the gate metal of the FET or the Schottky metal of the diode is buried in a groove formed on the semiconductor surface via an insulator, and the gate metal or the Schottky metal of the diode is By making the upper part of the metal thicker than the buried lower part, the gate metal length is reduced to 0.3 μm or less, the source-gate resistance is reduced to 273 or less, and the gate metal resistance is reduced to less than half of the conventional value. becomes possible. In addition, it is possible to freely select the type of gate metal,
It is possible to realize semiconductor devices with extremely high gain and low noise.
その実用的効果は大なるものがある。Its practical effects are significant.
第１図は、本発明の一実施例における半導体装置のＭＥ
Ｓ ＦＥＴの断面図、第２図は、第１の従来例の半導体
装置のＭＥＳ ＦＥＴの断面図、第３図は、第２の従来
例の半導体装置のＭＥＳ ＦＥＴの断面図である。
１ ・・・半導体基板の活性層、 ２・・・半導体基板
の低抵抗層、 ３ ・・・半導体基板の高抵抗層、４
・・・ゲート金属、 ５ ・・・絶縁膜、 ６ ・・・
ソースまたはドレイン金属、ｅ・・・ゲート金属長、
ｔ ・・・絶縁膜厚。
特許出願人 松下電子工業株式会社
ｆ−１
第１図
２°°°平華棒庵反Ｉ）代底水麿
３゛°゛子＃俸（模の南芯犠盲
４・・・ プ゛−トε為
５・・・蛇ル縁
６・・・ ソー基 化はビレ４ン、金鳥Ｌ・・・胞オ伶
袂落
ｌ・・ ソ゛−ト心＆徒FIG. 1 shows ME of a semiconductor device in one embodiment of the present invention.
FIG. 2 is a cross-sectional view of the MES FET of the semiconductor device of the first conventional example, and FIG. 3 is a cross-sectional view of the MES FET of the semiconductor device of the second conventional example. 1... Active layer of semiconductor substrate, 2... Low resistance layer of semiconductor substrate, 3... High resistance layer of semiconductor substrate, 4
... Gate metal, 5 ... Insulating film, 6 ...
Source or drain metal, e...gate metal length,
t...Insulating film thickness. Patent applicant Matsushita Electronics Co., Ltd. To ε 5...Snake edge 6...Saw base is fin 4, Kintori L...Ball fall down l... Soto mind & soul
Claims (4)
形成されるとともに、前記電極と前記溝の側壁との間に
絶縁物が介在されていることを特徴とする半導体装置。(1) A semiconductor device characterized in that a groove is formed in the surface of a semiconductor, an electrode is formed in the groove, and an insulator is interposed between the electrode and a side wall of the groove.
ことを特徴とする特許請求の範囲第（１）項記載の半導
体装置。(2) The semiconductor device according to claim (1), wherein the electrode is a gate electrode of a field effect transistor.
極のショットキー障壁電極であることを特徴とする特許
請求の範囲第（１）項記載の半導体装置。(3) The semiconductor device according to claim (1), wherein the electrode is a Schottky barrier electrode of one electrode of a Schottky barrier diode.
とを特徴とする特許請求の範囲第（１）項、第（２）項
または第（３）項記載の半導体装置。(4) The semiconductor device according to claim (1), (2), or (3), wherein the top of the electrode is formed larger than the bottom.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29358685A JPS62156876A (en) | 1985-12-28 | 1985-12-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29358685A JPS62156876A (en) | 1985-12-28 | 1985-12-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62156876A true JPS62156876A (en) | 1987-07-11 |
Family
ID=17796643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29358685A Pending JPS62156876A (en) | 1985-12-28 | 1985-12-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62156876A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5220186A (en) * | 1990-12-26 | 1993-06-15 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with a mushroom-shaped gate electrode |
| US5252843A (en) * | 1989-09-01 | 1993-10-12 | Fujitsu Limited | Semiconductor device having overlapping conductor layers |
| US5409849A (en) * | 1990-01-24 | 1995-04-25 | Kabushiki Kaisha Toshiba | Method of manufacturing a compound semiconductor device having gate electrode self-aligned to source and drain electrodes |
| US5470767A (en) * | 1992-08-06 | 1995-11-28 | Mitsubishi Denki Kabushiki Kaisha | Method of making field effect transistor |
| US6002148A (en) * | 1995-06-30 | 1999-12-14 | Motorola, Inc. | Silicon carbide transistor and method |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5772384A (en) * | 1980-10-24 | 1982-05-06 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of field-effect transistor |
| JPS57103363A (en) * | 1980-12-18 | 1982-06-26 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of field effect transistor |
| JPS59205765A (en) * | 1983-05-09 | 1984-11-21 | Nec Corp | Manufacture of semiconductor device |
| JPS59222965A (en) * | 1983-06-02 | 1984-12-14 | Nec Corp | Manufacture of schottky barrier gate type field-effect transistor |
| JPS60779A (en) * | 1983-06-17 | 1985-01-05 | Nec Corp | Manufacture of semiconductor device |
| JPS6046074A (en) * | 1983-08-24 | 1985-03-12 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS60165764A (en) * | 1984-02-08 | 1985-08-28 | Nec Corp | Manufacture of compound semiconductor device |
| JPS6181673A (en) * | 1984-09-28 | 1986-04-25 | Sony Corp | Semiconductor device |
| JPS6240776A (en) * | 1985-08-15 | 1987-02-21 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1985
- 1985-12-28 JP JP29358685A patent/JPS62156876A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5772384A (en) * | 1980-10-24 | 1982-05-06 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of field-effect transistor |
| JPS57103363A (en) * | 1980-12-18 | 1982-06-26 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of field effect transistor |
| JPS59205765A (en) * | 1983-05-09 | 1984-11-21 | Nec Corp | Manufacture of semiconductor device |
| JPS59222965A (en) * | 1983-06-02 | 1984-12-14 | Nec Corp | Manufacture of schottky barrier gate type field-effect transistor |
| JPS60779A (en) * | 1983-06-17 | 1985-01-05 | Nec Corp | Manufacture of semiconductor device |
| JPS6046074A (en) * | 1983-08-24 | 1985-03-12 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS60165764A (en) * | 1984-02-08 | 1985-08-28 | Nec Corp | Manufacture of compound semiconductor device |
| JPS6181673A (en) * | 1984-09-28 | 1986-04-25 | Sony Corp | Semiconductor device |
| JPS6240776A (en) * | 1985-08-15 | 1987-02-21 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5252843A (en) * | 1989-09-01 | 1993-10-12 | Fujitsu Limited | Semiconductor device having overlapping conductor layers |
| US5409849A (en) * | 1990-01-24 | 1995-04-25 | Kabushiki Kaisha Toshiba | Method of manufacturing a compound semiconductor device having gate electrode self-aligned to source and drain electrodes |
| US5220186A (en) * | 1990-12-26 | 1993-06-15 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with a mushroom-shaped gate electrode |
| US5288654A (en) * | 1990-12-26 | 1994-02-22 | Mitsubishi Denki Kabushiki Kaisha | Method of making a mushroom-shaped gate electrode of semiconductor device |
| US5470767A (en) * | 1992-08-06 | 1995-11-28 | Mitsubishi Denki Kabushiki Kaisha | Method of making field effect transistor |
| US6002148A (en) * | 1995-06-30 | 1999-12-14 | Motorola, Inc. | Silicon carbide transistor and method |
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