JPS6237543B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a MOS type semiconductor device, and particularly to a method for manufacturing a MOS type semiconductor device with a small element area and high reliability.

In order to increase the degree of integration in MOS type semiconductor integrated circuit devices, attempts have been made to reduce the area of the elements and the length of the channels. However, when the channel is shortened, the depletion layer extending from the drain to the semiconductor substrate immediately reaches the source due to the voltage applied to the source and drain, resulting in a so-called punch-through phenomenon in which the source and drain are short-circuited. The disadvantage is that it is easier. This drawback is
One method is to increase the impurity concentration of the semiconductor substrate to suppress the expansion of the depletion layer into the semiconductor substrate, and the other is to use a semiconductor substrate with high specific resistance and to connect the semiconductor substrate through the diffusion hole to form the source region. There is a method of increasing the impurity concentration near the source region by diffusing impurities that provide the same conductivity type, and making it a so-called DSA (diffusion, self, align) type, in which only that region is effectively used as a channel. However, the former has the disadvantage that due to the high impurity concentration of the semiconductor substrate, the mobility of the minority chiaria flowing through the channel is reduced, which reduces the conductance of the channel and ultimately reduces the response speed of the element. arise. On the other hand, in the case of the latter DSA type device, the manufacturing process is complicated, and the structure of the channel part near the source region is different from the structure of the channel part near the drain region, so the source region and drain region are not interchangeable. That is, there is a drawback that it is difficult to use the source region and the drain region reversed, which poses a major obstacle in circuit design.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a MOS type semiconductor device which eliminates the above-mentioned drawbacks, has a small element area, a short channel length, and is less likely to cause punch-through.

A feature of the present invention is that the surface of at least one of the channel regions is formed at a deeper position than the depth of the portion adjacent to the channel region of at least one of the source and drain regions.

Another feature of the present invention is that after forming polysilicon for electrical connection to the source/drain regions, the polysilicon above the channel region and the surface of the semiconductor substrate in the channel region are removed by etching, and the source is etched in a self-aligned manner. , a channel portion deeper than the drain region is formed.

According to the present invention, since the channel portion is formed deeper than the source/drain region,
The depletion layer extending from the drain to the semiconductor substrate does not extend much toward the source, and has the great advantage that punch-through is less likely to occur because it extends only deep into the semiconductor substrate. Another advantage is that after forming the polysilicon for electrical connection to the source and drain, the polysilicon on the channel region and the semiconductor substrate are etched at the same time, making it self-aligned and effective in reducing the device area. It also has

Next, in order to better understand the present invention, the present invention will be explained using the drawings. FIG. 1 is a sectional view for explaining an embodiment of a MOS type semiconductor device and a method for manufacturing the same according to the present invention. In the MOS type semiconductor device of the present invention, as shown in FIG. The thick oxide films 103 and 103' are used in the field portions. Next, as shown in FIG. 1b, the nitride film 102
After removing the silicon substrate 101, polysilicon 10 containing impurities such as phosphorus gives N-type conductivity to the entire surface of the silicon substrate 101.
4 to full growth. Thereafter, as shown in FIG. 1c, a silicon oxide film 105 is grown on the polysilicon 104 by vapor phase growth, and using the silicon oxide film 105 as a mask, the polysilicon 104 selectively becomes the source/drain outlet. The portions other than those portions are etched away, the silicon substrate in the portion 106 where the channel will be formed is also etched, and the vapor grown oxide film 105 is further etched away. In this case, the etching depth of the silicon substrate is set to be deeper than the depth of the source and drain regions to be formed later. Finally, as shown in Figure 1d, the etched silicon substrate and polysilicon 1
After oxidizing the surface of polysilicon 04 to form a gate oxide film 107 and at the same time diffusing impurities in polysilicon 104 to form a source 108 and a drain 109, gate electrode metal 110 is applied to the source region, electrode metal 111 to the drain region Electrode metal 112 is formed to obtain MOS type semiconductor device 113 of the present invention.

According to this MOS type semiconductor device 113 of the present invention, the gate oxide film 107 in which a channel is formed
The silicon substrate surface below can be located below the source 108 and drain 109. Therefore, in the source 108 and the drain 109,
When a voltage that makes the drain 109 positive is applied, the silicon substrate 10 near the drain 109
The depletion layer extending into the silicon substrate 101 becomes very difficult to extend in the direction of the source 108 and easily extends into the silicon substrate 101 . Therefore, the depletion layer extends from the drain 109 to the source 108, and there is a great advantage that punch-through, in which the source 108 and the drain 109 become conductive, is extremely difficult to occur.

FIG. 2 is a sectional view for explaining another embodiment of the present invention. In this embodiment, field partial oxide films 202, 202' are first selectively formed on the surface of a P-type silicon substrate 201, as in FIG.
and then polysilicon 203 containing phosphorus.
grow. FIG. 2a Next, as shown in FIG. 2b, the polysilicon 203 is selectively etched to leave only the polysilicon 204 extending over the source region and the polysilicon 205 extending over the drain region, and then thermally oxidized. So, polysilicon 204,2
Oxide films 206, 206' formed by oxidizing 05
Then, an oxide film 207 is formed by oxidizing the silicon substrate 201. At this time, polysilicon 20
4,205 contains a large amount of n-type impurities such as phosphorus and has a high oxidation rate, so the oxide film 20
6, 206' is thicker than the oxide film 207 formed by oxidizing the silicon substrate 201.
When the entire oxide film is etched as shown in FIG.
7 will be removed, so if the silicon substrate 201 is etched in this state, it will be possible to form a recess 208 in the channel portion. After this, the same method as in the ordinary embodiment shown in FIG.
A MOS type semiconductor device can be obtained. This second
In this embodiment, when etching the silicon substrate 201, since an oxide film is formed on the side surfaces of the polysilicon 204 and 205, etching from the side is suppressed, and the polysilicon 204 and 205 are etched.
05 can be made smaller, while the recess 20
8 can be deep. Therefore, even if it is desired to increase the channel length, the channel length can be increased by deepening the recess 208, so the polysilicon 2
This has the great advantage that the interval between 04 and 205 can be narrowed and the degree of integration can be increased.

In the embodiment, the entire source and drain regions are formed by diffusion from the polysilicon layer, but this is not necessarily necessary; for example, the portions adjacent to the field oxide film may be subjected to another introduction step.
Diffusion from the polysilicon layer may be performed only in the portion adjacent to the channel portion. Furthermore, when the source and drain regions are formed in multiple steps and the depths of these regions are formed in a stepped manner, the channel surface is equal to the depth of the source and drain regions adjacent to the channel portion. The comparison should be deeper than this.

[Brief explanation of the drawing]

FIGS. 1a to 1d are cross-sectional views showing a first embodiment of the present invention in the order of steps, and FIGS. 2a to 2c are sectional views showing the second embodiment of the present invention in the order of steps. FIG. In the figure, 101, 201... silicon substrate, 102... silicon nitride film, 103, 10
3', 202, 202'... Field partial oxide film, 104, 203, 204, 405... Polysilicon, 105, 107, 206, 206', 2
07... Oxide film, 106... Channel forming part,
108... Source, 109... Drain, 11
0, 111, 112...metal wiring, 208...indentation.

Claims (1)

[Claims] 1. A process of forming a polysilicon film containing impurities that provides conductivity, covering at least the portions of the silicon substrate that will become the source and drain regions, and forming a polysilicon film that extends over the source region and a polysilicon film that extends over the drain region. selectively etching the polysilicon film while leaving the silicon film; oxidizing the silicon substrate portion between the source region and the drain region exposed by this selective etching and the surface of the polysilicon film; A process of forming a thin oxide film on the surface of the silicon substrate and a thick oxide film on the surface of the polysilicon film, and utilizing the difference in thickness between the oxide film on the polysilicon film and the oxide film on the silicon substrate. The oxide film on the silicon substrate is then etched away, and the oxide film on the polysilicon film is etched to remove only a portion of its thickness. A method for manufacturing a MOS type semiconductor device, which includes a step of etching to a depth deeper than at least one region of a substrate.