JPS6353977A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6353977A JPS6353977A JP19706286A JP19706286A JPS6353977A JP S6353977 A JPS6353977 A JP S6353977A JP 19706286 A JP19706286 A JP 19706286A JP 19706286 A JP19706286 A JP 19706286A JP S6353977 A JPS6353977 A JP S6353977A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- source
- film
- deposited
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 5
- 239000011259 mixed solution Substances 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 abstract description 3
- 229910017604 nitric acid Inorganic materials 0.000 abstract description 3
- 150000004767 nitrides Chemical class 0.000 abstract description 3
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 abstract description 2
- 239000011630 iodine Substances 0.000 abstract description 2
- 229910052740 iodine Inorganic materials 0.000 abstract description 2
- 239000007788 liquid Substances 0.000 abstract description 2
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 239000000243 solution Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PNDPGZBMCMUPRI-UHFFFAOYSA-N iodine Chemical compound II PNDPGZBMCMUPRI-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】 【発明の目的〕 （産業上の利用分野） 本発明は半導体装置の形状及びその形成方法に関する。[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a shape of a semiconductor device and a method of forming the same.
（従来の技術）
ＭＯＳ −ＦＥＴのショートチャネル効果を抑制するた
めにゲートのＭＯ３界面をＳｉ基板表面よりも深く作り
、実効的なソース、ドレイン部の接合深さを浅くした半
導体装置が知られている。第１図はその様な装置の断面
図を示したものである。第１図の構造は以下の工程によ
り形成される。第１の多結晶５ｉｌｌを堆積後ホトレジ
ストをマスクにしてゲート部のみＲＩＥエツチングする
１次いで熱酸化によりゲート酸化膜１２を形成後ゲート
電極用の多結晶５ｉ１３を堆積し、再びホトレジストを
用いエツチングにより電極を形成、その後熱酸化膜をゲ
ート部のみ残してエツチングする。次に第１の多結晶５
ｉｌｌをホトレジストでソース、ドレイン部を残しエツ
チング、酸化膜１４を全面に堆積した後、第１の多結晶
Ｓｉからの拡散によりソース、ドレイン拡散層１５を形
成する。この方法でＦ！造された半導体装置では実効的
なソース、ドレインの接合深さの制御がむずかしい、ソ
ース、ゲート、ドレイン間の絶縁がうまくとれない、ゲ
ート・ドレイン、ゲート・ソース間の容景が大きい、ゲ
ート酸化膜の角の部分に電界が集中し、ゲートリークが
起きやすいという問題がある。またエッチバックを用い
ているために工程が複雑になっている。(Prior art) In order to suppress the short channel effect of a MOS-FET, a semiconductor device is known in which the MO3 interface of the gate is made deeper than the surface of the Si substrate, thereby reducing the effective junction depth of the source and drain parts. There is. FIG. 1 shows a cross-sectional view of such a device. The structure shown in FIG. 1 is formed by the following steps. After depositing the first polycrystal 5ill, RIE etching only the gate portion using photoresist as a mask. 1. Next, form the gate oxide film 12 by thermal oxidation, deposit polycrystalline 5ill 13 for the gate electrode, and then etching the electrode using photoresist again. is formed, and then the thermal oxide film is etched leaving only the gate area. Next, the first polycrystal 5
After etching with photoresist and depositing an oxide film 14 on the entire surface, leaving only the source and drain portions, source and drain diffusion layers 15 are formed by diffusion from the first polycrystalline Si. F! with this method! In manufactured semiconductor devices, it is difficult to control the effective junction depth of the source and drain, it is difficult to maintain good insulation between the source, gate, and drain, the area between the gate and drain and between the gate and source is large, and gate oxidation There is a problem in that the electric field is concentrated at the corners of the film, making gate leakage more likely. Furthermore, the process is complicated because etchback is used.
（発明が解決しようとする問題点）
この発明は上述した従来装置の欠点を改良したもので実
効的なソース、ドレインの接合深さの制御、ソース、ゲ
ート、ドレイン間の絶縁が簡単にできる溝掘りゲートＭ
Ｏ３−ＦＥＴ製造プロセスを提供することを目的とする
。また本発明によりゲート・ドレイン、ゲート・ソース
間の容量が小さく、ゲート酸化膜角でのゲートリークの
少ない溝掘りゲートＭＯ３−ＦＥＴを提供することがで
きる。(Problems to be Solved by the Invention) This invention improves the above-mentioned drawbacks of the conventional device, and has grooves that can effectively control the junction depth of the source and drain and easily provide insulation between the source, gate, and drain. Digging gate M
The purpose is to provide an O3-FET manufacturing process. Further, according to the present invention, it is possible to provide a trench gate MO3-FET with small gate-drain and gate-source capacitances and less gate leakage at the gate oxide film angle.
（問題点を解決するための手段）
上記の問題点を解決するために１本発明はソース、ドレ
イン拡散層形成後、ゲート領域定義用の膜を堆積し、そ
れをホトレジストをマスクにしてエツチングし、次いで
開口部の拡散層のみを、低抵抗のＳｉを早くエツチング
する液またはＲＩＥとそれとの併用でエツチングした後
、熱酸化によりゲート酸化を形成、ゲート材料を全面堆
積後、リフトオフ法を用いてゲート部分のみゲート材料
を残しさらに絶縁膜を堆積してから、コンタクト部を形
成するというＭＯＳ −ＦＥＴ形成方法を特徴とする。(Means for Solving the Problems) In order to solve the above problems, one aspect of the present invention is that after forming the source and drain diffusion layers, a film for defining the gate region is deposited, and the film is etched using a photoresist as a mask. Then, only the diffusion layer in the opening is etched using a solution that quickly etches low-resistance Si or RIE and a combination thereof, gate oxidation is formed by thermal oxidation, gate material is deposited on the entire surface, and then a lift-off method is used. The method for forming a MOS-FET is characterized in that the gate material is left only in the gate portion, an insulating film is further deposited, and then a contact portion is formed.
（作用）
図２（ｂ）に低抵抗の８１のみを早くエツチングする液
によるエツチング後の形状。図２（Ｃ）にゲート酸化、
ゲート電極材料堆積後の形状を示す、ソース・ドレイン
拡散層のみがそのエツチング液で除去されるため拡散層
と基板との接合深さまでちょうどゲートが掘られる結果
となる。また液によるエツチングを用いているためゲー
ト酸化膜の形状はその角が丸い形状を示すとともに横方
向へのエツチングによりゲート電極とソース・ドレイン
拡散層の間にすき間を作る結果となる。(Function) Figure 2(b) shows the shape after etching with a solution that quickly etches only the low resistance 81. Gate oxidation is shown in Figure 2(C).
Since only the source/drain diffusion layer, which shows the shape after the gate electrode material is deposited, is removed by the etching solution, the gate is dug exactly to the depth of the junction between the diffusion layer and the substrate. Furthermore, since etching with a liquid is used, the shape of the gate oxide film has rounded corners, and the etching in the lateral direction creates a gap between the gate electrode and the source/drain diffusion layer.
（実施例）
次に本発明を１実施例につき図面を参照し詳述する０図
２（ａ）〜（ｅ）は本発明による半導体装置の形成方法
を概略説明するための断面図である。シリコン基板２０
表面に不純物、例えばボロンのイオン注入、拡散などに
よりソース、ドレイン用の拡散層２１を形成し、次にゲ
ート領域定義用のシリコン窒化膜２２を堆積させる０次
にホトレジストをマスクにして窒化膜をＲＩＥにより部
分的に除去しホトレジストを除去する。ついでフッ酸、
硝酸。(Embodiment) Next, one embodiment of the present invention will be described in detail with reference to the drawings. FIGS. 2(a) to 2(e) are cross-sectional views for schematically explaining a method of forming a semiconductor device according to the present invention. silicon substrate 20
Diffusion layers 21 for sources and drains are formed on the surface by ion implantation and diffusion of impurities, such as boron, and then a silicon nitride film 22 for defining gate regions is deposited.Next, the nitride film is deposited using photoresist as a mask. The photoresist is partially removed by RIE. Then hydrofluoric acid,
nitric acid.
酢酸及びヨウ素の混合液を用いてゲート部のＳｉの低抵
抗部のみを選択的に除去する。ゲート酸化膜２３を形成
した後ゲート電極として多結晶５ｉ２４を全面に堆積さ
せる。次にゲート部分以外の多結晶Ｓｉを熱リン酸を使
ったりフトオフ法により除去し、酸化膜２５を堆積し、
最後にホトエツチングによりコンタクト開口後アルミニ
ウムまたはアルミニウム合金２６を全面に堆積、ホトエ
ツチングにより電極配線を形成する。Using a mixed solution of acetic acid and iodine, only the low resistance portion of Si in the gate portion is selectively removed. After forming the gate oxide film 23, polycrystalline 5i 24 is deposited on the entire surface as a gate electrode. Next, the polycrystalline Si other than the gate portion is removed using hot phosphoric acid or by a foot-off method, and an oxide film 25 is deposited.
Finally, after contact openings are made by photo-etching, aluminum or aluminum alloy 26 is deposited on the entire surface, and electrode wiring is formed by photo-etching.
上の実施例ではフッ酸、硝酸、酢酸及びヨウ素の混合液
をＳｉの低抵抗部の選択エツチングに使用しているが、
この液のみのエツチングの他にＲ工Ｅ′で拡散層をある
適当までけずってから混合液でのエツチングをするとい
う方法を用いてもよい、またゲート電極材料として多結
晶Ｓｌを用いているがシリコン窒化膜と選択的にエツチ
ングできる材料ならば金属、シリサイドを問わない。In the above example, a mixed solution of hydrofluoric acid, nitric acid, acetic acid, and iodine is used for selective etching of the low resistance part of Si.
In addition to etching with only this solution, it is also possible to use a method in which the diffusion layer is etched to a certain extent with R-E' and then etched with a mixed solution.Also, polycrystalline Sl is used as the gate electrode material. Any material can be used, such as metal or silicide, as long as it can be selectively etched with the silicon nitride film.
本発明によれば実効的なソース、ドレインの接合深さを
常にほぼＯにすること、またソース、ゲート、ドレイン
の間隔を適当にとることが簡単にできる。またそれに伴
ってゲート・ドレイン、ゲート・ソース間の容量を小さ
くすること、ドレイン、ゲート、ソース電極間の絶縁を
確実にとることができ、掘った溝の底が丸まっているた
めにゲート酸化膜角での電界集中を少なくすることがで
きる。またリフトオフ法を用いているためレジスト工程
の数が通常のＭＯＳＦＥＴとかわらず、従来の方法より
少ないことも本発明の特徴である。According to the present invention, it is possible to easily maintain the effective junction depth of the source and the drain to be approximately O at all times, and to appropriately set the spacing between the source, the gate, and the drain. In addition, it is possible to reduce the capacitance between the gate and drain and between the gate and source, and to ensure insulation between the drain, gate and source electrodes. Electric field concentration at corners can be reduced. Another feature of the present invention is that because the lift-off method is used, the number of resist steps is the same as in a normal MOSFET, and is fewer than in conventional methods.
第１図は従来の半導体装置の断面図、第２図は本発明に
よる半導体装置の形成方法を示す説明図である。
１０・・・シリコン基板 １１・・・第１の多結晶５
１１２・・・ゲート酸化膜 １３・・・第２′＠、極
用多結晶５ｉ１４・・・シリコン酸化膜
１５・・・ソース、ドレイン拡散層
１６・・・電極配線用ＡＱ
１７・・・素子分離用シリコン酸化膜
２０・・・シリコン基板
２１・・・ソース、ドレイン用拡散層
２２・・・シリコン窒化膜 ２３・・・ゲート酸化膜
２４・・・ゲート電極用多結晶５ｉ
２５・・・シリコン酸化膜 ２６・・・電極配線用Ａ
Ｑ代理人 弁理士 則 近 憲 佑
同 竹花喜久男
第 ２ 図FIG. 1 is a sectional view of a conventional semiconductor device, and FIG. 2 is an explanatory diagram showing a method of forming a semiconductor device according to the present invention. 10... Silicon substrate 11... First polycrystal 5
112...Gate oxide film 13...2nd'@, polycrystalline 5i14...Silicon oxide film 15...Source and drain diffusion layer 16...AQ for electrode wiring 17...Element isolation Silicon oxide film 20...Silicon substrate 21...Diffusion layer 22 for source and drain...Silicon nitride film 23...Gate oxide film 24...Polycrystalline 5i for gate electrode 25...Silicon oxide Membrane 26...A for electrode wiring
Q Agent Patent Attorney Nori Chika Ken Yudo Kikuo Takehana Figure 2
Claims (1)
ン用不純物拡散層を形成し、この拡散層上にゲート領域
定義用の膜を堆積してホトエッチングでパターニングし
た後、低抵抗Ｓｉのみを選択的に早くエッチングするエ
ッチング液、若しくはこのエッチング液とＲＩＥエッチ
ングとの併用によりゲート用溝掘りを行ないゲート電極
をゲート領域定義用の膜を用いたリフトオフ法を用いて
形成することを特徴とする半導体装置の製造方法。In manufacturing trench gate MOSFETs, an impurity diffusion layer for the source and drain is formed, a film for defining the gate region is deposited on this diffusion layer, and after patterning by photoetching, only low resistance Si is selectively etched quickly. 1. A method of manufacturing a semiconductor device, comprising: digging a groove for a gate using an etching solution or a combination of this etching solution and RIE etching, and forming a gate electrode using a lift-off method using a film for defining a gate region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19706286A JPS6353977A (en) | 1986-08-25 | 1986-08-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19706286A JPS6353977A (en) | 1986-08-25 | 1986-08-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6353977A true JPS6353977A (en) | 1988-03-08 |
Family
ID=16368079
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19706286A Pending JPS6353977A (en) | 1986-08-25 | 1986-08-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6353977A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2844396A1 (en) * | 2002-09-06 | 2004-03-12 | St Microelectronics Sa | METHOD FOR PRODUCING AN INTEGRATED ELECTRONIC COMPONENT AND ELECTRIC DEVICE INCORPORATING AN INTEGRATED COMPONENT THUS OBTAINED |
-
1986
- 1986-08-25 JP JP19706286A patent/JPS6353977A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2844396A1 (en) * | 2002-09-06 | 2004-03-12 | St Microelectronics Sa | METHOD FOR PRODUCING AN INTEGRATED ELECTRONIC COMPONENT AND ELECTRIC DEVICE INCORPORATING AN INTEGRATED COMPONENT THUS OBTAINED |
| US7041585B2 (en) | 2002-09-06 | 2006-05-09 | Stmicroelectronics S.A. | Process for producing an integrated electronic component |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2837014B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS63140571A (en) | Bipolar transistor and manufacture thereof | |
| JPH0586673B2 (en) | ||
| JPH02100326A (en) | Manufacture of mos type semiconductor device high in breakdown strength | |
| JPH11163342A (en) | Semiconductor device | |
| JP2923768B2 (en) | Field effect transistor and method of manufacturing the same | |
| JP3528750B2 (en) | Semiconductor device | |
| JPS60145664A (en) | Manufacture of semiconductor device | |
| JPS6353977A (en) | Manufacture of semiconductor device | |
| JPS6245071A (en) | Manufacture of semiconductor device | |
| JPS6237543B2 (en) | ||
| JPH06232163A (en) | Vertical type mosfet device and its manufacture | |
| JP4439678B2 (en) | Manufacturing method of semiconductor device | |
| JPS60136377A (en) | Manufacture of semiconductor device with insulated gate | |
| JPH0682758B2 (en) | Method for forming semiconductor integrated circuit | |
| JPS6294985A (en) | Manufacture of mos semiconductor device | |
| JPH02183567A (en) | Manufacture of semiconductor device | |
| JPS63129664A (en) | Manufacture of semiconductor device | |
| JPH04256366A (en) | Field effect transistor and its manufacture | |
| JPS5914676A (en) | Manufacture of vertical type field effect transistor | |
| JPH0582066B2 (en) | ||
| JPS6229165A (en) | Manufacture of vertical semiconductor device | |
| JPH04250668A (en) | Semiconductor device and manufacture thereof | |
| JPH0334574A (en) | Mos type semiconductor device and manufacture thereof | |
| JPS61258476A (en) | Manufacture of semiconductor device |