JPS6294985A - Manufacture of mos semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the MOS semiconductor device which is effective for the enhancement in velocity of a device by reducing a junction capacity by reducing a junction area of a source and drain region diffusion layer of a MOS transistor and reducing a junction area with a channel stopper layer as much as possible. CONSTITUTION:On a P-type semiconductor substrate 1, a channel stopper region 2 is formed in an inactive region, followed by selective oxidation to form a field insulating oxide film 3, and a gate oxide film 4 is formed in an active region. Next, a gate electrode 5 and a thermal oxide film 6 are formed on the gate oxide film 4 by photo-etching technique, etc. By the sufficient thermal oxidation of the whole surface of the semiconductor substrate, thermal oxidation films 8 and 9 are formed on the P-type semiconductor substrate 1 and on a silicon nitride film 7, respectively. After removing the silicon nitride film selectively, an opening 10 is formed in the active region of the P-type semiconductor substrate 1 and a polysilicon layer 11 is formed. Next, the polysilicon layer 11 is patterned and an N-type diffusion layer 12 is formed by heat treatment. Then an interlaminar insulating film 13 is formed over the entire surface of the semiconductor substrate. Lastly, an opening 14 is formed and an aluminum electrode 15 is formed there.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a MOS type semiconductor device, and in particular, a method for forming a source/drain region diffusion layer, a contact portion, and a gate electrode in a self-aligned manner to achieve miniaturization. Suitable and source
[Related technology] Conventionally, the source and drain regions of an MOa transistor are formed using a self-alignment method with respect to a gate electrode and a field insulating layer. It was formed. Therefore, it had the structure shown in FIG. In FIG. 2, 101 is a P-type semiconductor substrate, 103
102 is a field insulating oxide film, 102 is a channel stopper of the same conductivity type as the substrate formed on the substrate surface directly under the field insulating oxide film region, 104 is a gate oxide film, 105 is a polycrystalline silicon gate electrode, and 106 is polycrystalline silicon. A thermal oxide film 107 formed on the outside of the gate electrode is a field insulating oxide film 103 and a polycrystalline silicon gate electrode 105.
, 106 are N-type diffusion layers for source and drain formed in a self-aligned manner, 108 is an interlayer insulating film, 109 is a contact portion, and 110 is an aluminum electrode.

[Problem that the invention seeks to solve]

In the above-mentioned conventional MOS transistor, it is necessary to prepare a sufficient area in advance to form a contact hole as a source/drain region diffusion layer, which is a major drawback in reducing the size and increasing the density of the device. had.

Furthermore, in the manufacturing method, the source/drain region diffusion layer is formed in a self-aligned manner with the gate electrode and the field insulating region, and therefore the source/drain region diffusion layer is formed as a channel stopper (source・The junction area between the drain/region and the high concentration impurity layer region of the opposite conductivity type is extremely large.

For the above reasons, conventional MOS! The structure of the transistor and the transistor formed by the manufacturing method limit miniaturization, and the junction capacitance of the source/drain/region diffusion layer is extremely large, making it unsuitable for increasing the speed of devices. There was a drawback.

An object of the present invention is to reduce the junction area of the source/drain region diffusion layer of a MOS transistor, and to
To provide a MOS type semiconductor device in which the junction area between a drain region diffusion layer and a channel stopper layer made of a high concentration impurity layer of the opposite conductivity type is minimized, thereby reducing the junction capacitance and being effective in increasing the speed of the device. There is a particular thing.

[Means for solving problems]

The method for manufacturing a MOSfi semiconductor device of the present invention includes a first conductor t.
forming an active region on a semiconductor substrate of m, forming a gate oxide film on the active region, and forming a gate electrode made of a first polycrystalline silicon containing impurities on the gate oxide film. a step of forming an oxide film on at least the side surfaces and an upper surface portion of the gate electrode; a step of forming an oxidation-resistant mask material on the side surface of the gate electrode via an oxide film; and a step of oxidizing the semiconductor substrate. removing the oxidation-resistant masking material, and exposing only the first conductivity type semiconductor substrate in the active region immediately below the region where the oxidation-resistant masking material was present, and the gate electrode being covered with an oxide film; forming and patterning a second polycrystalline silicon layer containing a second conductivity type impurity having a conductivity type opposite to that of the semiconductor substrate on the entire surface of the semiconductor substrate; patterning from the second polycrystalline silicon layer through the semiconductor substrate lead-out portion by heat treatment; and diffusing impurities of opposite conductivity type into the semiconductor substrate to form a source/drain/region. Consists of.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIGS. 1(a) to 1(h) are cross-sectional views of a MOS type semiconductor device shown in order of steps to explain an embodiment of the present invention.

First, as shown in FIG. 1 (al), a channel stopper region 2 is formed in an inactive region on a P-type semiconductor substrate l, and then selective oxidation is performed to form a field insulating oxide film 3, and a field insulating oxide film 3 is formed in an active region. A gate oxide film 4 is formed thereon.

Next, as shown in FIG. 1(b), a phosphorus-doped polycrystalline silicon layer is formed on the gate oxide film 4, and then a gate electrode 5 is formed by photoetching, and the entire substrate is thermally oxidized. Therefore, on the side surface of the gate electrode 5,
A thermal oxide film 6 is formed.

At this time, since the gate electrode 5 usually contains phosphorus at a high concentration, a thermal oxide film that is sufficiently thicker than that of the semiconductor substrate is formed against thermal oxidation. Then, a silicon nitride film 7 is formed on the entire surface of the semiconductor substrate by chemical vapor deposition.

Next, as shown in FIG. 1fc), anisotropic etching is performed to form a silicon nitride film 7 only on the side surfaces of the gate electrode.
leave.

Next, as shown in FIG. is formed.

Next, the thermal oxide film 9 is removed and the oxide film is etched to a sufficient degree to expose the silicon nitride film 7, but not to expose the P-type semiconductor substrate in the transistor element region. Thereafter, after selectively removing the silicon nitride film, an oxide film is further formed.

Next, as shown in FIG. 1ff), the entire surface of the semiconductor substrate is covered with
Polycrystalline silicon layer 1 containing N-type impurity, for example, phosphorus
form 1.

Next, as shown in FIG. 1(g), one polycrystalline silicon layer 1
By patterning 1 and performing heat treatment, an N-type diffusion layer 12 is formed, and an interlayer insulating film 13 is formed on the entire surface of the semiconductor substrate.
form.

Finally, the device of the present invention is completed by forming the opening 14 and forming the aluminum electrode 15.

〔Effect of the invention〕

As explained above, according to the manufacturing method of the present invention, the junction area of the source/drain region diffusion layer of a MOS transistor can be made extremely small, and the source/drain region diffusion layer is of the opposite conductivity type. The junction area with the channel stopper layer, which is a concentrated impurity layer, is minimized, and therefore the junction capacitance can be significantly reduced, which is extremely effective for increasing the speed of devices.

[Brief explanation of drawings]

FIGS. 1(a) to (h) are cross-sectional views of a MOS type semiconductor element shown in the order of steps for explaining one embodiment of the present invention;
FIG. 2 is a cross-sectional view of an example of a conventional MOS type semiconductor device. 1, 101...P-type semiconductor substrate, 2, 102
・・・・・・Channel stopper, 3,103・・Group・Field insulating oxide film, 4,104・・Mountain・・Gate oxide film, 5,105・・・・Polycrystalline silicon gate electrode, 6,8 , 9, 106... thermal oxide film, 7...
...Silicon nitride film, 10... P-type semiconductor substrate opening, 11... Polycrystalline silicon layer, 12, 107... N-type diffusion layer, 13, 1
08... Interlayer insulating film, 14... Polycrystalline silicon layer opening, 15... Aluminum electrode, 109 Old... Contact part. Agent Patent Attorney Uchihara 2 ′□・・・′・l
:j:;:,z \1. -Ippin 1 Tuwan 2

Claims (2)

[Claims] (1) Forming an active region on a semiconductor substrate of a first conductivity type, forming a gate oxide film on the active region, and forming a first polycrystalline silicon containing impurities on the gate oxide film. a step of forming an oxide film on at least side and top surfaces of the gate electrode; a step of forming an oxidation-resistant mask material on the side surfaces of the gate electrode via an oxide film; oxidizing the substrate, removing the oxidation-resistant masking material, and exposing only the first conductivity type semiconductor substrate in the active region immediately below the region where the oxidation-resistant masking material was present, and The gate electrode includes a step of removing an oxide film so that it is covered with an oxide film, and a second polycrystalline silicon layer containing impurities of a second conductivity type opposite to that of the semiconductor substrate on the entire surface of the semiconductor substrate. forming and patterning the semiconductor substrate, and heat-treating the semiconductor substrate to diffuse impurities of a conductivity type opposite to that of the semiconductor substrate from the second polycrystalline silicon layer through the exposed portion of the semiconductor substrate to form a source. An MO characterized by comprising the step of forming a drain region.
A method for manufacturing an S-type semiconductor device. (2) The method of manufacturing a MOS type semiconductor device according to claim (1), wherein the oxidation-resistant mask material is a silicon nitride film.