JPS6245071A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the reproducibility of the gate electrode length by a method wherein an impurity diffusion layer having a concentration higher than the diffusion layer is formed by self alignment by means of the ion implantation with a thermal oxide silicon film as a mask in a region which is spaced apart from the end of the gate electrode by the thickness of the silicon oxide film on the sides of the silicide layer. CONSTITUTION:After sequentially laminating and forming a gate oxide film 12, polycrystalline silicon layer 13 and high-melting point metal silicide layer 14 on a semiconductor substrate 11, the region of the laminate except for a predetermined gate electrode pattern is etched away, and impurity ions 19 of the conductivity type opposite to the substrate are implanted onto the substrate by self alignment with respect tot he gate electrode pattern, forming, a low concentration diffusion layer 15. Then, a heat treatment is applied, forming a thermal oxide silicon film 17 on the substrate surface and the gate electrode surface. The impurity ions 19 exhibiting the conductivity type opposite to the substrate are implanted in high concentration onto the substrate, forming a high concentration diffusion layer 16 having one end in a region which is spaced apart from the end of the gate electrode by the thickness of the oxide film on the sides of the high-melting point silicide layer.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and relates to a method for manufacturing a semiconductor device.
The present invention relates to a method of manufacturing a field effect transistor having a (Lightly Doped Drain) structure.

[Conventional technology]

Conventionally, as a method for forming a field effect transistor having an LDD structure, for example, a method as shown in FIG. 2 is known. First, as shown in FIG. 2, a gate oxide film 22 is formed on a semiconductor substrate 21, and a gate electrode pattern having a silicon nitride film 28 on a polycrystalline silicon layer 23 is anisotropically formed in a predetermined region thereon. Formed by etching method. Next, as shown in FIG. 2), using the silicon nitride film 28 as a mask, the polycrystalline silicon layer 23 is removed by isotropic etching to form a gate electrode. Make the end protrude like a canopy. Next, using the silicon nitride film 28 as a mask, impurity ions 29t- ions having a conductivity type opposite to that of the substrate are implanted onto the semiconductor substrate 21 to form a high concentration diffusion layer 26. Next, as shown in FIG. 2(C), a silicon nitride film 2
After removing 8, impurity ions 29 having the same conductivity type as the high concentration diffusion layer 26 are implanted onto the substrate using the polycrystalline silicon layer 23 as a mask in a smaller amount than the ion implantation amount to form the low concentration diffusion layer 25. form. This results in
Channel region under gate oxide film 22 and high concentration diffusion layer 26
An LDD structure is obtained in which the two are connected via the low concentration diffusion layer 25.

[Problem that the invention seeks to solve]

In the conventional manufacturing method of a field effect transistor having an LDD structure described above, when forming a gate electrode, a predetermined amount of the polycrystalline silicon layer is etched away using an isotropic etching method, but since it is difficult to control the amount of etching, the polycrystalline silicon layer is It is difficult to obtain the length after etching, that is, the gate electrode length, with good reproducibility, and it is difficult to realize a short channel transistor that reflects the design value with good reproducibility.

In addition, poor reproducibility of the gate electrode length means poor reproducibility of the length of the low concentration diffusion layer region located between the end of the gate electrode and the end of the high concentration diffusion layer, which in turn leads to poor reproducibility of the transistor's mutual conductance. This means that the reproducibility of is poor, which causes difficulties in transistor circuit design. Furthermore, the length of the gate electrode made of the polycrystalline silicon layer when the transistor is completed is shorter than the gate mask dimension by the amount of isotropic etching, so it is necessary to estimate the gate electrode length larger in advance when designing the transistor. Therefore, when a plurality of transistors are arranged, the degree of integration cannot be increased, and there is no advantage of using the LDD structure of the transistors to shorten the channel.

[Means for solving problems]

A method for manufacturing a semiconductor device according to the present invention includes forming a gate electrode having a two-layer structure consisting of a lower polycrystalline silicon layer and an upper refractory metal silicide layer on a -conductivity type semiconductor substrate via a gate insulating film. forming a low concentration impurity diffusion layer of opposite conductivity type on the substrate in a self-aligned manner by masking the gate electrode and using an ion implantation method; heating the surface of the substrate and the surface of the gate electrode; oxidizing to form a silicon oxide film thicker than the substrate surface and the side surfaces of the polycrystalline silicon layer of the gate electrode on the side and top surfaces of the silicide layer of the gate electrode; and a thermally oxidized silicon film on the side of the silicide layer. forming an impurity diffusion layer with a higher concentration than the diffusion layer in a self-aligned manner in a region separated from the end of the gate electrode by the thickness of the silicon oxide film on the side surface of the silicide layer by an ion implantation method using a mask as a mask. Consists of.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1A to 1B are vertical cross-sectional views of main steps in an embodiment of the present invention.

First, as shown in FIG. Regions other than the pattern are removed by etching.Next, impurity ions 19 having a conductivity type opposite to that of the substrate are implanted onto the substrate in a self-aligned manner with respect to the gate electrode pattern to form a low concentration diffusion layer 15.

Next, as shown in FIG. 1(b), a thermal oxidation silicon film 17 is formed on the substrate surface and the gate electrode surface by performing heat treatment. At this time, on the side surface of the polycrystalline silicon layer 13, an oxide film of approximately the same thickness is formed on the inward and outward sides of the side surface, whereas on the surface of the refractory metal silicide layer, most of the oxide film is directed outward. is formed, and the oxidation rate is higher than that of the polycrystalline silicon layer, so the oxide film on the sides of the high-melting point metal silicide layer protrudes further to the outside of the gate electrode than the oxide film on the sides of the polycrystalline silicon layer. become. Next, using the protruding thermal oxidation silicon film on the side surface of the high melting point metal silicide layer as a mask, impurity ions 19 having a conductivity type opposite to that of the substrate are implanted onto the substrate at a higher concentration than the ion implantation amount performed previously. .

As a result, a high concentration diffusion layer 16 is formed having one end in a region separated from the end of the gate electrode by the thickness of the oxide film on the side surface of the high melting point metal silicide layer.

Through the above steps, an LD is formed in which the channel region under the gate electrode and the high concentration diffusion layer 16 are connected via the low concentration diffusion layer 15.
D structure is obtained.

〔Effect of the invention〕

As explained above, in the present invention, when two types of impurity diffusion layers with different concentrations are formed by ion implantation in a self-aligned manner with respect to the gate electrode, an anisotropic etching method is used when forming a low concentration diffusion layer as a mask. In addition, when forming a high concentration diffusion layer, a thermally oxidized silicon film on the surface of the silicide layer obtained by thermally oxidizing a silicide layer of a refractory metal of the gate electrode is used. Thereby, the mutual positional relationship between the gate electrode and the low-concentration and high-concentration diffusion layers can be realized with good reproducibility, and it is possible to manufacture a short channel transistor with good reproducibility. Furthermore, the reproducibility of the mutual conductance of the transistor is improved, which facilitates circuit design.

Furthermore, since the gate length of the polycrystalline silicon layer when the transistor is completed is approximately the same as the gate mask dimension, the degree of integration can be increased when a plurality of transistors are arranged. Furthermore, by using a silicide layer of a high melting point metal for the gate electrode, the gate electrode resistance can be lowered, which has the effect of enabling high-speed operation.

[Brief explanation of drawings]

FIG. 1 (al to middle) is a vertical cross-sectional view of the main steps of an embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 2 (al to (C1
1 is a vertical cross-sectional view of main steps in a conventional method for manufacturing a semiconductor device. 11.21... Semiconductor substrate, 12.22...
... Gate oxide film, 13.23 ... Polycrystalline silicon layer, 14 ... High melting point metal silicide layer, 15.25 ... Low concentration diffusion layer, 16 .26・
... High concentration diffusion layer, 17 ... Thermal oxidation silicon film, 19,29 ... Impurity ion, 28.
...Silicon nitride film. Agent Patent Attorney Susumu Uchihara 1JJJJJiJJ~・ri1 Exploration jmJJ〜・Rikan 1 time 1 adventurej j l k-・ri111111 @ J l-″・2 ?21fl

Claims (1)

[Claims] A step of forming a gate electrode having a two-layer structure consisting of a lower polycrystalline silicon layer and an upper layer of high melting point metal silicide layer on a semiconductor substrate of one conductivity type with a gate insulating film interposed therebetween; forming a low concentration impurity diffusion layer of opposite conductivity type on the substrate in a self-aligned manner by ion implantation using a mask as a mask, and thermally oxidizing the substrate surface and the gate electrode surface to form a silicide layer of the gate electrode. The gate is formed by forming a silicon oxide film thicker than the substrate surface and the side surface of the polycrystalline silicon layer of the gate electrode on the side and top surfaces, and by ion implantation using the thermally oxidized silicon film on the side surface of the silicide layer as a mask. A method for manufacturing a semiconductor device, comprising the step of forming in a self-aligned manner an impurity diffusion layer with a higher concentration than the diffusion layer in a region separated from the electrode end by the thickness of the silicon oxide film on the side surface of the silicide layer. .