JP2594121B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial application field The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a S / D region by self-alignment with respect to a gate electrode.
The present invention relates to a method for manufacturing a semiconductor device capable of accurately controlling the positional relationship between regions and finely controlling an S / D region and improving leakage current characteristics.

In the field of semiconductor integrated circuits, advances in miniaturization technology have been rapidly advancing as the demand for higher density has further increased.

Therefore, an invention has been made in which an S / D region is formed by a self-alignment with respect to a gate by a LOCOS technique using a SiN sidewall spacer.

(B) Prior art FIG. 2 is a cross-sectional view of a conventional semiconductor device during the manufacturing process, in which the S / D region is the most well-known conventional example formed by patterning. (B) is a partial cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment, in which an S / D region is self-aligned with respect to a gate by LOCOS technology using a SiN sidewall spacer. This is the newest conventional example.

In FIG. 2, (101) is a P-type semiconductor substrate, (102)
Is a field SiO ₂ film, (104) is a 200-mm-thick gate Si
O ₂ , (105) is an N ^{+ type} polysilicon gate electrode, (106) is insulating SiO ₂ , (109) is a low concentration S / D region, (110) is a high concentration S / D region, and (111) is This is an SiO ₂ sidewall spacer.

The semiconductor device shown in FIG. 1 shows a MOSFET having an LDD structure having sidewalls, and the position of a field SiO ₂ film and the position of a gate are determined by patterning. As an effect of this, firstly, the size of the S / D region of the LDD structure is different on both sides of the gate due to the misalignment of the mask. Therefore, the series resistance and the contact resistance in the S / D region may be unbalanced on both sides and may be increased on one side. Second
In addition, the size of the S / D region itself is limited in miniaturization. Therefore, it is difficult to reduce the capacitance between the source and the substrate and between the drain and the substrate, and it is also difficult to increase the speed of the semiconductor device.

FIG. 3 is an improvement of the semiconductor device of FIG.
In FIG. 1A, (201) is a P-type semiconductor substrate, (20)
2) is the first field SiO ₂ , (204) is the gate SiO ₂ ,
(205) is a ⁺ N-type polysilicon gate electrode, (206) is an insulating SiO ₂ film, and (207) is a SiN film. The above can be formed by a normal semiconductor integrated circuit manufacturing method. Next, a thick SiN film for sidewalls is deposited, and it is desirable that an SiO ₂ film having a thickness of at least about 100 ° be deposited on the P-type semiconductor substrate in advance to prevent the surface of the P-type semiconductor substrate from being roughened. The gate SiO ₂ film (204) corresponds to this. Thereafter, a SiN film is deposited, and the width is 2500 to 300 by anisotropic etching.
A 0Å SiN sidewall is formed. Next, a gate SiO ₂ for forming a _second field SiO ₂ film (203)
After removing the film, the semiconductor substrate is etched by about 700 ° to facilitate formation of the second field SiO ₂ film (203). After that, the SiN sidewall (208) was masked.
With LOCOS technology, a second field SiO _{2 of} 2000 mm thickness
Form a film.

Next, the SiN film (207), the SiN film sidewall (208), and the gate SiO ₂ film other than under the polysilicon gate electrode are sequentially removed.

Next, as shown in FIG. 2B, after forming a low concentration S / D region, an SiO ₂ sidewall spacer (211) is formed by a well-known method. Thereafter, an N ^{+ type} high concentration SiS / D pad (210) is formed by a selective silicon growth technique.

As described above, the semiconductor device of FIG.
Since 09) is formed by self-alignment, the size can be reduced. Therefore, the stray capacitance can be reduced and the density can be increased.

By However SiN sidewall (208) a second field SiO ₂ film (202) heat treatment during formation by LOCOS technique using a semiconductor and a second field SiO ₂ film (202) under the SiN sidewall (208) Since distortion remains at the boundary with the substrate (201), the low-concentration S / D region (209) formed here shows an increase in leakage current with the P-type semiconductor substrate (201). This is a major drawback, especially for memory devices.

(C) Problems to be Solved by the Invention According to the two types of conventional methods described above, one is that the S / D region is formed by patterning, so that miniaturization and high speed are difficult, and the series resistance and contact resistance are low. It has the disadvantage that it can be large on one side. On the other hand, since the S / D region is formed by self-alignment, miniaturization and high speed can be achieved, but there is a drawback that a large leak current occurs.

Therefore, an object of the present invention is to form a S / D region by self-alignment to achieve miniaturization and high speed, and at the same time, to reduce a leak current so as not to give a distortion to a semiconductor substrate and to improve characteristics. Things.

(D) Means for Solving the Problems The above object is achieved by an LDD formed by a manufacturing method including a step of forming an S / D region with respect to a gate by self-alignment.
In a semiconductor device having a gate structure having a structure and the side wall spacers, a step of forming a first SiO ₂ film serving as a gate SiO ₂ film on a semiconductor substrate of one conductivity type, the first SiO ₂ film Depositing a first polysilicon film serving as a polysilicon gate electrode, introducing an impurity of an opposite conductivity type into the first polysilicon film, and forming a second polysilicon film on the first polysilicon film. Attaching a SiO ₂ film, depositing a first SiN film on the second SiO ₂ film,
The first polysilicon film and the gate SiO ₂ film and the oxidation preventing SiN film becomes the first SiN film becomes SiO ₂ film and polysilicon gate electrode of the second of the insulating SiO ₂ film Forming a first gate multilayer film by sequentially and selectively etching the first SiO ₂ film; and oxidizing the semiconductor substrate on which the first gate multilayer film is formed to form the first gate multilayer film. Depositing a third SiO ₂ film on an exposed surface of the semiconductor substrate other than the region where the multilayer film is formed, and on a peripheral side surface of a polysilicon film which is a gate electrode constituting the first gate multilayer film; A _second layer is formed on the entire surface of the third SiO ₂ film on the semiconductor substrate except for the upper surface of the first gate multilayer film, the peripheral side surfaces thereof, and these portions.
Forming a second polysilicon film, depositing a second polysilicon film on the second SiN film, and anisotropically etching the second polysilicon film to form the first gate multilayer film. Forming a polysilicon sidewall on the peripheral side surface of the semiconductor device via the second SiN film, and selectively removing the second SiN film by etching using the polysilicon sidewall as a mask to prevent a second oxidation. Forming a SiN film for etching, etching and removing the polysilicon sidewall, and selectively oxidizing the surface of the semiconductor substrate using the first and second SiN films for oxidation prevention as a mask to form a field SiO ₂ film. Forming a low concentration S / D region at the same time as forming, etching and removing the first and second antioxidant SiN films, and masking the first gate multilayer film and the field SiO ₂ film. Selectively for the semiconductor substrate Forming a low-concentration opposite conductivity type impurity region to be a low-concentration S / D region; and forming the low-concentration S / D region from the gate SiO ₂ film, the insulating SiO ₂ film, the third SiO ₂ film, and the polysilicon gate electrode. a step of the second gate multilayer film covering and the third SiO ₂ film on the entire surface of the semiconductor substrate is deposited a fourth SiO ₂ film made, said the SiO ₂ film of the fourth is anisotropically etched Forming a sidewall spacer in contact with the peripheral side surface of the second gate multilayer film and at an appropriate interval so as not to overlap the region where the field SiO ₂ film is formed; Forming a high-concentration S / D region by selectively introducing high-concentration opposite-conductivity-type impurities into the semiconductor substrate using the sidewall spacer and the field SiO ₂ film as a mask. This is achieved by a method of manufacturing a semiconductor device.

(E) Function In the present invention, a polysilicon sidewall is formed in place of the SiN sidewall (208) of the conventional semiconductor device shown in FIG. 3 which is an improvement of the conventional example shown in FIG. After forming directly between the field SiO ₂ leaving the film,
By forming an S / D region between the gate and this field SiO ₂ film, the occurrence of distortion of the semiconductor substrate caused by the SiN sidewall formed from the thick SiN film is suppressed, and the S / D region is formed. In addition to making it possible to keep the leakage current when forming the S / D area small, and by forming the S / D area by self-alignment, the S / D area can be formed finely and with the same width, Small variations and high density are possible.

(F) Embodiment Hereinafter, the present invention will be described in detail with reference to an embodiment shown in the drawings.

1 (a) to 1 (i) are process sectional views illustrating a method for manufacturing a semiconductor device according to the present invention.

As shown in FIG. 1 (a), the thickness of a P-type semiconductor substrate (1) (for example, a P-type Si substrate) serving as a gate SiO ₂ film is formed.
A first SiO ₂ film having a thickness of 200 mm and a first polysilicon film having a thickness of 4000 mm serving as a polysilicon gate electrode will be shown. After that, the first polysilicon film is converted to N ⁺ by N such as phosphorus.
Form impurities are introduced.

Next, as shown in FIG. 2B, the thickness of the insulating SiO ₂ film acting as a stress prevention on the polysilicon gate is 2000 μm.
A second SiO ₂ film (4) and a first SiN film (5) with a thickness of 500 ° serving as a first oxidation-preventing SiN film are deposited.

Further, as shown in FIG. 3C, the first SiN film (5), the second SiO ₂ (4) and the first polysilicon film are patterned and selectively formed from the multilayer films thus formed. After etching, the first anti-oxidation SiN film (55) and the insulating SiO ₂ film (5)
4) and a polysilicon gate electrode (53) are formed. Then, the insulating and second
A thickness of 300 for the coverage of the SiN film ((8) in the same figure (d))
The third SiO ₂ film (7) will be shown. At this time, a first SiO ₂ film (FIG. 5A) is formed on the P-type semiconductor substrate (1) except for the SiO ₂ film (52) under the polysilicon gate electrode (53).
(2)), a new SiO ₂ film is deposited, and a third SiO ₂ film (7) is formed.

Next, as shown in FIG.
A second SiN film with a thickness of 500 mm to be a film and a second polysilicon film (9) with a thickness of 6000 mm to be a polysilicon sidewall for forming an S / D region by self-alignment are exhibited. .

Thereafter, as shown in FIG. 4E, a polysilicon sidewall (59) having a width of 0.6 μm is formed by anisotropic etching by RIE.

Thereafter, as shown in FIG. 4F, a second SiN film (FIG. 4E) is formed using the polysilicon sidewall (59) as a mask.
(8)) is wet-etched with hot phosphoric acid. At this time, the polysilicon gate electrode (FIG.
(53)), the second SiN film ((8) in FIG. (D)) is also removed, and the first antioxidant SiN film ((55) in FIG. (C))
Appears.

Thereafter, the first antioxidant SiN film (see (5) in FIG.
5)) and the second oxidation-preventing SiN film (58) are selectively oxidized as a mask to form a field SiO ₂ film (10) around the gate.

Next, as shown in FIG.
The SiN film ((55) and (56) in FIG. 7F) is removed, and the first gate multilayer film and the field SiO ₂ film (10) are used as a mask to perform self-alignment to form an N ⁻ -type low concentration S / D region. (56)
Is formed by ion implantation of an N-type impurity, and then a fourth SiO ₂ film (11) having a thickness of 4000 ° serving as a SiO ₂ film sidewall spacer is formed.

Next, as shown in FIG. 1H, a 0.2 μm wide SiO ₂ side wall spacer (6
After forming 1), an N-type impurity is introduced into a P-type semiconductor substrate ((1) in FIG. 1A) to form a high concentration S / D region (12).

The S / D region thus formed by self-alignment
The width of the polysilicon sidewall ((59) in Figure (e))
It has a size (approximately 0.4μ width) determined by the difference between 0.6μ and the 0.2μ width of the SiO ₂ sidewall spacer (61).

Next, as shown in FIG. (I), N ⁺ form polysilicon S / D
After forming the electrodes, the BPSG film (15) between the layers is deposited, and the S / D wiring opening (16) is opened to form the Al S / D wiring electrode (14).

If necessary, the semiconductor device is completed by covering the cover insulating film.

The manufacturing method described above uses the semiconductor substrate (1) and the S / D
It is needless to say that the conductivity types of the regions (56) and (12) are also effective even if the conductivity types are reversed. Also, the conductivity type of the polysilicon gate electrode and the polysilicon S / D electrode is effective even if the conductivity type is reversed.

(G) Effects of the Invention As described above, according to the present invention, a thin SiN film is patterned using a polysilicon sidewall formed by self-alignment, and a SiO ₂ sidewall smaller in width than the polysilicon is formed. The feature is that the spacer is formed to form an S / D region having a difference between the width of the polysilicon sidewall and the width of the SiO ₂ sidewall spacer, thereby effectively increasing the density and characteristics of the semiconductor device. .

[Brief description of the drawings]

1 (a) to 1 (i) are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to the present invention, FIG. 2 is a cross-sectional view in the process of manufacturing one conventional semiconductor device, and FIG. 7A and 7B are cross-sectional views partially illustrating a method of manufacturing another conventional semiconductor device. In the figure, (1), (101), (201)... P-type semiconductor substrate, (1)
0), (102): Field SiO ₂ film, (202), (203)
... First and second field SiO ₂ films (2), (4),
(7), (11) ... first, second, third and fourth SiO ₂ films,
(3), (9) ... first and second polysilicon films,
(5), (8) ... first and second SiN films, (207) ... SiN
Film, (6) ... low concentration diffusion region, (52), (104), (2
04) Gate SiO ₂ film, (53), (105), (205)
N ^{+ type} polysilicon gate electrode, (54), (106), (20
6) ...... insulating SiO ₂ film, (59), (208) .... polysilicon, SiN sidewall (61), (111), (211) ....
SiO ₂ sidewall spacer, (56), (109), (20
9) Low density S / D area, (12), (110) High density S / D
Region, (55), (58) ... First and second anti-oxidation SiN
Film, (13) ...... N ⁺ form polysilicon S / D electrodes, (14) ...... A
l S / D wiring electrode, (15) BPSG film, (16) S / D wiring opening, (210) High-concentration Si S / D pad.

Claims (1)

(57) [Claims] An LDD (L) formed by a manufacturing method including a step of forming an S / D region with respect to a gate in a self-aligned manner.
In a semiconductor device having an IG (ightly Doped Drain) structure and a gate structure having a sidewall spacer, a first Si film serving as a gate SiO ₂ film is formed on a semiconductor substrate of one conductivity type.
Forming an O ₂ film; and forming a first polysilicon gate electrode on the first SiO ₂ film.
Depositing a polysilicon film of the following, a step of introducing an impurity of the opposite conductivity type into the first polysilicon film, and a step of depositing a _second SiO ₂ film on the first polysilicon film; Depositing a first SiN film on the second SiO ₂ film; and forming the first SiN film to be a first oxidation-preventing SiN film and an insulating Si film.
The _second SiO ₂ film serving as an O ₂ film, the first polysilicon film serving as a polysilicon gate electrode, and the first SiO ₂ film serving as a gate SiO ₂ film are sequentially and selectively etched to form a _second SiO ₂ film. Forming a first gate multilayer film, oxidizing the semiconductor substrate on which the first gate multilayer film is formed, and exposing an exposed surface of the semiconductor substrate other than a region where the first gate multilayer film is formed; A third SiO ₂ film is formed on the peripheral side surface of the polysilicon film which is the gate electrode constituting the first gate multilayer film.
Forming a film; forming a second SiN film on the entire surface of the third SiO ₂ film on the semiconductor substrate except for the upper surface and peripheral side surfaces of the first gate multilayer film and these portions; Depositing a second polysilicon film on the second SiN film; anisotropically etching the second polysilicon film to form a second polysilicon film on a peripheral side surface of the first gate multilayer film; Forming a polysilicon sidewall via the SiN film; and using the polysilicon sidewall as a mask to form the second sidewall.
Selective removal of SiN film by etching to prevent second oxidation
forming an iN film; etching and removing the polysilicon sidewall; and selectively oxidizing the surface of the semiconductor substrate using the first and second oxidation-preventing SiN films as a mask to form a field SiO ₂ film. Simultaneously forming the low-concentration S / D region; etching and removing the first and second oxidation-preventing SiN films; and using the first gate multilayer film and the field SiO ₂ film as a mask. A step of selectively forming a low-concentration opposite-conductivity-type impurity region which becomes a low-concentration S / D region in the semiconductor substrate; the gate SiO ₂ film, the insulating SiO ₂ film, and the third SiO ₂
Covering the second gate multilayer film comprising a film and the polysilicon gate electrode, and depositing a fourth SiO ₂ film in the third SiO ₂ film on the entire surface of the semiconductor substrate, SiO ₂ of the fourth Anisotropically etching the film to form sidewall spacers in contact with the peripheral side surface of the second gate multilayer film and at appropriate intervals so as not to overlap the region where the field SiO ₂ film is formed; Using the second gate multilayer film, the sidewall spacers, and the field SiO ₂ film as a mask, selectively introducing a high-concentration impurity of the opposite conductivity type into the semiconductor substrate to form a high-concentration S / D
Forming a region.