JPS60178666A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable the reduction in input-output capacitance and that in transistor dimension by a method wherein one end of a semiconductor thin film is constructed with due regard to self-alignment and a gate electrode. CONSTITUTION:A field insulation film 2 constructed by boring grooves in an Si substrate 1 and by filling the grooves with Si oxide films is formed. The Si surface of an active region is exposed, and a clean gate oxide film of 10nm thickness is formed; thereafter, a tungsten thin film 4 of about 0.3mum thickness is evaporated and an Si oxide film 13 slightly doped with phosphorus is deposited. An Si oxide film 14 having deposited at the flat part is selective removed by etching the oxide film 14 vertically to the surface of the Si substrate 1. A source diffused layer 6 and a drain diffused layer 7 are formed on activating heat treatment by ion-implanting arsenic via exposed gate insulation film 3. A double metallic wiring 20' is processed according to a desired circuit construction. A surface protection insulation film 10 made up of a phosphorus-doped Si oxide film is deposited, and hole opening to the surface protection insulation film 16 at a desired point of connection is carried out.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor device, and is particularly suitable for miniaturizing the area of a source/drain diffusion layer, and is suitable for connecting an electrode to the diffusion layer. MOS type field effect 1 - related to transistors.

[Background of the invention]

Device dimensions such as gate length, gate oxide film thickness, and weld depth in MO3 type field effect transistors or insulated gate type field effect transistors (hereinafter simply referred to as transistors) are based on known shrinkage periods. The trend toward miniaturization continues. However, the area of the source/drain diffusion layer is not reduced to 111 [IIl] in proportion to dimensions such as the gate length. The above is for conventional structure 1-transistor,
This is because the contact holes on the source/drain diffusion layer are not self-aligned with the ends of the diffusion layer and the end of the gate electrode. That is, in the conventional structure transistor, it is necessary to secure alignment margin for the contacts 1 to holes. 0.5 μm using the latest technology such as electron beam lithography
Even if a contact hole of the same size as the contact hole is formed, an alignment margin of 0.5 μm must be secured around each contact hole. That is, the conventional structure transistor has the drawback that the source/drain width cannot be miniaturized to 1.5 μm or less.

In order to eliminate the above-mentioned drawbacks, a self-aligned contact structure as shown in FIG. 1 has been devised. In FIG. 1, l is a P conductivity type silicon substrate, 2 is a thick filled oxide film for isolation between elements, 3 is an insulating film with a thick gate oxide film, 6 and 7 are source/drain diffusion layers, respectively. Reference numerals 8 and 9 are silicon thin film wirings into which impurities are diffused at a high concentration, 10 is a surface protection insulating film, and 11 and 12 are SONY, SO and drain gold a electrodes, respectively. In conventionally known transistors including the self-aligned contact structure 1 shown in FIG. 1, the gate electrode 4 is not self-aligned with the filled oxide film 2. Therefore, in an ultra-fine transistor with a conventional structure, the source diffusion layer 6 and the drain diffusion layer 7 have a desired width due to misalignment of the gate and electrode.
It has the disadvantage that it is difficult to realize.

That is, variations in the area of the source and drain diffusion layers cause variations in the capacitance of the diffusion layers, resulting in a disadvantage that desired input/output speeds cannot be achieved. Furthermore, the filled oxide film 2 is usually formed by a selective oxidation method called LOCO5, but because the oxide film grows in the lateral direction called a bird's beak, the source oxide film 2 is formed by a distance approximately equal to the thickness of the filled oxide film. The drain region is eroded by the filled oxide film 2. Therefore, in an extreme case, an ultrafine 1-transistor having a conventional structure as shown in FIG. 1 may have a fatal defect in which the source or drain region disappears.

The self-aligned contact structure in Figure 1 is a silicon thin film arrangement A8.
and 9 are directly connected to the source diffusion Nj6 and the drain diffusion N7, but the ultra-fine transistor with the above structure also has other drawbacks. That is, the silicon thin film wirings 8 and 9 as well as the surface protection insulation @10 are doped with impurities at a high concentration. Therefore, impurity diffusion occurs during high-temperature heat treatment such as planarization of the surface protection insulating film 1O, and the junction depth of the source 6 and drain diffusion layer 7, which should be extremely shallow, becomes uneven and deep. have. Furthermore, in the conventionally known self-aligned contact structure as shown in FIG. , and the distance between the goo 1 and the electrode/contact 1 varies. In an ultra-fine transistor having an extremely shallow junction, the source/drain diffusion resistance is high, and the influence of the alignment error appears as a variation in series resistance, that is, a variation in the amount of current.

Furthermore, in the self-aligned contact 1- and 1-transistors shown in FIG. <43 must be achieved. However, in transistors 1 to 1 whose gate length is miniaturized to 1 μm or less, when the area of the source/drain diffusion layer is also miniaturized, the source diffusion layer 6 or the train diffusion layer 7 of the silicon film wirings 8 and 9 is alignment becomes difficult.

That is, in the case of the other end, there is a risk that a part of the source side silicon thin film wiring 8 may cross over the goo 1-electrode 4 and be connected to the drain diffusion layer, resulting in misalignment. Therefore, in the transistor with the conventional structure, the area of the source/drain diffusion layer cannot be ultra-miniaturized despite the miniaturization of the gate length.

That is, in a transistor with a conventional structure, the area of the source/drain diffusion layer cannot be miniaturized to the utmost limit, so it is difficult to reduce the capacitance of the source/drain diffusion layer, and high-speed operation is hindered.

[Purpose of the invention]

The purpose of the present invention is to eliminate the drawbacks of the prior art described above, to configure extremely narrow source/drain diffusion layers having a constant area in a self-aligned manner with respect to the gate electrode, to reduce input/output capacitance, and to reduce the input/output capacitance of transistors. The object of the present invention is to provide a structure that enables miniaturization of dimensions.According to the present invention, the input/output resistance based on alignment error and its fluctuation range are reduced and the self-alignment method does not affect the source/drain junction depth. Contact structures can also be provided.

Further, according to the present invention, the drawbacks of the above-mentioned prior art are solved,
It is also possible to provide a source/drain lead wiring structure that can be connected in a self-aligned manner even to ultra-fine source/drain diffusion layers. or.

According to the present invention, it is possible to ultra-miniaturize the area of the source/drain diffusion layer and provide a transistor structure with improved operating speed due to the reduction in the diffusion layer capacitance.

[Summary of the invention]

In semiconductor device formation, the present invention aligns only the main steps, if necessary, and in other steps, positions specified by the above main steps or from the positions are adjusted depending on other process factors (e.g. This is a semiconductor device using a so-called self-alignment technology in which a desired region is formed at a position specified by a certain distance (oxide film thickness, deposition film thickness, etc.).

That is, when the present invention is applied to a so-called standalone MO8 type semiconductor device, a photomask is used only when forming the gate electrode, and nothing else is used at all, making it possible to form a MOS transistor. However, in actual semiconductor devices, a mask that roughly covers a portion is often used. This is a problem in actual application, a problem when applying the present invention, and is not essential.

In the present invention, in order to form an extremely narrow source/drain diffusion layer in the gate electrode in a self-aligned relationship with the gate electrode with good fliU control, the gate electrode is formed in a self-aligned relationship with the gate electrode.
After forming the protective insulating film, the silicon nitride film and the silicon thin film are selectively left only on the side walls of the gate electrode with the gate protective insulating film interposed therebetween. Using the above silicon thin film as a mask, after completely removing the silicon nitride film other than the side walls of the gate electrode,
The above silicon @[ is also completely removed. The silicon nitride film is left only on the side walls of the gate electrode by the thickness of the silicon thin film, but if the exposed silicon substrate surface is selectively oxidized using the silicon nitride film as a mask and the silicon nitride film is removed, almost all silicon Only a very narrow silicon substrate surface having a width equal to the thickness of the thin film is exposed only to the gate sidewalls in a self-aligned relationship with the gate electrode. Source on the exposed part above.
A drain diffusion layer is formed, and its width is determined by the thickness of the silicon thin film, and the most controllable condition is about 0.1 to 0.3 μm. The width is more than 1/10 narrower than the minimum width of a conventionally known source or train diffusion layer.

Junction capacitance can also be made sufficiently small.

Contact formation to the extremely narrow source/drain diffusion layer described above is based on a self-aligned contact structure.

Here, in order to reduce the influence of fluctuations in the contact position and its area due to alignment errors of the connection wiring, a silicide layer is added to the surface of the source/drain diffusion layer using a high melting point metal or transition metal film. The diffusion layer is formed by self-alignment to reduce the resistance of the diffusion layer. After silicidation, the refractory metal or transition metal film left unreacted on the silicon oxide film is processed to form wiring. In the above wiring formation, the silicide layer is not etched by the etching solution for the metal layer, so a metal wiring is formed which is connected to the source/drain diffusion layer in a self-aligned manner. Since the main silicide layer has a resistance more than one order of magnitude lower than that of a normal diffusion layer, the influence of alignment errors of wiring metal is reduced to a negligible level.

Note that there is also a risk that the silicon substrate may be eroded by the silicide formation and an extremely shallow junction may be destroyed. Therefore, in order to compensate for the erosion and maintain a shallow junction, it is desirable to selectively deposit a silicon thin film only on the exposed silicon substrate before silicidation.

According to the above invention, a transistor structure having an ultra-fine source/drain diffusion layer with a diffusion layer width of 0.3 μm or less can be realized. In the above structure, both ends of the source/drain diffusion layer are configured in a self-aligned manner with the gate electrode, but in ultra-fine transistors where the gate electrode length is 0.5 μm or less, the structure of the source/drain lead electrodes is Another invention of the present application solves the above-mentioned problem in which the conventional technology causes a problem in securing alignment margins, by placing one end of the source/drain lead wiring on the gate electrode. In order to realize the above structure, the present invention focuses on the phenomenon that a silicon compound (silicide) of a high melting point metal such as titanium (Ti) is removed by aqua regia, but a silicon thin film is not removed. That is, in gate electrode processing, a gate electrode protective insulating film,
After simultaneously processing the and Ti thin films using the same mask, the gate electrode is protected by a gate electrode sidewall insulating film. Thereafter, a silicon thin film is deposited on the entire surface, and the exposed refractory metal film and silicon thin film are reacted to form silicide only on the gate electrode. If the above structure is etched with, for example, aqua regia, only the silicide is removed, and a structure in which no silicon thin film exists is obtained in self-alignment with the gate electrode. Although the source/drain lead electrodes are constructed of the silicon thin film described above, the ends of the lead electrodes other than the electrode end 1 may be etched into a desired shape.

If the fourth and fifth structures of the present invention are used, the connection flower between the source/drain extraction electrode and the upper fLm wiring can also be configured in a self-aligned manner with respect to the extraction electrode.

In order to realize the above-mentioned self-consistent flowering, in the present invention, electron v
This method utilizes the phenomenon that the An optical phenomenon depends on the mass of the underlying material, and that the exposure sensitivity of the cyst film is extremely increased when an electric T-ray is applied in a region where a substance with a large mass is present. That is, after the source/drain lead electrodes are formed using a silicon thin film, a film of high melting point metal 1, such as tungsten (W), having a mass sufficiently larger than that of silicon is deposited, and the lead W1 pole is silicided. The unreacted high melting point metal film can be selectively removed using, for example, hydrogen peroxide (H202), an aqueous solution, or the like. After the above configuration, a wiring interlayer insulating film is deposited, a resist for electron beam exposure is applied to form openings for connection between wirings, and electron beam irradiation is performed.

In this case, the electron beam irradiation area is larger than the planned hole opening area.
Even if this process is carried out, the resist film in the opening area is exposed in a self-aligned manner with the source/drain extraction electrodes because the exposure sensitivity is high on the source/drain extraction electrodes, which are silicided with a high-melting point metal having a large mass. Pores can be opened.

If the goo electrode is made of a material with a large mass such as W, there is a possibility that the above method may cause blooms to be formed even on the gate electrode. In order to overcome the above-mentioned drawbacks, in the present invention, the thickness of the wiring interlayer insulating film on the gate electrode where openings are not desired is made thicker than the insulating film thickness of the source/drain lead-out electrode.

In the above implantation, the exposure sensitivity on the gate electrode is not increased due to the difference in insulating film thickness, and the source/drain extraction i! ! Apertures are made in a self-aligned manner only on the very top. The method of selectively forming a thick interlayer insulating film on the gate electrode where flowering is not desired will be explained in detail in Examples, but when the gate electrode length is 0.5
In ultra-fine transistors of micrometers or less, if the gate electrode is formed in a concave shape before the glabellar insulation 1M is deposited, it is extremely easy to deposit thickly only on the goo 1 to electrode. That is, an interlayer insulating film having a thickness sufficient to fill the concave shape may be deposited over the entire surface.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in more detail with reference to Examples.

For convenience of explanation, the explanation will be made using drawings, but please note that important parts are shown enlarged.

Embodiment 1 FIGS. 2 to 6 are diagrams showing an embodiment of a semiconductor device according to the present invention, in which reference numeral 1 denotes a p-conductivity type silicon substrate with a specific resistance of 1 Ω. A trench was bored in a silicon substrate 1 using a known device isolation technique, and a filled insulating film 2 was formed by filling the trench with a silicon oxide film. The filled insulating film 2 may be formed by a conventional selective oxidation method, or may be formed by a U-1 insulation method in which an insulating film is formed on the wall of the trench and a silicon film is embedded inside. After forming the filled insulating film 2, the silicon surface of the active region is exposed and a clean gate oxide film β of 10 nm is formed. Thereafter, a tungsten thin film 4 of approximately 0.3 μm is deposited and a silicon oxide film 13 slightly doped with phosphorus is deposited.

Thereafter, the tungsten thin film 4 and the silicon oxide film 13 were etched at the same time using a photo studio method to form the gate electrode 4 and the gate protection insulating film 13 with the same dimensions. Next, a 0.1 μm silicon oxide film 14 was deposited over the entire surface again by chemical vapor phase reaction. The silicon oxide film 14 was etched in a direction perpendicular to the surface of the silicon substrate 1 by reactive sputter etching, and the silicon oxide film 14 deposited on the flat portions was selectively removed. As a result of the above etching, the deposited silicon oxide film 14 is selectively left only on the side walls of the gate electrode 4, and the gate electrode 4 is covered with the silicon oxide films 13 and 14.

After that, a silicon nitride film 15 with a thickness of about 20 nm and a silicon nitride film 15 with a thickness of 0.3 nm are formed.
A silicon thin film 16 of 5 μm in thickness was sequentially deposited by chemical vapor phase reaction (FIG. 2). Next, the silicon thin film 16 was etched in a direction perpendicular to the surface of the silicon substrate 1 using a reactive sputter etching method, and was deposited on a flat area. The silicon thin film 16 is removed and selectively left only on the sidewalls of the gate electrode 14 with the gate sidewall silicon oxide film 14 interposed therebetween.

In this state, the exposed silicon nitride lB115 was removed using heated phosphoric acid (113PO4) using silicon *ll1i16 as a mask (FIG. 3). Next, the silicon thin film 16 remaining on the side wall of the gate electrode 4 is coated with hydrofluoric acid (II).
When removed with a mixed solution of F) and nitric acid (IINO3), the silicon nitride film 15 selectively left under the silicon thin film 16 is preserved as it is. Next, the exposed gate oxide film 3 is removed using the remaining silicon nitride film 15 as a mask, and then the exposed surface of the silicon substrate 1 is oxidized by a thermal oxidation method to form a silicon oxide film of about 0.15 μm. 2 filled insulation@17 was formed. The second field Rf! 3. Before forming the rim film 17, if desired, the borium 1 (B
) may be implanted into the exposed silicon substrate 1 by ion implantation.
It was formed by penetrating under the m silicon nitride film 15. After forming the second filled insulating film 17, the remaining silicon nitride film 15 was removed using heated phosphoric acid solution again. Subsequently, the dose amount I is applied via the exposed gate isolation i11+II3.
A source diffusion layer 6 and a drain diffusion layer 7 were formed by ion implantation of arsenic (As) of X 10 "cm-2 and subsequent activation heat treatment at a temperature of 900°C. In this example, the thickness was approximately 0.15 μm. However, in the present invention, the source/drain region only needs to be sufficiently close to the channel formed by the gate, and therefore the depth can be varied.Then, the exposed gate oxide is Film 3 was removed to expose the surface of silicon substrate 1 (
Figure 4). In this state, 0.1 μm thick palladium (
After the Pd) film 20 was deposited on the entire surface, a low-temperature heat treatment at 250° C. was performed. Through the above heat treatment, palladium silicide (Pd2) layers 18 and 19 with a thickness of 50 nm were formed on the source diffusion layer 6 and drain diffusion layer 7, respectively. . In the Pd film 20, Pdz 51M18 and 19 are selectively formed only on the source diffusion layer 6 and the doped twin diffusion layer 7 where silicon, which reacts with the silicon oxide film, is exposed (FIG. 5). Next, ammonium cyclide (N114
After removing the unreacted Pd film 20 with an aqueous solution of I) and iodine (I2), the low resistance I of Pd25iyP11B and 19
The heat treatment for No. 6 was carried out at 600°C. After the above resistance-lowering heat treatment, a 20 nm thick titanium (Ti) film and a
．． A Pd film of 2 μm thickness was sequentially deposited, and a double gold J-layer wiring film 2 was formed.
0' was formed. Next, the above double metal wiring 20' was processed according to a desired circuit configuration. Etching was performed by dry etching using I2. In the above etching, P
d2 Si layers 18 and 19 are not eroded at all. Therefore, even if some misalignment occurs during the etching process of the double metal wiring film 20', the double metal wiring film 20' and the Pd
As long as the 7Si layers 18 and 19 are in contact with each other even locally, the resistance of the source/drain diffusion layer is sufficiently low and the fluctuation range is suppressed to a small level. In the above, the entire surface of the source diffusion layer 6 and drain diffusion layer 7 is made of Pd2S with low resistance in a self-aligned manner.
This is because they are covered with i-layers 18 and 19, respectively. Wiring by 5 heavy metal wiring film 20' and PdPd25i 8
After the connection step with 19 and 19, a surface protection insulating film 10 made of a silicon oxide film doped with phosphorus was deposited according to a known method.

Subsequently, the surface protection insulating film 16 was bloomed at the desired connection location. A TiW film was deposited on the entire surface with the photoresist film used for the openings remaining. When the photoresist film was removed in this state, TiW 21 and 22 remained selectively only in the area corresponding to the flowering part. Nao T
Although the iW film is formed by the above method, the double metal wiring film 2
In the evaporation of 0', a TiW film was further deposited on top of 3.
The wiring process may be performed using a heavy metal wiring film and using a desired circuit system. After selectively leaving TiW21 and 22 on the flowering part, aluminum (AQ) was deposited on the entire surface,
A source electrode 11, a drain electrode 15, and wiring were constructed according to a desired circuit configuration using a known wiring process (
Figure 6).

Above Jl! ! In the transistor manufactured through the manufacturing process, the width of both the source diffusion layer 6 and the drain diffusion layer 7 is 0.2 μm, which is 15 times narrower than the minimum width of 3 μm in the conventional structure 1-transistor, and It showed good transistor characteristics. Furthermore, the input/output capacitance of the transistor based on this example was reduced to about half of that of the conventional structure, and the input/output speed was more than doubled. Comparing the area of the active region consisting of the source, drain, and gate for transistors with a gate length of 0.8 μm, the area of the active region consisting of the source, drain, and gate is reduced to about 115 times that of the conventional structure, and the input/output The resistance was low and the transfer conductance was improved. The above is thought to be due to the fact that the distance from the channel end to the source or drain contact hole in the conventional structure is extremely reduced in the structure of this embodiment, and the diffusion resistance is reduced by silicidation.

Embodiment 2 FIGS. 7 and 8 are diagrams showing another embodiment of the present invention. In the first embodiment, after removing the silicon nitride film I5 used for the selective shape of the second filled insulating film 17 and the gate oxide [3] thereunder, dichlorosilane (
A chemical vapor phase reaction between SiHz CQx ) and hydrochloric acid (HCfl) is performed at a temperature of 775° C. to selectively deposit polycrystalline or amorphous silicon thin films 23 and 24 with a thickness of 0.2 μm on the exposed silicon substrate. I let it happen. The formation conditions for the silicon thin film L are 5ill, CQ, 200cc, I((,9
The condition is 60cc and the deposition rate is 3. Onm is 1 minute.

Under the above conditions, unless a silicon nitride film is present on the surface to be deposited, the silicon thin films 23 and 24 are selectively deposited only on the silicon substrate, and even at the boundary with the silicon oxide film 14 on the sidewall, there is a fazzet. The so-called concave shape does not occur. Note that on the second filled insulating film I7, the filled [
The silicon thin films 23 and 24 were deposited approximately 0.1 μm above the Li film 17 (FIG. 7). After selectively depositing the silicon thin films 23 and 24, As ions were implanted into the silicon deposited films 23 and 24.

The above injection amount is 7 x 1013c+n-'. Next, short-time heat treatment was performed at 1100° C. for 30 seconds to activate the implanted ions and form a source diffusion region 6 and a drain diffusion region 7. The diffusion coefficient of impurities in polycrystalline or amorphous silicon thin films 23 and 24 is 10 to 20 times larger than the diffusion coefficient in single crystal silicon.

Therefore, by the above-mentioned short-time heat treatment, the silicon thin film 23
and impurity distribution within 24 is approximately uniform distribution,
Diffusion into the underlying silicon substrate could be controlled to an extremely shallow junction depth of about 35 nm. After forming the source diffusion layer 6 and drain diffusion WJ7 (depth approximately 0.1 μm)
d. The Si layers 18 and 19 were formed in accordance with the first embodiment, and the subsequent steps were also carried out in accordance with the embodiment to manufacture a transistor (FIG. 8).

[Manufacturing above] In the transistor manufactured through the two steps, Pd, 5i) W 18 and 19 are formed by silicon f'
If the film thicknesses of the silicon thin films 23 and 24 are set in advance to compensate for the silicon layer thickness consumed during silicide formation because it is performed on the IT films 23 and 24, junction breakdown due to silicide formation can be prevented. That is, based on this example, a transistor having an extremely shallow junction of 35 nm could be realized without impairing any of the characteristics of the transistor based on the first example. Furthermore, the high breakdown voltage structure of the ultra-fine transistor described in Japanese Patent Application No. 76110/1980 was also able to be reduced to a device area of approximately 115 mm based on this embodiment. The surface impurity concentration of the source/drain diffusion layer of the transistor based on this example was finally configured to be as low as 5×10111 cm′. By employing the above-mentioned low concentration drain diffusion layer, a high breakdown voltage between the source and drain is realized, and in a transistor having a gate length of 0.2 μm, the breakdown voltage between the source and drain is 8V, according to the above-mentioned Japanese Patent Application No. 76119/1983. The same value as the transistor was obtained. The above-mentioned breakdown voltage is two to three times higher than that of the conventional one-transistor structure.

Embodiment 3 FIGS. 9 to 12 are diagrams showing an embodiment of a semiconductor device according to the present invention, in which reference numeral 1 denotes a silicon substrate of p-conductivity type and specific resistance of 1 Ω-cl. After selectively forming a 0.5 μrn thick filled oxide film 2 on a silicon substrate 1 using a known device isolation technique, the silicon surface of the active region is exposed and a 10 nm clean gate oxide film 3 is formed. . Thereafter, a 0.35 μrn W film, a 0.3 μm silicon oxide film slightly doped with phosphorus, and a 0.2 μm Ti film were sequentially deposited.

The three-layer film is etched simultaneously by photolithography, and the gate electrode 4. A Ti film 31 processed in alignment with the gate protective oxide film 13 and the gate electrode 4 was formed. The width of the gate electrode 4 after the above photo-etching, that is, the gate length is 0.5 μn)
Met. Next, a silicon oxide film 5' having a thickness of 0.3 μm was deposited on the entire surface by a chemical vapor reaction using monosilane (SiH4) (Fig. 9). During the phase reaction, phosphine (pH,
) is added in small amounts to add a slight amount of filtering.

The silicon oxide film 5' is etched in a direction perpendicular to the surface of the silicon substrate by reactive sputter etching to remove the silicon oxide film deposited on the flat areas. A gate sidewall oxide film 5) is left behind.

In this state, the silicon thin film 32 of 0.35 μm is coated with SiH4
It was deposited on the entire surface by thermal decomposition. The above thermal decomposition temperature was about 720°C, but in the above deposition]
Above, the deposited silicon thin film reacted with the 'I' i film 31 to form a titanium silicide (TiSi2) film 31' (FIG. io).

In the above silicidation reaction, the thickness of the Ti film 31 is 0.
．． Although the silicon thin film was as thin as 2 μm, all of the silicon thin film deposited on the Ti film 31 reacted and was turned into silicide.

The above is thought to be due to the fact that the ratio of silicon that is eroded during the formation of disilicide (D 1 silicide) is large. After selective formation of the TiSi film 31', T is removed using aqua regia.
The iS i 2 film 31' was removed. In the above etching, the silicon thin film 32 is not removed, so that a structure in which the silicon thin film 32 does not exist on the gate electrode 4 in self-alignment with the end of the gate electrode 4 is obtained. The silicon thin film 32 left in this state is etched into a desired shape, and the source lead electrode 8' (32) and the drain lead electrode 9' (32) are etched into a desired shape.
2) was formed. Thereafter, arsenic (As) was implanted into the source lead-out electrode 8' and the drain lead-out electrode 9' by ion implantation at an acceleration energy of 70 KeV and a dose of 5 x 10 "cIl-". After the above ion implantation, heat treatment for activating the implanted ions and stretching the diffusion layer on the silicon substrate is performed at 1000°C.
' and drain lead-out electrode 9', and a source diffusion layer 6 and a train diffusion layer 7 were formed (FIG. 11).

After that.

A surface protection insulating film 10 was deposited using Kokari's technique, and holes were formed in the surface protection insulating film 10 on the source lead-out electrode 8' and drain lead-out ffi electrode 9' by a known photolithography method. Subsequently, wires including wires 11 and 12 to be connected to the source lead electrode 8' and drain lead electrode 9' were formed according to a desired circuit system (FIG. 12).

In the transistor manufactured through the above manufacturing process, although the source/drain diffusion layer regions 6 and 7 were formed by a known selective oxidation method, each end of the source/drain lead electrodes 8' and 9' Since the portion can be constructed in self-alignment with the end portion of the gate electrode 4, there is no need for alignment margin between the source/drain lead electrode and the source/drain diffusion layer. Therefore, the width of the source/drain diffusion layer could be reduced to 1 .mu.m, which is about 1/3 that of a transistor with a conventional structure. The area of the source/drain diffusion layer has been miniaturized to 1/3 of that of a transistor with a conventional structure, which reduces the input/output capacitance, and the operating speed of the transistor according to the present invention is approximately 20% higher than that of a transistor with a conventional structure. % could be improved.

Embodiment 4 FIGS. 13 to 19 are diagrams showing other embodiments of the present invention. In the first embodiment, the element isolation filled oxide film 2 was formed by a well-known buried oxidation method.

After forming the field oxide 1112, a gate oxide film 3, a W film, and a gate protective oxide film were successively formed according to the first embodiment. The thickness of both the W film and the gate protective oxide film is 0.
．． It was 15 μm. followed by a second WI of 0.15 μm
A second gate protective oxide film with a thickness of 5.0 nm was deposited. No. 1 above. the second W film, and the first. The four-layer superimposed film consisting of the second gate protective oxide film is etched at the same time by photolithography, and the second W film 34 is processed to be self-aligned with the gate electrode t@4. and 1st. A second gate protection oxide film 13.33 was formed. Thereafter, a gate sidewall oxide film 5 was formed in accordance with the first embodiment. Then about 20
A silicon nitride film 15 with a thickness of nm and a silicon thin film 16 with a thickness of 0.35 μm were sequentially deposited by chemical vapor phase reaction (FIG. 13).

Next, when the silicon thin film 16 is etched again in the direction perpendicular to the surface of the silicon substrate 1 by the reactive sputter etching method, the thin silicon RF 1416 deposited on the flat portion is removed, and the gate sidewall oxidation [5] is selectively etched only on the sidewall of the gate sidewall. was left behind. In this state, using the silicon thin film 16 as a mask, heated phosphoric acid (H, Po,') removes the exposed silicon.
The oxide film 15 was removed (FIG. 14).

Next, the silicon thin film 16 selectively left on the sidewalls of the gate sidewall oxide film 5 is treated with hydrofluoric acid (HF) and nitric acid (HNO2).
When it is removed with the mixed solution of s), only the silicon nitride film 15 under the silicon thin film 11116 that was selectively left remains. Subsequently, the remaining silicon nitride 115115
After removing the exposed gate oxide film 3 using the mask as a mask, the exposed surface of the silicon substrate 1 is oxidized by a thermal oxidation method to form a second filled oxide film 17 made of a silicon oxide film with a thickness of about 0.15 μm. Formed. The second filled oxide film is approximately O from the edge of the remaining silicon nitride film 15.
t S μm, and was formed penetrating under the silicon nitride film 15 . After forming the second filled oxide film 17, the remaining silicon oxide film 15 is removed again using a heated phosphoric acid solution.
Subsequently, the exposed gate oxide film 3 was also removed (Fig. 15).
.

Next, after coating the entire surface with electron beam resist solution RE50000 (trade name), the entire surface was irradiated with an electron beam at a dose of -10 μC/r+IT, and when a phenomenon occurred, only the resist film on the second W film 34 was selected. The resist [37] on other areas remained at ρ. Above, resist film 3
7 on the second W film 34.
selectively removed only the gate protection M# 833 (first
Figure 6). The selective residual film effect of the resist film by electron beam irradiation is based on the characteristics shown in FIG. This figure shows the resist remaining film rate after electron beam irradiation and the phenomenon when the silicon substrate is under the oxide film. That is, when electron beam irradiation is performed under the condition of LOttC/d, the resist film is completely removed on Wm, but about 50% of the resist film remains on the silicon substrate. By utilizing this phenomenon, it is possible to selectively remove a resist film on a substance having a large mass such as W.

The above phenomenon is due to the fact that the amount of reflection of the electron beam depends on the mass difference of the underlying material, and in order to prevent the above phenomenon, the distance to the underlying material, that is, the thickness of the oxide film on the W film, must be adjusted compared to others. The second W film 34 may be made thicker, etc.
After selectively exposing the surface, a 0.3 μm silicon substrate film is deposited according to the first embodiment, and a second W film 34 is deposited.
When the tungsten silicide film formed in the section was removed with aqua regia, a structure was obtained in which no silicon film was selectively present only on the first W film 4. In this state, a source lead electrode 8', a drain lead electrode 9', a source diffusion layer 6, and a drain diffusion layer 7 were formed according to the first embodiment. Thereafter, Tt was deposited on the entire surface, and titanium silicide electrodes 35 and 36 were formed on the source lead electrode 8' and the drain lead electrode, respectively, by silicidation heat treatment at 720° C. and selective removal of the unreacted Ti film. Although a mixed aqueous solution of hydrogen peroxide and ammonia water was used to remove the unreacted Ti film, the titanium silicide film was not removed depending on the mixed solution, and the source/drain extraction electrodes configured in self-alignment with the gate electrode 4 were removed. A silicide layer is left only on the top (FIG. 17). After silicide, a surface protection insulating film is formed based on the first embodiment, holes are formed in desired areas, and source/drain leads are formed. A wiring process including connection to electrodes was performed (FIG. 18).

In the transistor manufactured through the above manufacturing process, the source/drain diffusion layer 6. and 7 could be formed extremely finely with a width of 0.2 μm, and the extraction electrode could be formed in a self-aligned manner to the ultra-fine diffusion layer without causing wiring short circuits or poor contact. Furthermore, since the above-mentioned lead-out electrodes are silicided, the series resistance of the source and drain can be reduced to 1/I0 compared to the conventional wiring formed of a silicon thin film. By lowering the wiring resistance and making the source/drain diffusion layers ultra-fine, the operating speed of the transistor based on this example could be increased to about twice that of the conventional structure.

Embodiment 5 FIG. 20 is a diagram showing another embodiment of the present invention. In this example, silicide layers (35, 36
) is used to provide holes in which the electrodes 11 and 12 are provided in a self-aligned manner.

That is, this method takes advantage of the fact that only the photoresist on the silicide layers (35, 36) can be removed.

According to the second embodiment, TiSi layers 35 and 36 were formed in a self-aligned manner on the source lead-out ftt electrode 8' and drain lead-out electrode 9', respectively. The length of the gate electrode 4 was 0.3 μm, and the distance between the source and drain electrodes was also 0.3 μm. Further, the film thickness of the second gate protection insulating film 33 was 0.1511 m. After forming the Ti5iz layer, a surface protection insulating film IO with a thickness of 0.5 μm was deposited on the entire surface, and the thickness of the insulating film on the gate electrode 4 including the gate protection oxide film 13 was about 1 μm. In this state, electron beam resist application and lO
Electron beam irradiation under conditions of μC/J was selectively applied to the source extraction electrode and drain extraction electrode portions.

In the above case, the amount of reflection of the irradiated electron beam was large on 'i'isi, y with a large trade-off number, and there was no residual resist film after the image was developed. However, on the gate electrode 4, the remaining film ratio of the resist film was about 1/2, and no opening was formed, probably because the thickness of the underlying insulating film was about twice that of the TiSi layer. Similarly, the resist remaining film rate on the silicon substrate was about 1/2. Even though the alignment accuracy of the electron beam irradiation area is set coarse, the openings of the connection holes between the source/drain extraction electrodes and the external wiring are self-aligned only with the silicided source/drain extraction electrodes 35 and 36. It was specially formed. In this case, even if the alignment is extremely misaligned, the holes for electrodes 11 and 12 correspond to part A in FIG.
It is not formed anywhere other than the upper part of 6). The portion of the surface protection insulating film 10 that is removed is only the portion of the resist that is irradiated and corresponds to portion A.

After removing the surface protection insulation IFJ in the openings of the resist film, connections were made using aluminum wiring according to the desired circuit configuration (FIG. 20).

In the transistor manufactured through the above manufacturing process, the width of the source/drain diffusions M6 and M7 can be extremely finely configured as 0.2μ1 as in the case of the second embodiment. Super eta and high-speed operation characteristics similar to those of the transistor in the second embodiment could be achieved without causing connection failure or the like. Furthermore, since the wiring connection hole formation to the source/drain lead W1 pole can be configured by self-alignment, there is no alignment margin for the connection hole, so it is called a so-called dog bone, which forms an area wider than the normal wiring width. This made it possible to eliminate the need for the configuration. As a result of the above, it was possible to significantly reduce the wiring area. The significant reduction in the area occupied by wiring according to the present invention is particularly achieved in the logic circuit MO5.
This is particularly effective in LSI.

In this example, it is desirable that the insulating film thickness ratio on the source/drain extraction electrode and on the gate electrode is 1.5 to 2 times or more, and under the above conditions Thus, only the resist film on the source/drain extraction electrodes can be developed and removed by electron beam irradiation in a self-aligned manner.

〔Effect of the invention〕

According to the present invention, the extremely narrow source/drain diffusion layer of 0.2 to 0.3 μm can be formed in a self-aligned manner with the gate electrode, so the area occupied by the source/drain diffusion layer can be reduced by 1715 μm compared to the conventional structure. It can be reduced to: In the above transistor, each junction capacitance of the source and drain is reduced by more than one order of magnitude compared to the conventional structure, so the input/output speed can be increased by more than twice. Furthermore, according to the present invention, interconnections can be connected in a self-aligned manner with narrow silicided source/drain diffusion layers, making it possible to reduce the resistance of the diffusion layer, reduce the series resistance, and reduce the range of variation thereof. . Therefore, there is an effect of improving the transfer conductance. The present invention can also be applied to high-voltage, ultra-fine transistors having a gate length of about 0.2 μm. Therefore, according to the present invention, a 0.2 μm gate length transistor having a source-drain breakdown voltage of 8 V can be constructed with an occupied area of 115 μm or less compared to the conventional structure.

As is clear from the first and second embodiments, the semiconductor device according to the present invention is based on a manufacturing method in which the second filled insulating film is formed after forming the 1-ffl electrode. Therefore, the first filled insulating film 2 is
As shown in the figure, it is not necessary to provide the second filled insulating film 17 and the gate electrode, and it is sufficient to simply provide the second filled insulating film 17 in contact with the second filled insulating film 17 in the direction perpendicular to the drawing, that is, in the channel width direction.

In addition, in the first and second embodiments, the source diffusion layer 6
If the same impurity region as the drain diffusion layer 7 is to be provided in areas other than those shown in FIGS. 4 to 8, a mask for photolithography is selectively placed over the desired area in the state shown in FIG. The silicon thin film 16 may be etched and then manufactured based on the first or second embodiment.

In the first and second embodiments, for convenience of explanation, the silicide layers 18 and 19 are made of Pd and Si, but the silicide layers are made of Ti, Zr, If
, V, Nb, Ta, Cr;, Mo.

It may also be a silicide layer of other high melting point metals such as W, Nj, r't, or transition metals6. Furthermore, the double metal wiring film 20' is not limited to the Ti and Pd polymerized film. The first layer metal film, which requires good adhesion to the silicon oxide film, is made of TiW in addition to Ti.

It may also be a film of other metals such as Mo, Zr, AQ, Ta, Cr, or a mixture thereof. Furthermore, a second film corresponding to the above Pd film is
The metal film in the second layer may be made of Au, Cu, or the various high melting point metals mentioned above, or transition metals. Further, instead of the double metal bending wiring 20', the wiring layer may be formed solely of the metal of the first layer described above.

According to the third to fifth embodiments of the present invention, the lead electrode from the source/drain diffusion layer can be self-aligned with the gate electrode, so that the source/drain diffusion layer can be formed without causing defects such as short circuits between wirings. The layer area can be extremely reduced. Therefore, it has the effect of significantly reducing the diffusion layer capacitance. Furthermore, according to the present invention, since the openings for connection to the source/drain extraction electrodes can be constructed in a self-aligned manner, allowances for positioning the openings can be made unnecessary, and the area occupied by the wiring can be effectively reduced. . Furthermore, according to the present invention, the source
Since the train lead-out electrode is silicided, the effect of reducing the source-drain series resistance can also be utilized, allowing high gain and high-speed operation.

In each of the third to fifth embodiments described above, for convenience of explanation, a gate electrode 1! is provided on the gate electrode 4. WSi2. Alternatively, although the case of TiSi2 has been described, it may be a silicide film of other high melting point metal or transition metal that is removed with an etching solution that does not etch the silicon film. Furthermore, these removal solutions are not limited to aqua regia. Furthermore, the silicidation of the source/drain extraction electrodes described in the fourth and fifth embodiments is not limited to TiSi2, but may also include high melting point metals (or transition metals) with a mass number greater than Si, such as Mo, Ta, W, etc. Zr.

Any silicide such as Hf, V, Cr, Ni, Pt, or Pd may be used.

In each of the above embodiments, for convenience of explanation, a p conductivity type substrate is used!
Although the so-called n-channel transistor in which the source and drain regions are formed by type 1 impurities has been described, the semiconductor device according to the present invention is also applicable to a so-called p-channel transistor which is formed by the n-conductivity type substrate and the source and drain regions to be formed by p-type impurities. can also be applied. Furthermore, the present invention is not limited to the above single transistors, but can also be applied to complementary transistors and semiconductor integrated circuit devices.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a conventional MO5 field effect transistor with self-aligned connection to the source/drain diffusion layer, and FIGS. 2 to 6 are cross-sectional views showing a first embodiment of the present invention. 7 to 8 are cross-sectional views showing a second embodiment of the present invention, FIGS. 9 to 12 are cross-sectional views showing a third embodiment of the present invention, and FIGS. 13 to 18 are cross-sectional views showing a third embodiment of the present invention. FIG. 19 is a cross-sectional view showing the fourth embodiment of the present invention, and is a diagram showing the underlying material dependence as a parameter regarding the electron beam irradiation condition dependence characteristics of a positive electron beam resist. Diagram 20 explaining the self-aligned hole opening technique in the fifth embodiment
The figure is a sectional view showing a fifth embodiment of the present invention. l... Semiconductor substrate, 2... Insulating film for isolation, 3...
Goo 1 - insulating film, 4... gate electrode, 5... isolation B film, 6, 7... source and drain region, 8, 9.8'
, 9'...Extraction electrode, 10...Surface protection insulating film, 11, 12,...ll? j%jwatA,,,mmm
m1 dead-, -X+11-+41v solidified film, 16... silicon layer, 17... silicon oxide film, 18.19...
・Silicide layer, 20.20'... Extraction electrode, 2
1.22...TiW film, 23.24...Silicon layer, 31...T+ film, 31'...Titanium silicide film, 32...Silicon oxide film, 33...Insulating film, 34
...W film 1. i5,36...Titanium silicide film,
■ 1 Country 5132 map YJ 3 Figure ■ 4 Figure 'fJ 5 Figure 'fJt Figure 7 Foil 8 Figure C/ Item fJ10 Kuchi piece 11 Figure VJl, 3 Figure Kaya 14 Figure 'fJ' 5 Figure 'fJt! 7 Figure foil 18 Figure

Claims (1)

[Claims] 1. Adjacent to the gate electrode via an insulating film formed on the side wall of the gate electrode, partially covering the insulating film, and at least connected to the source or drain region in the semiconductor substrate. 1. A semiconductor device in an insulated gate field effect transistor having a semiconductor thin film that is partially in contact with the semiconductor thin film, wherein one end of the semiconductor thin film is configured in a self-aligned relationship with the gate electrode. 2. In the semiconductor device according to claim 1,
The semiconductor thin film is made of a compound with a high melting point metal or a transition metal. A semiconductor device characterized in that the insulating film is thicker than the insulating film covering the compound. 4. It has a gate electrode, an insulating film covering the gate electrode, and a source or drain region, the source or drain region is located at a position defined by an element isolation region and the insulating film, and the element isolation region is , a semiconductor device characterized in that the gate electrode is located at a certain distance from the gate electrode due to at least one factor of the manufacturing process. 5. In an insulated gate field effect transistor in which the source or drain region is separated from the outside by at least first and second insulating film regions, the second insulating film region is separated from the first insulating film region. A semiconductor device characterized in that one side of the second insulating film region that is in contact with at least one side and that does not share a boundary with the first insulating film region is self-aligned with an end of the gate electrode. 6. In the semiconductor device according to claim 4,
A semiconductor thin film, a silicon compound layer of a refractory metal or transition metal, and the refractory metal or transition metal film are formed on at least a portion of the source or drain region, and the refractory metal or transition metal film is comprised of the refractory metal or transition metal film. A semiconductor device characterized in that it is configured to cover at least a portion of a second insulating film. 7. - A method for manufacturing a semiconductor device, comprising: a step of forming a semiconductor element; and a step of forming an isolation region between elements after the main step of determining an element region in the semiconductor element forming step. 8. The semiconductor device v1 manufacturing method according to claim 6, wherein the main step is a step of forming a gate electrode of an MO8 type transistor.