JPS6362271A - Manufacture of mis field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce the element area of an MIS field effect transistor thereby to shorten the switching time of a circuit including the same transistor by providing a contact at source.drain region in a self-alignment. CONSTITUTION:A gate electrode 104 made of polysilicon is formed by a lithography technique, N-type impurity ions are implanted to obtain source.drain region 105. With the sidewall 109 of a silicon oxide film as a mask a silicon nitride film 108 is etched, And the sidewall 109 of the silicon oxide film is then removed by etching. Then, with the remaining silicon nitride film 110 as a mask a polysilicon film 107 is thermally oxidized. Then, when the film 110 and the polysilicon film disposed under the film 110 are sequentially etched, the shape of the silicon oxide film is obtained. A gate electrode is insulated by the silicon oxide film, a contact can be opened in the region since the region on the source.drain adjacent to the silicon oxide film for insulting the gate electrode has no thick silicon oxide film oxidized from the polysilicon.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing an MIS type field effect transistor, and relates to a method for manufacturing an MIS type field effect transistor in which contacts can be provided in the source and drain regions using a self-line. Regarding the method.

[Conventional technology]

Conventionally, contacts to the source and drain of a MIS field effect transistor are formed by patterning using a resist mask separate from the resist mask for forming the gate electrode.

[Problem that the invention seeks to solve]

In the conventional contact forming method described above, the distance between the gate and the contact cannot be reduced below a certain level in order to ensure a margin in alignment accuracy between the resist masks.

Further, the area of the contact portion is limited by lithography technology and cannot be reduced below a certain area. Therefore, conventional contact forming methods have hindered miniaturization of MIS field effect transistors. In addition, source φ
The drain diffusion layer requires an area corresponding to the area of the contact portion. Therefore, the operating speed has been degraded due to the parasitic capacitance associated with this source/drain diffusion layer.

[Means for solving problems]

The method for manufacturing a MIS field effect transistor of the present invention includes:
In order to provide contacts to the source/drain regions of a MIS field effect transistor formed on the entire surface of a silicon substrate of one conductivity type, there are a process of forming a gate electrode, a process of depositing a silicon nitride film, and a process of depositing a thin film. A step of forming a sidewall by reactive ion etching the deposited thin film, a step of etching the silicon nitride film using the sidewall as a mask, and a step of thermally oxidizing the silicon nitride film remaining without being etched as a mask. and a step of removing the silicon nitride film by etching 0 [Example] Next, the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(g) are sectional views taken in the order of steps to explain the first embodiment of the present invention.

The n-channel MIS type field effect transistor according to the first embodiment of the present invention can be manufactured by the following steps.

First, an element isolation region 102 made of an oxide film is provided on a p-type silicon single crystal substrate 101, and a gate oxide film 103 is provided on the element region [FIG. 1(a)]. Next, a gate electrode 104 made of polysilicon is provided using a phosphorography technique, and an n-type impurity is ion-implanted to obtain a source/drain region 105 [FIG. 1(b)]. Next, a silicon oxide film of 400 OA is deposited by vapor phase growth and reactive ion etching is performed, leaving sidewalls 106 of the silicon oxide film on the side surfaces of the gate electrode [FIG. 1(C)]. Next, 100 OA polysilicon film 107.50 OA silicon nitride film 10
8 are deposited in this order, a silicon oxide film of 400 OA is deposited by vapor phase growth, and reactive ion etching is performed.

As a result, as shown in FIG.
Get 9. Next, the silicon nitride film 108 is etched using the side wall 109 of the silicon oxide film as a mask, and then the side wall 109 of the silicon oxide film is removed by etching.
Figure (e)]. Next, the polysilicon film 107 is thermally oxidized using the silicon nitride layer 111110 left in FIG. 1+e) as a mask.

Subsequently, the silicon nitride film 110 and the underlying polysilicon film are sequentially etched to obtain the shape of the silicon oxide film as shown in FIG. In Figure 1), the gate electrode is insulated with a silicon oxide film, and the regions on the source and drain adjacent to the silicon oxide film insulating the gate electrode are covered with a thick silicon oxide film made by oxidizing polysilicon. Since there is no contact hole in this area, a contact can be drilled in this area. Therefore, by providing the aluminum wiring 111, a MIS type field effect transistor can be obtained [FIG. 1(g)].

FIGS. 2(a) to 2(g) are cross-sectional views showing a method for manufacturing an n-channel MIS type field effect transistor according to a second embodiment of the present invention in order of steps.

A structure similar to that shown in FIG. 1C is obtained on a p-type silicon single crystal substrate 201 by the same steps as in the first embodiment.

Next, after oxidizing the polysilicon of the gate electrode at 500A,
A silicon nitride film 207 of 50 OA is deposited, a polysilicon film of 500 Å is deposited, and reactive ion etching is performed to obtain polysilicon side walls 208 [FIG. 2(a)]. Next, ion implantation of VCn type impurities is performed. The advantage of this ion implantation is that it compensates for p-type impurities in the silicon substrate, widens the width of the depletion layer under the source/drain diffusion layer, and reduces parasitic capacitance. Next, the silicon nitride film 207 is etched using the polysilicon sidewall 208 as a mask, and then the polysilicon sidewall 208 is removed by etching. Next, thermal oxidation is performed using the remaining silicon nitride film as a mask.
The shape of the oxide film shown in FIG. 2(C) is obtained. Next, a polysilicon film of 600 OA is deposited, and its surface is oxidized to 500 OA. Windows are etched in this two-layer film of oxide film and polysilicon film at a distance of 1.5 μm from the gate edge as shown in FIG. 2(d).

This etching uses an exposed resist mask.

Next, in order to form a contact opening in a region adjacent to the silicon oxide film on the gate 9411 surface and masked from thermal oxidation by the ζ silicon nitride film, the silicon oxide film is etched to cover the silicon substrate. After that, the polysilicon film 213 was deposited at 7000! It accumulates and becomes a processed shape as shown in FIG. 2(e). Next, the polysilicon film is etched and packed, and the etching is finished when the silicon oxide film 212 is exposed.

Next, n-type impurity ions are implanted to form the polysilicon film with lQ
Dope to the extent of "cIL-" [see Figure 2]. Next, for example, a tungsten film is sputtered to a thickness of 100! It is deposited on the entire surface of the substrate and silicided by heat treatment. Subsequently, unreacted tungsten is removed by etching to obtain a silicide layer 216. Next, the resist mask is patterned and the two-layer film of polysilicon silicide unnecessary for the wiring is removed by etching [FIG. 2(g)]. Through the above steps, the wiring of the polysilicon silicide layer is drawn out from the source/drain through the contacts of the self-line.

〔Effect of the invention〕

As described above, the present invention allows the element area of a MIS field effect transistor to be made smaller than the conventional method by providing contacts to the source and drain regions in a self-aligned manner. This effect arises from the fact that the distance between the gate and the contact does not have to be lenient due to the limitations of phosphorography techniques. Further, the area of the contact is not limited by the phosphorography technique, but is determined by the width of the sidewall in the method of manufacturing the MIS field effect transistor of the present invention. Therefore, the contact area is also reduced, which contributes to reducing the element area of the MIS field effect transistor.

In addition, in the method for manufacturing an MIS field effect transistor of the present invention, by providing contacts in sulfur alignment, the area of the source/drain diffusion layer is reduced, and the associated capacitance is also reduced. There is. Therefore, there is an effect that the switching time of a circuit including an MIa field effect transistor manufactured by the method of the present invention is shortened.

[Brief explanation of drawings]

FIG. 1 tal to (g) is the MIS of the first embodiment of the present invention.
FIGS. 2(a) to 2(g) are cross-sectional views illustrating the manufacturing method of a type field effect transistor in the order of steps, and FIGS.
FIG. 3 is a cross-sectional view showing the manufacturing method of an IS type field effect transistor in order of steps. 101...P-type silicon single crystal substrate, 1o2.
...Element isolation region, 103...Gate oxide film, 1o4...Cate electrode, 105. Old...
Source/drain region, 106... Side wall of silicon oxide film, 107... Polysilicon film, 10
8... Silicon nitride film, 109... Side wall of silicon nitride film, 110... Group silicon nitride film,
111... group aluminum storage, 201... p-type silicon single crystal substrate, 202... element isolation region,
203... Gate oxide film, 204 Old... Gate electrode, 205... N-type impurity diffusion layer, 206
...Side wall of silicon oxide film, 207...
・Silicon nitride film, 208... Polysilicon side wall, 2o9... N-type impurity ion implantation, 21
0...Region where n-type impurities are ion-implanted, 2
11...Group polysilicon [,212...Silicon oxide film, 213...01. Polysilicon film, 21
4. Old... n-type impurity ion implantation, 215...
Polysilicon g, zls, old...silicide layer. Agent: Susumu Uchihara, Patent Attorney 2 ゛Pa No. 7 躬 / Illustrated Z zu No. ZI ¥1

Claims (2)

[Claims] (1) A step of forming a gate electrode, a step of depositing a silicon nitride film, a step of depositing a thin film and performing reactive ion etching on the thin film to form a sidewall, and etching the silicon nitride film using the sidewall as a mask. A method for manufacturing an MIS type field effect transistor, comprising the steps of: performing thermal oxidation using the silicon nitride film remaining unetched as a mask; and removing the silicon nitride film by etching. (2) The method for manufacturing an MIS field effect transistor according to claim 1, wherein the silicon substrate of one conductivity type is a silicon thin film insulated from the substrate.