JPH01114070A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To simplify construction and a manufacturing process by forming a diffusion layer on the channel neighboring part only and composing all the element separation and wiring parts of silicide. CONSTITUTION:After forming a polycrystalline Si gate 1 and an SiO2 side wall 3 on Si on an SiO2 layer 2, an Si exposed part is converted to a silicide up to the SiO2 layer 2 by a self-matching silicide technics, while an n-type diffusion layer 5 and a p-type diffusion layer 6 are formed by drive-in diffusion from silicide 4. By this construction, a complementary MOS transistor having little parasitic resistance and parasitic capacity on a substrate is formed so as to simplify construction and a manufacturing process.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device.
(Silicon on In5ulator) This invention relates to a method suitable for forming a complementary MOS transistor (0MO8) with extremely few parasitic regions on a substrate.

[Conventional technology]

As LSIs become more highly integrated and operate at higher speeds, the deterioration of their characteristics due to the effects of parasitic regions has become impossible to ignore. Examples of this include parasitic capacitance between the element and the substrate and parasitic resistance in the diffusion layer of a MOS transistor, both of which impede speeding up. A typical solution to parasitic capacitance is the so-called SOI technology, in which elements are formed in single-crystal Si on an insulating film. What is SOI technology?

It is also attracting attention as an elemental technology for forming tertiary elements. In addition, for example, IEEEEI is effective in reducing parasitic resistance in the diffusion layer portion.

Transaction on Electron Devices Eday 33. Pages 345 to 353 (1986)
(IEEE Trans Electron De
vices.

ED-33, pp. 345-353 (1986)), a method of forming metal silicide in a self-aligned manner over the entire surface of a diffusion layer is attracting attention.

FIG. 2 is an example of an 0MO8 structure formed by making full use of SOI technology and self-aligned silicide technology.

Si20 on 5iOz2 with gate 1. n-type diffusion layer 5.
p-type diffusion layer6. Silicide film 4. 0MO8 consisting of AQ wiring 8 is formed.

[Problem that the invention seeks to solve]

However, while this method can solve the problem of parasitic capacitance and parasitic resistance, it has the disadvantage that the structure or manufacturing process becomes complicated. The complexity of the structure is also an obstacle in advancing the miniaturization of elements.

The purpose of the present invention is to provide a CMO8 with low parasitic capacitance and parasitic resistance.
The objective is to realize a device with a simple structure and process that can be adapted to miniaturization.

[Means for solving the problem] The main complexity of the structure in the example of FIG.
It is located in the element isolation/wiring section between the O8 element and the p-channel MO3 element. Further, in the source/drain diffusion layer, only the portions near both sides of the channel are actually involved in device operation, and it is essentially sufficient to form only those portions.

Based on the above considerations, the above object, that is, simplification of structure and process, can be achieved by making the diffusion layer only in the vicinity of the channel and making all the element isolation/wiring parts silicide.

The present invention will be explained using FIG.

After forming a polycrystalline Si gate 1 and a 5ins sidewall 3 on the Si on the SiOx layer, the exposed Si is silicided using self-aligned silicide technology up to the SiOz layer 2, and the diffusion layers 5 and 6 are It is formed by drive-in diffusion from silicide 4.

[Effect]

With such a structure, the element isolation/wiring formation process can be replaced with a silicide formation process, which simplifies the process. Furthermore, since the structure is simpler than the structure shown in FIG. 2 and self-alignment technology is used for forming silicide and diffusion layers, it is suitable for miniaturization of elements.

〔Example〕

Hereinafter, the present invention will be explained in detail using Examples.

Example 1 FIG. 3 is a diagram illustrating the manufacturing process of an example of the present invention. A single crystal Si layer with a thickness of 200 nm is formed on 5iOz2 by a well-known in-phase epitaxial growth method, and an n-type well 10. A p-type well 9 gate oxide film 11 polycrystalline Si gate 1°5iOz gate sidewalls 3 were formed (FIG. 3(a)).

The gate length is 0.8 μm. Next, Ti12 with a thickness of 200 nm is deposited by sputtering (Fig. 3(b)).
After forming titanium silicide 13 by heat treatment at 700°C for 30 minutes in a N2 atmosphere, unreacted Ti was removed by wet etching, and further heat treatment was performed at 800°C for 30 seconds in an Ar atmosphere (third Figure (C))
. Under these conditions, titanium silicide was formed in contact with 5i023.

Next, the area where the n-type well 10 has been formed is covered with photoresist 1.
4 and then exposed to As at 150 k e V.

After ion implantation under the conditions of 5 x 10 "cm-" and removal of the resist, an n-type diffusion layer 5 was formed by drive-in diffusion by heat treatment at 1000°C for 20 seconds (Fig. 3(d)). . Furthermore, in the same manner, without masking the p-type well formation region, B was applied at 25keV2X10.
After ion implantation under the conditions of 8cffI-2, too
A p-type diffusion layer 6 was formed by heat treatment at 0° C. for 20 seconds (FIG. 3(e)).

According to this embodiment, in order to reduce parasitic resistance, the value of transfer conductance g1 is 1.2 x 10-4, which is 1.6 times that of 0MO9 formed on an SOI substrate by the conventional technology.
'IJ''/ttm was obtained.

Example 2 A 64 kilobit static RAM based on 0MO8 was fabricated using tungsten silicide as the silicide and using the same manufacturing process as in Example 1. The design rule is 1.3 μm. According to this embodiment, compared to the conventional CMO8 configuration that does not use an SOT substrate,
The access time was reduced by about 0.6 times to 20 ns.

〔Effect of the invention〕

According to the present invention, C with extremely low parasitic resistance and parasitic capacitance
Since uO2 can be formed, the speed of the device can be increased.

In addition, since the structure is simple and the manufacturing process uses self-alignment technology, it is suitable for miniaturization of elements.

[Brief explanation of the drawing]

FIG. 1 is a sectional view for explaining the present invention in detail, FIG. 2 is a sectional view for explaining the prior art, and FIG. 3 is a sectional view for explaining the steps of an embodiment of the present invention. 1... Gate electrode, 2... Insulating film (SiOz), 4
...metal silicide, 5...n-type diffusion layer, 6...
P-type diffusion layer.

Claims (1)

[Claims] 1. SOI (Silicon on Insulator: Sil)
icon on Insulator) In the manufacturing process of forming complementary MOS transistors on a substrate, SO
A step of forming a gate electrode on the I substrate, a step of forming metal silicide so that the entire area of exposed Si except the gate electrode is in contact with an insulating film layer inside the SOI substrate, and a step of implanting ions into the metal silicide. and forming a diffusion layer by drive-in diffusion from the metal silicide.