JPH01765A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to the structure of a MIS field effect transistor.

[Conventional technology]

Conventional MI S type field effect transistor (2 lower, MI
It is abbreviated as SFET. ) adopts a structure in which a polycrystalline silicon layer is used as a gate electrode in order to achieve high speed, high density +A, high reliability, etc.

FIG. 2 is an explanatory cross-sectional view showing the structure of this type of MO3 field effect transistor (hereinafter abbreviated as MOSFET).

For example, in the n-channel MO3FET shown in FIG. 2, this transistor is formed on the main surface of a P-type silicon (Si) substrate 1. A field oxide film 2 for element isolation is selectively formed in the P-type Si substrate 1, and a gate electrode 9 made of a polycrystalline silicon layer is provided in the element forming region via a gate electrode 6. Further, an n+ type source region 3 and an n+ type drain region 4 are formed in a self-aligned manner using this gate electrode (temporary 9) as a mask for ion implantation.In addition, in FIG.
Electricity is drawn from the tray/region 4 and the gate electrode 9 using aluminum (AI), but this is omitted here.

[Problem that the invention attempts to solve]

According to the f+W structure of the conventional h+ OS FET mentioned above, there are a few disadvantages in the device characteristics mainly caused by the electrode hM a as listed below.

(1) In a conventional MOS FET, the capacitance between the drain and the substrate is large, so the operating speed of the transistor is slow.

(2) In order to reduce the capacitance between the drain and the substrate, the area of the drain region can be reduced. However, according to the conventional structure as shown in FIG.
'The formation of the source drain/contact hole and source self-train electrode is limited by the alignment of the phosphorography process, so it is necessary to have alignment margin for each pattern. Therefore, there is a limit to reducing the area of the drain region, and there is a limit to increasing the speed and density of the above-mentioned device.

(3) With the miniaturization of devices, the contact between the diffusion layer and the arranged electrode in the contact hole area is becoming more stable due to the narrowing of the junction of the V: diffusion layer in the source and drain regions and the reduction in the size of the contact hole. This makes it difficult to form.

(4) Since polycrystalline silicon 7Er is used as the gate electrode, the wiring delay caused by this becomes an obstacle to increasing the speed of the device.

Therefore, the present invention aims to solve these problems.
The purpose of this is to significantly reduce the parasitic capacitance by reducing the area of the parasitic region, and to create a structure that allows the use of a fully bent gate electrode, thereby improving the performance and high performance of MOSFETs. The object of the present invention is to realize an element with excellent reliability by achieving high density and by making the tray/region have a gently sloped impurity concentration distribution.

[Means for solving problems]

The semiconductor device of the present invention is a semiconductor HH having an MIS structure.
A polycrystalline silicon layer provided from a source or drain formation region to an element isolation region, and a source region and a drain region formed in a self-aligned manner by diffusion from the polycrystalline silicon layer and having a gently sloped impurity concentration distribution. and a channel region defined in a self-aligned manner by the polycrystalline silicon decoy, and a gate electrode formed over the channel region through a gate film and an insulating film provided on the polycrystalline silicon layer. It is characterized by having

[Effect]

In the present invention, source and drain regions are formed in a self-aligned manner by impurity diffusion from polycrystalline silicon.
Furthermore, since the source tray/electrode is drawn out using this polycrystalline silicon layer, the area of the parasitic region can be reduced without being subject to the limitations of phosphorography technology, and the shadow of the parasitic region on the device can be largely eliminated. . Furthermore, since the diffusion layer is connected to the wiring layer via the polycrystalline silicon layer, stable electrical contact is achieved in the contact hole portion.

Furthermore, since it is possible to lower the temperature of heat treatment after forming the gate electrode, a metal layer is used as the gate electrode material to reduce wiring delay due to the gate electrode material. In addition, since the drain region has a gently sloped impurity concentration distribution, the MISFE
Electric field concentration near the drain region during T operation is alleviated, and threshold voltage shifts due to hot electrons and the like are reduced.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings, together with a manufacturing method thereof.

FIG. 1 is an explanatory cross-sectional view of a semiconductor device showing one embodiment of the present invention.

In FIG. 1, the MOSFET is an n-channel type,
It is formed on the main surface of the P-type Si substrate 1. ■) Type S
A field oxide film 2 is selectively formed in the i-substrate l, and this field oxide film l12 is further formed from above the element formation region.
2, an n+ type polycrystalline silicon layer 5 is provided, and by impurity diffusion from the n+ type polycrystalline silicon layer 5, a source region (n+ source region 3 and n- Consisting of north area 3a)
and drain regions (consisting of n+ drain region 4 and n- drain region 4a) are formed, and electrodes of these source and drain regions are drawn out by n+ type polycrystalline silicon layer 5. Further, a channel region is defined by this n+ type polycrystalline silicon layer 5 in a self-aligned manner, and any one of the polycrystalline silicon layer, high melting point metal, metal, and metal silicide is formed on this channel region via a gate film 6. A gate electrode 8 selected from these is formed. In addition, in the figure, 7 is an oxide (SiOt) film, and n
The drawing out of the electrode from the +-type polycrystalline silicon layer 5 is omitted.

According to the structure of the above embodiment, the n+ type multi-component silicon layer 5
Source/drain/region 3.3a by impurity diffusion from
, 4.4a are formed in a self-aligned manner, and the source and drain electrodes are drawn out using this n''ffi polycrystalline silicon 56. As a result, parasitic elements such as the train-to-substrate dissolution volume can be significantly reduced, leading to higher performance and higher integration of the device.

Furthermore, diffusion layers (source and drain regions 3.3a, 4.
Since the n+ type polycrystalline silicon layer 5 is inserted between the wiring metal layer 4a and the wiring metal layer, the diffusion layer and the wiring metal layer do not come into direct contact with each other, and stable electrical contact is possible at the contact hole portion.

Additionally, according to this structure, it is possible to lower the temperature of heat treatment after forming the gate electrode, and a metal layer such as aluminum can be used as the gate electrode, reducing wiring delays caused by the gate electrode material and increasing the speed of the device. It has a calming effect.

Moreover, since the drain region consists of an n+ type drain region 4 and an n- drain region and has a mild graded impurity concentration, MO3FET! It alleviates the electric field concentration near the drain region during operation, and
The shift of the threshold voltage of ET and the degradation of gm are reduced, and the reliability of the device is greatly improved.

Next, a method for manufacturing the semiconductor device of the above embodiment is shown in FIG.
l to tdl will be explained in order.

(1) On the P-type St substrate 1 on which the field oxide film 2 is formed, polycrystalline silicon: 17 layers 0.2
After depositing ~0.6 μm, hi f, (A s )/(P
) to form an n medium polycrystalline silicon layer 5. Furthermore, a 5IOt film 7 is deposited by CVD.

(See FIG. 3, fat) (2) Next, the SrOx film 7 and the n+ type polycrystalline silicon layer 5 in the region excluding the channel region of the MOSFET and the source/drain electrode extension regions are selectively etched. (See Figure 3 (bl)
(3) Next, the gate oxide film 6 is formed by oxidizing the Si substrate at 800 to 1000°C. At this time, n+ type polycrystalline silicon r! The side walls of 15 are oxidized, and SiO and film 7a are formed at the same time.

At the same time, arsenic and phosphorus are doubly diffused from the n+ type polycrystalline silicon layer 5, and by utilizing the difference in their diffusion rates in Si, an n-type source region and an n-type drain are formed with a gently sloped impurity concentration distribution. A region is formed. Note that the n-type source region consists of the n+ type tunnel region 3 and the n- type source region 3a, and the n-type drain region consists of the n+ type tunnel region 4 and the n+ type source region 3a.
e consisting of type dray/area 4a (see Figure 3 tcl)
(4) Subsequently, after sputtering a metal such as aluminum, the gate electrode 8 is patterned by phosphorography. (Figure 3(d)) See Jl! ? ) Hereinafter, by following the conventional method for manufacturing a semiconductor device, a semiconductor device having the above-mentioned effects can be formed in a relatively small number of steps.

In the above embodiments, a polycide layer or a silicide layer may be used instead of the polycrystalline silicon layer. Furthermore, instead of aluminum, polycrystalline silicon, tungsten, molybdenum, titanium, platinum, cobalt, or silicide compounds thereof may be used as the gate electrode. In addition, a phosphorus glass (PSG) film, a boron phosphorus glass (BPSG) film, a plasma nitride (P-3iN) film, etc. may be used instead of the SiOx film. Also,
The polycrystalline silicon layer may be doped with impurities of the same type having different diffusion rates of 2 gi or more.

By the way, in the above embodiment, the source/drain regions with a gently sloped impurity concentration distribution were formed by double diffusion of impurities from the polycrystalline silicon layer, or alternatively, a type of source/drain region from the polycrystalline silicon layer was formed. By combining two or more heat treatments to diffuse impurities, the source/drain 7 f! An IT area may also be formed.

In the above embodiments, the case of an n-channel MO5FET was explained, but instead of the n-type impurity, boron (
B) or by using a P-type impurity such as BF, a P-channel type M having the same effect as the above semiconductor device.
An O3FET is obtained.

Furthermore, it goes without saying that the present invention is not limited to the above-described embodiments, and that various changes can be made without departing from the spirit of the invention.

〔Effect of the invention〕

As described above, according to the semiconductor device of the present invention, the source/drain regions are formed in a self-aligned manner by impurity diffusion from the polycrystalline silicon, and the source/drain regions are formed in the polycrystalline silicon by the impurity diffusion from the polycrystalline silicon. In order to bring out this, the device size can be reduced without being limited by phosphorography technology.

As a result, the shadow U of the parasitic region of the MISFET can be significantly reduced, and higher performance and higher integration of the device can be achieved.

Further, since the diffusion layer and the wiring metal layer do not come into direct contact with each other, electrically stable contact can be obtained at the contact hole portion, and a highly reliable device can be obtained.

Furthermore, since it is possible to reduce the cost of the heat treatment step after forming the gate electrode, a metal layer can be used as the gate electrode, speed delays caused by the gate electrode material can be reduced, and the device can be made faster.

Furthermore, since the drain/region has a gently sloped impurity concentration distribution, the electric field concentration near the drain region during MISFET operation is alleviated, and problems such as hot electrons are avoided, making it possible to realize a device with excellent reliability. to have a baby.

[Brief explanation of the drawing]

': Figure J1 is a cross-sectional explanatory diagram of a semiconductor device showing one embodiment of the present invention, FIG. 2 is a cross-sectional explanatory diagram of a conventional semiconductor device, and FIG.
Figures (a) to (di) are cross-sectional explanatory views showing a method of manufacturing the semiconductor device shown in Figure 1.l...P-type semiconductor substrate 2...Field oxide film 3... ...N+ type source region 3a...N- type source region 4...N+ type drain region (JT btc4a...
...N- type drain region 5...N+ type packed crystal 7977 layer 6...
Gate 7, 7 a-...S i Ox film 8.9...Gate electrode and above Applicant Seiko Epson Co., Ltd. Representative Patent attorney Tsutomu Mogami and 1 other person, Wahai, - ，
i'-1 -tonyu 1 Figure 2

Claims (1)

[Claims] In a semiconductor device having an MIS structure, a polycrystalline silicon layer provided from a source or drain formation region to an element isolation region and a polycrystalline silicon layer formed in a self-aligned manner by diffusion from the polycrystalline silicon layer, a source region and a drain region having a gently sloped impurity concentration distribution; a channel region defined in a self-aligned manner by the polycrystalline silicon layer; A semiconductor device comprising: a gate electrode formed over an insulating film.