JPH0555246A - Formation of insulated-gate semiconductor device - Google Patents

Abstract

PURPOSE:To propose an entirely new method capable of applying a gate electrode in high aspect ratio exceeding 1 posing no problems at all as for the formation method of an LDD structure. CONSTITUTION:In order to form an LDD region in a MOSFET, firstly a low concentration region 13 (the first impurity region) is formed by self-alignment step using a prospective gate electrode part 11 as a mask and then said part 11 is oxidized by thermal oxidizing step, etc., to form a gate electrode 15 inside thereof and then a high concentration impurity region 16 (the second impurity region) is formed.

Description

Detailed Description of the Invention

[0001]

The present invention is excellent in high speed and
The present invention relates to a method for manufacturing an insulating gate field effect semiconductor element (semiconductor device) capable of high integration. The semiconductor device according to the present invention includes a microprocessor, a microcontroller,
It is used for a microcomputer or a semiconductor memory.

[0002]

2. Description of the Related Art Many researches and developments have been made on miniaturization and high integration of semiconductor elements. In particular, MOSF
The progress of miniaturization technology of an insulated gate field effect type semiconductor device called ET is remarkable. MOS is a metal
-Oxide-This is an acronym for Semiconductor. The metal is used in a broad sense including a semiconductor material having a sufficiently large electric conductivity and an alloy of a semiconductor and a metal, even if it is not a pure metal. Further, instead of an oxide between a metal and a semiconductor, not only a pure oxide but also an insulating material having a sufficiently large resistance such as a nitride may be used. In such a case, strictly, Is MOS
Although the term is not correct, hereinafter, the field effect element having such a structure including a nitride and other insulators will be referred to as a MOSFET.

The miniaturization of the MOSFET is performed by reducing the width of the gate electrode. A smaller width of the gate electrode means a shorter length of the channel region thereunder, that is, a shorter channel length, which means that the time required for carriers to pass through the channel length is shortened. As a result, high integration as well as high speed are brought about.

However, this causes another problem (short channel effect). The most important of these is the hot electron problem. Like traditional
In a structure in which a channel region doped with impurities of opposite polarities is sandwiched between impurity regions called a source and a drain, which have a sufficiently high impurity concentration, the voltage applied to the source and drain may be increased as the channel region is narrowed. The electric field near the boundary between the channel region and the impurity region becomes large. As a result, the operation of the MOSFET becomes extremely unstable.

A new MOSFET structure proposed for the purpose of solving such a problem is an LDD (Lightly-Do
ped-Drain). This is typically shown in FIG.
It is shown in (D). In FIG. 2D, a region 27 having a low impurity concentration which is provided shallower than the region 26 having a high impurity concentration is called an LDD. By providing such a region, it is possible to reduce the electric field near the boundary between the channel region and the impurity region and stabilize the operation of the device.

The LDD is usually formed as shown in FIG. FIG. 2 shows an example of NMOS, but the same is formed even if it is PMOS. First, an oxide film and a conductive film are formed on a p-type semiconductor substrate, and these are etched to form a gate insulating film 22 and a gate electrode 21 as shown in FIG. Then, using this gate electrode as a mask, the impurity region 23 having a relatively low impurity concentration (represented by n ^{− in the} symbol) is formed in a self-aligned manner, for example, by an ion implantation method or the like.

Next, an insulating film 24 such as PSG is formed on this. Then, the insulating film 24 is removed by an anisotropic etching method (also referred to as a directional etching method) such as bias plasma etching, but as a result of the anisotropic etching, the PSG is not etched on the side surface of the gate electrode. Then, the shape remains as shown by 25 in FIG. This residue is called a spacer. Then, using the spacer 25 as a mask, the impurity concentration is high in self-alignment (denoted by n ^{+ in the} symbol).
Impurity region 26 is formed. The n ⁺ type impurity region is used as the source and drain of the FET.

It has been shown that by adopting such an LDD structure, it is possible to narrow the channel length, which was said to be 0.5 μm in the conventional method, to 0.1 μm.

[0009]

However, this does not solve all the problems of shortening the channel. Another problem is the resistance of the gate electrode due to the reduced gate width. Even if the operating speed is improved by shortening the channel, if the resistance of the gate electrode is large, the propagation speed is reduced by canceling out the resistance. To reduce the resistance of the gate electrode, for example, use metal silicide having a low resistivity instead of polycrystalline silicon having a high impurity concentration, which is conventionally used, or use a low-resistance wiring such as aluminum in parallel with the gate electrode. Although it has been studied and adopted to run, it is expected to reach its limit when the width of the gate electrode is 0.3 μm or less.

As another solution in that case, it is considered to increase the height-width ratio (aspect ratio) of the gate electrode. By increasing the aspect ratio of the gate electrode, it becomes possible to increase the cross-sectional area of the gate electrode and reduce the resistance. However, conventional LDD
However, the aspect ratio could not be increased without limitation due to manufacturing problems.

This is because the width of the spacer formed by anisotropic etching depends on the height of the gate electrode.
Normally, the width of the spacer was 20% or more of the height of the gate electrode. Therefore, when the width L of the LDD region 27 in FIG. 2 is 0.1 μm, the height h of the gate electrode is 0.
It had to be less than 5 μm. If the gate electrode has a height higher than that, L will be 0.1 μm or more. This is an increase in resistance between the source and drain, which is not desirable.

Now, the height h of the gate electrode is 0.5 μm, the width W of the gate electrode is 1.0 μm, and the width L of the LDD is 0.1 μm.
Let's say m. By reducing the scale of this element,
If W is set to 0.5 μm, h must be 1.0 μm in order to maintain the resistance of the gate electrode. However, because of that, L becomes 0.2 μm. That is, the resistance of the gate electrode does not change, but ON
State (state in which the resistance of the channel region has become sufficiently smaller than the resistance of the n ⁻ region when a voltage is applied to the gate electrode)
The resistance between the source and drain is doubled. On the other hand, since the channel length is halved, the device can be expected to respond at twice the speed, but this is canceled because the resistance between the source and drain is doubled.
In the end, only high integration of the device has been achieved, and the speed is still conventional. On the other hand, in order to keep L at the same level as in the conventional case, h must be set to 0.5 μm. If this is done, the resistance of the gate electrode will be doubled, and in the end, high speed cannot be obtained.

In a typical example, the width of the spacer is 50% to 100% of the height of the gate electrode, which is considerably more difficult than the one shown above. Therefore, in the conventional LDD manufacturing method, the aspect ratio of the gate electrode was 1 or less, and most was 0.2 or less. In addition, the width of the spacer varies widely, and the characteristics among the transistors are often different. As described above, the conventional LDD manufacturing method has provided stability in a short channel and high integration and high speed associated therewith, but a problem in its manufacture hinders higher speed and higher integration. That is a contradiction.

The present invention proposes, as a method for producing an LDD structure, a completely new method which can be carried out without problems even with a gate electrode having a high aspect ratio of 1 or more. As described above, due to the miniaturization, increasing the aspect ratio of wiring is an unavoidable problem.

[0015]

A typical example of the present invention is shown in FIG. This is the case of the NMOS, but the same can be implemented with the PMOS. First, an insulating film such as an oxide film and a conductive film are formed on a p-type semiconductor substrate, and the insulating film and the conductive film should be etched to form a gate electrode as shown in FIG. It becomes the portion 11 and the gate insulating film 12. Then, using the portion to be the gate electrode as a mask, in a self-aligned manner,
For example, by ion implantation or the like, 1 × 10 ^{17 to} 5
A first impurity region 13 having a low impurity concentration of about × 10 ¹⁸ cm ⁻³ (denoted by n ^{− in the} symbol) is formed.

Then, the surface of the portion to be the gate electrode is oxidized by the thermal oxidation method. Therefore, the portion to be the gate electrode needs to be made of a material that is oxidized. By this step, the surface of the portion that will become the gate electrode recedes. Finally, the gate electrode 15 remains inside the oxide layer 14. (FIG. 1 (B)) If the material 11 of the portion to be the gate electrode is polycrystalline silicon and the oxide film 12 is silicon oxide, the silicon substrate is also oxidized, but if the gate insulating film is used. (Silicon oxide)
Is not etched at the same time as the formation of the gate electrode and the silicon substrate is covered with the silicon oxide film,
The rate is sufficiently low compared to the rate of oxidation of the part that should become the gate.

That is, the oxidation rate decreases as the thickness of the oxide film initially present increases. It is generally known that the following equation holds for thermal oxidation of silicon. x ² −x ₀ ² + Ax −Ax ₀ = Bt (1)

Here, A and B are positive constants depending on silicon and silicon oxide, and depend on the temperature, the plane orientation of silicon, the diffusion rate of oxygen atoms and water in silicon, and the like. In addition, x ₀ is the film thickness of silicon oxide that was initially present, and x is the thickness of silicon oxide after a lapse of time t. (1)
By transforming the formula, the following formula is obtained. _{Δx (x + x 0 + A} ) = Bt ( where _{Δx = x-x 0) (} 2)

For example, in the state where almost no silicon oxide is formed on the surface, x ₀ = 0, so Δx ₁ = Bt / (x + A) (3), while a considerably thick film is formed at the beginning. And
In the case of x to x ₀ , Δx ₂ = Bt / (2x + A) (4). From (3) and (4), it can be seen that the oxidation rate (represented by Δx / t) is higher when the silicon oxide film is not initially present on the surface under the same conditions. Although this calculation is not detailed, the speed difference is Δx ₁ / Δx ₂ = (2x + A) / (x + A) <2.

In fact, in the thermal oxidation of the single crystal silicon (100) surface in dry oxygen at 1 atm, when the surface is oxidized at 1000 ° C. for 100 minutes and the silicon oxide is not formed on the surface before the thermal oxidation. Silicon oxide is formed to 100 nm, whereas when 100 nm of silicon oxide is formed on the surface before thermal oxidation, the thickness of silicon oxide is only 150 nm, and even if oxidation is performed for the same time. Regardless, in the former, 100 nm of silicon oxide was formed, but in the latter, only 50 nm of silicon oxide was newly formed.

Similarly, even if thermal oxidation is performed at 900 ° C. for 100 minutes, if silicon oxide is not formed before thermal oxidation, 50 nm of silicon oxide is formed, but before thermal oxidation is performed. When the silicon oxide having a thickness of 50 nm is formed, the thickness of the silicon oxide which increases is only 20 nm, and even when the heat treatment is performed for 200 minutes, the silicon oxide is not present before the thermal oxidation. As a result, the silicon oxide having a thickness of 70 nm is formed, whereas when the silicon oxide having a thickness of 90 nm is formed before the thermal oxidation, the silicon oxide increases by only 30 nm.

Furthermore, the rate of thermal oxidation greatly differs depending on the plane orientation, and the rate of the (100) plane of silicon is (11
1) The oxidation rate is lower than other surfaces such as the surface. Further, since the surface orientations of polycrystalline silicon are different, the polycrystalline silicon is naturally oxidized at a rate higher than the (100) plane and about twice as fast.

For the above reasons, as shown in FIG. 1, the thickness of the silicon oxide formed in the portion to be the gate electrode is the same as that of the silicon oxide newly formed on the silicon substrate through the gate insulating film. It is much larger than the thickness, and as shown in the figure, the unevenness on the surface of the silicon substrate is sufficiently small. For example, when 100 nm is oxidized from the original surface of the portion 11 (polycrystalline silicon) to be the gate electrode, the silicon substrate below the oxide film 12 (silicon oxide) is newly oxidized by 25 nm. .. The unevenness of this degree does not seriously affect the characteristics of the semiconductor element.

In the process of this thermal oxidation, the impurity region 13 previously formed is also diffused and expanded by heat. In the present invention, since the element needs to operate efficiently as a field effect transistor, the tip of the impurity region thus expanded needs to be geometrically aligned with both ends of the gate electrode.

The gate electrode 15 thus formed and the oxide layer 14 around the gate electrode 15 are used as a mask to self-align with a large impurity concentration of 1 × 10 ^{20 to} 5 × 10 ²¹ cm ^-3 (symbol). in represented as n ⁺⁾ second impurity region 16 is formed. In this way, the conventional L
It is possible to obtain an LDD having the same shape as in the case of the DD manufacturing method. What should be noted in this step is that the width L of the LDD is not restricted by the height of the gate electrode, so that the aspect ratio of the gate electrode can be increased, as is clear from the figure. is there.

Further, according to the present invention, the width L of the LDD can be controlled extremely finely. For example, L from 10 nm to 0.1
It can be arbitrarily changed up to μm. Further, the channel length W at this time can be 0.5 μm or less. In the conventional method, it is extremely difficult to set the width of the LDD to 100 nm or less, and an error of about 20% is natural. However, if the present invention is used, the width of the LDD is 10 to 100.
It is possible to manufacture with an error of about 10% in nm. The fact that L can be finely controlled is based on the fact that it is easy to control the oxidation rate.

Further, according to the present invention, as compared with the conventional LDD manufacturing method, it is not necessary to form an insulating film to serve as a spacer, so that the process is simplified and the productivity is improved.
Hereinafter, the present invention will be described in more detail with reference to examples.

[0028]

EXAMPLES Examples using the present invention will be described. In this embodiment, a complementary MO formed on a single crystal semiconductor substrate is used.
The case where the present invention is used for an SFET device (CMOS) is shown. This embodiment is shown in FIG. First, as shown in FIG. 3A, an n-type well 32, a field insulator 30, a channel stopper (p ⁺ type) are formed on a p-type single crystal silicon semiconductor substrate by using a conventional integrated circuit manufacturing method. 31, n ^-
Type impurity region 34, n ⁺ type impurity region 36, p ⁺ type impurity region 33, p ⁻ type impurity region 35, phosphorus-doped n-type polycrystalline silicon gate electrode 37 (for NMOS)
And 38 (for PMOS) are formed.

The detailed manufacturing method is as follows.
First, BF ₂ ⁺ ions are implanted into a p-type silicon wafer having an impurity concentration of about 10 ¹⁵ cm ^-3 , so-called LOC.
Channel stopper 3 by OS method (local oxidation method)
1 and the field insulator 30 are formed. In addition to this,
Phosphorus ions are implanted and annealed at 1000 ° C. for 3 to 10 hours to diffuse and re-distribute the phosphorus ions to obtain an impurity concentration of 1
An n-type well 32 of about 0 ¹⁶ cm ^-3 is formed.

Thereafter, the thickness is 70 nm by the thermal oxidation method.
Of the gate insulating film (silicon oxide) and a low pressure CVD method to form a polycrystalline silicon film having a thickness of 500 nm and a phosphorus concentration of 10 ²¹ cm ⁻³ , and patterning this to form portions 37 and 38 to be gate electrodes. To form. And
Arsenic ions are implanted to form an n ⁺ type impurity region 36 having an impurity concentration of about 10 ²¹ cm ^−3, and a BF ₂ ⁺ ion is implanted to form ap ⁺ type impurity region 33 having an impurity concentration of 10 ²¹ cm ⁻³ . Then, after that, the n ⁻ -type impurity region 34 having an impurity concentration of 10 ¹⁸ cm ⁻³ is formed again by using a portion to be a gate electrode and another mask if necessary, and BF ₂ ⁺ ions are further implanted, Impurity concentration 10 ¹⁸ c
An m ⁻³ p ⁺ type impurity region 35 is formed. Impurity region 3
The depth of 4 and 35 was 20 nm. Then, these impurity regions are activated by annealing at 900 ° C. for 1 hour to become source and drain regions. In this way, FIG. 3A is obtained.

Next, as shown in FIG. 3B, the portion to be the gate electrode is oxidized by the thermal oxidation method. The oxidation conditions are, for example, 800 ° C. in 1 atmosphere of dry oxygen.
It will be 500 minutes. By this thermal oxidation, a silicon oxide layer 3 having a thickness of about 100 nm is formed around the portion to be the gate electrode.
9 and 40 are formed, and the gate electrodes 41 and 42 remain therein. In this oxidation process, the silicon surface of the portion that should become the gate electrode is recessed by about 50 nm, while the surface of the single crystal silicon substrate is recessed by about 10 nm.
Since the receding is extremely small, the characteristics of the semiconductor element are hardly affected.

Then, again by ion implantation, n ⁺
A p-type impurity region 43 and a p ⁺ -type impurity region 44 are formed. The impurity concentration in each impurity region is 1 × 10 ²¹ cm
^-3 . The depth of this impurity region is 100 n.
m.

Finally, a phosphorous glass layer 45 is formed as an interlayer insulator as in the case of manufacturing a conventional integrated circuit.
For example, a low pressure CVD method may be used to form the phosphorous glass layer. As a material gas, monosilane SiH ₄ , oxygen O _2, and phosphine PH ₃ are used and obtained by reacting at 450 ° C.

After that, holes are formed in the interlayer insulating film for forming electrodes, and aluminum electrodes 46 to 49 are formed. Thus, FIG.
The complementary MOS device as shown in (D) is completed.

[0035]

According to the present invention, L with extremely few restrictions
It has become possible to fabricate a DD type MOSFET. As described in the text, by using the present invention, the LDD is hardly limited by the aspect ratio of the gate electrode.
A region can be formed. Also, the width of the LDD region is 10 to
It can be controlled very precisely between 100 nm.
In particular, the present invention is an effective method for increasing the aspect ratio of the gate electrode, which is expected to progress in the future by shortening the channel.

Of course, it is possible to use the present invention even in a conventional low aspect ratio gate electrode having an aspect ratio of 1 or less, and the formation of an insulating film and its difference compared with the conventional LDD manufacturing method. The effect of the present invention is remarkable because the step of isotropic etching is unnecessary and the width of the LDD region can be precisely controlled.

Although the present invention has mainly been described with respect to a silicon-based semiconductor device, it is obvious that the present invention can be applied to a semiconductor device using another material such as germanium, silicon carbide, gallium arsenide or the like. Further, in the present invention, the oxidation characteristics of the gate electrode play an important role, but in addition to the silicon gate mainly described in the present invention, tungsten, molybdenum, chromium, aluminum, or their silicides, carbides or the like are used as the gate electrode. You may use as. In the embodiment, the MOSFE on the single crystal semiconductor substrate is used.
Although the manufacturing process of T has been described, it is also clear that the present invention can be applied to the manufacturing of a thin film transistor (TFT) using a polycrystalline or single crystal semiconductor film formed on an insulating substrate such as quartz or sapphire. Let's see

[Brief description of drawings]

FIG. 1 shows a method for producing an LDD according to the present invention.

FIG. 2 shows a conventional LDD manufacturing method.

FIG. 3 is a CM on a single crystal semiconductor substrate using the present invention.
A method for manufacturing an OS will be described.

[Explanation of symbols]

11 Gate Electrode 12 Gate Insulating Film 13 n ^- Impurity Region 14 Oxide Layer 15 Gate Electrode 16 n ⁺ Impurity Region

Claims (4)

[Claims] 1. An insulating coating formed on a semiconductor,
Forming a portion to be a gate electrode; introducing impurities into the semiconductor using the portion as a mask to form a first impurity region in a self-aligned manner; and oxidizing at least a side surface of the portion. And a step of introducing an impurity into the semiconductor by using the portion of the gate electrode oxidized in the above step as a mask to form a second impurity region in a self-aligned manner. Method. 2. The method for manufacturing an insulating gate type semiconductor device according to claim 1, wherein the height of the gate electrode is not less than 1 times its width. 3. The method for manufacturing an insulated gate semiconductor device according to claim 1, wherein the impurity concentration of the first impurity region is lower than the impurity concentration of the second impurity region. 4. A step of forming a portion to be a gate electrode made of polycrystalline silicon on an insulating film formed on single crystal silicon, and using the portion as a mask to introduce impurities into the semiconductor, The step of forming the first impurity region in a consistent manner, the step of oxidizing the portion by a thermal oxidation method, and the step of introducing the impurity into the semiconductor by using the portion oxidized in the step as a mask to self-align 2. A method for manufacturing an insulating gate type semiconductor device, comprising the step of forming an impurity region of 2.